MCUs Are Now Embracing Mainstream NoCs

The moral of today’s story is that to succeed in a late-adopter market, sometimes you just have to wait for the market to catch up (assuming you have a strong early adopter market to buy your product today). I have been working with Arteris for 6+ years now promoting their NoC technology, and there was never any question that they offer significant value for design teams building big, complex systems-on-chip connecting multiple IPs through complex networks. Such systems include application processors and, more recently, AI systems for automotive applications. Lower-end designs, commonly MCUs, had been more resistant to the benefits of Arteris technology. But as AI, safety, and security are becoming just as important in MCUs as elsewhere, even MCU design teams are rethinking their earlier strategies.

Evolving MCU demands

Historically, MCUs have served relatively bounded objectives like control units in car engines and home appliances. The architecture was comparably simple: an 8-bit processor, memory, peripherals, timers, counters. One initiator, a few targets, easily satisfied by crossbar switch interconnect. Design support teams often built their own generators for this kind of interconnect. A small number even built their own NoC generators to handle more complex system interconnects.

Now even legacy in-house generators are coming under pressure, in part through competitive and regulatory requirements and in part to meet scalability expectations. AI is everywhere, as much in MCUs as anywhere else to support intelligent sensing. Automation demands for smart homes, cars, cities, factories, all require smart MCUs with communication support. Many must also prioritize safety and security, all at very constrained cost and power demand per unit. Cities and factories planning to deploy thousands of devices want unit prices around a few dollars at most and even lower maintenance costs.

MCUs are growing up to meet these needs; now it’s not always easy to tell where MCUs end and SoCs begin. According to Andy Nightingale (VP Product Management and Marketing, Arteris), MCUs span a long tail beyond SoCs, from complex all the way down to simple devices. Simple MCUs still have their uses where cost is more important than adding features (simple toys or basic home thermostats, for example), but above wherever that breakpoint might be, more functions must be supported on-chip and that invariably requires NoC connectivity.

The drivers to mainstream NoCs

What is motivating change at the simpler end of this MCU range? In part, power reduction. Networks burn power even when there’s no traffic, a fact easy to overlook when concentrating on minimizing power in endpoint IPs. This power component alone can be an important overhead, unless you are using a network like Arteris FlexNoC which supports power domain switching and DVFS within the network.

Safety standards have become another driver. If the MCU is going into any safety-critical application (car, aircraft, industrial robotics, …) you must demonstrate compliance to applicable standards, again as much for the network as for the endpoint IP. Arteris has already done the groundwork against both ASIL B and ASIL D for automotive applications.

At higher complexities, many requirements making NoCs essential in SoC design have become just as relevant in MCU design. Support for multiple protocols (AXI, ACE-lite, ACE, CHI, APB, etc.) is unavoidable in designs using both legacy and 3rd party IP, and acceptable performance for systems with multiple initiators and targets is only possible through the packetization offered by NoCs.

AI accelerators, multicore processors, and again performance are pushing new network topologies: mesh, tree, Clos, even crossbars in some cases, demanding NoC generators with track records to prove support across this range. Meanwhile, network standards continue to evolve. In debug and parametric modeling support for ATB 128-bit trace and now DVM 8.1 have become essential. AMBA 5 now supports “stashing” to improve memory utilization, latencies, and bandwidths, here also requiring support from the NoC generator. High-end goals can only be guaranteed with networks that constantly track these new demands.

For implementation, it is now clear that complex NoC design must be physically as well as architecturally aware right from the outset. Bus widths and serialization options can be optimized early on against rough floorplan concepts and later fine-tuned against realistic floorplans to best optimize area/performance tradeoffs. Just as logical/physical co-design appeared years ago in physical synthesis for block design, now the same need has become unavoidable in full system design.

Strategic planning for scalability

No design is an island, as some reuse expert might have said. What we build today must also factor into tomorrow’s plan for larger or repurposed designs. Or reuse may go in the opposite direction. Auto OEMs may first design a system for the high end of a car range, with intent to deploy the same system or a derated version in lower-end models in the future. In support of these goals, it is necessary to plan for a design infrastructure that can span seamlessly from low-end MCUs to high-end MCUs to SoCs, without need for fundamental network redesign.

Between the intrinsic flexibility of NoC-based networks and physically aware design, Arteris networks can easily span this range (since they are already widely deployed in high-end SoC design flows). Hierarchical NoCs are already as commonplace as hierarchical crossbar switches, so reuse methods are also well-proven. It seems pretty clear that NoC architectures are the way to go for scalability.

You can learn more about Arteris HERE, their non-coherent FlexNoC architecture HERE, and their coherent Ncore architecture HERE.