BannerforSemiWiki 800x100 (2)

Visualizing hidden parasitic effects in advanced IC design 

Visualizing hidden parasitic effects in advanced IC design 
by Admin on 10-15-2025 at 10:00 am

[white paper] Parasitic Analysis Figures

By Omar Elabd

As semiconductor designs move below 7 nm, parasitic effects—resistance, capacitance and inductance—become major threats to IC performance and reliability, often hiding where netlist reviews cannot reach. Design teams need advanced visualization tools like heat maps, layer-based analysis and direct layout… Read More


Podcast EP311: An Overview of how Keysom Optimizes Embedded Applications with Dr. Luca TESTA

Podcast EP311: An Overview of how Keysom Optimizes Embedded Applications with Dr. Luca TESTA
by Daniel Nenni on 10-15-2025 at 8:00 am

Daniel is joined by Luca TESTA, the COO and co-founder of Keysom. After studying microelectronics in Italy, Luca obtained his PhD in France while working with STMicroelectronics on analog/RF circuit design.

Dan explores the charter and focus of Keysom with Luca. Luca describes how Keysom is providing an automated and reliable… Read More


Statically Verifying RTL Connectivity with Synopsys

Statically Verifying RTL Connectivity with Synopsys
by Bernard Murphy on 10-15-2025 at 6:00 am

TestMAX Advisor Use Model min

Many years ago, not long after we first launched SpyGlass, I was looking around for new areas where we could apply static verification methods and was fortunate to meet Ralph Marlett, a guy (now friend) with extensive experience in DFT. Ralph joined us and went on to build the very capable SpyGlass DFT app. So capable that SpyGlass… Read More


Assertion IP (AIP) for Improved Design Verification

Assertion IP (AIP) for Improved Design Verification
by Daniel Payne on 10-14-2025 at 10:00 am

Detailed flow min

Over the years design reuse methodology created a market for Semiconductor IP (SIP), now with formal techniques there’s a need for Assertion IP (AIP). Where each AIP is a reusable and configurable verification component used in hardware design to detect protocol and functional violations in a Design Under Test (DUT).  LUBIS … Read More


Secure-IC and Silicon Labs Raise the Bar for Hardware Security

Secure-IC and Silicon Labs Raise the Bar for Hardware Security
by Mike Gianfagna on 10-14-2025 at 8:00 am

Secure IC and Silicon Labs Raise the Bar for Hardware Security

Cybersecurity is getting more critical every day. Thanks to sophisticated AI attacks, the need for hardware chip-level security is greater than ever. To fortify hardware against these types of attacks is not easy. There are three key attributes of a successful strategy: a well-designed root-of-trust, collaboration to ensure… Read More


Why Choose PCIe 5.0 for Power, Performance and Bandwidth at the Edge?

Why Choose PCIe 5.0 for Power, Performance and Bandwidth at the Edge?
by Kalar Rajendiran on 10-14-2025 at 6:00 am

PCIe 5.0 Impact Across Markets

Synopsys recently held a webinar session on this topic and Gustavo Pimentel, Principal Product Marketing Manager at the company led the webinar session. Going into the webinar session, I found myself wondering: why focus on PCIe 5.0, eight years after its release? With the industry buzzing about Edge AI, cloud computing, and … Read More


Protect against ESD by ensuring latch-up guard rings

Protect against ESD by ensuring latch-up guard rings
by Admin on 10-13-2025 at 10:00 am

fig1 latchup event

By Mark Tawfik

Overview: Protecting ICs from costly ESD and latch-up failures

Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].

Ensuring the robust protection of integrated circuits (ICs) against various… Read More


The 2025 Semi Industry Forum: On the Road to a $1 Trillion Industry

The 2025 Semi Industry Forum: On the Road to a $1 Trillion Industry
by Daniel Nenni on 10-13-2025 at 6:00 am

image (1)

The global semiconductor industry stands at a defining moment in its history. Having surpassed $600 billion in annual revenue, the path to a $1 trillion market is no longer a distant dream but an achievable milestone within the next decade. The annual 2025 Semi Industry Forum, organized by Silicon Catalyst, brings together the… Read More


Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools

Selling the Forges of the Future: U.S. Report Exposes China’s Reliance on Western Chip Tools
by Daniel Nenni on 10-12-2025 at 10:00 am

Employees are seen working on the final assembly of ASML's TWINSCAN NXE:3400B semiconductor lithography tool with its panels removed, in Veldhoven

The U.S. House Select Committee on the Strategic Competition Between the United States and the Chinese Communist Party released a bombshell report titled “Selling the Forges of the Future” on October 7, 2025, detailing how the People’s Republic of China is stockpiling semiconductor manufacturing equipment… Read More


SEMICON West AZ- Congress & China- Memory Madness- AI Semiconductor Tsunami

SEMICON West AZ- Congress & China- Memory Madness- AI Semiconductor Tsunami
by Robert Maire on 10-12-2025 at 8:00 am

Semicon West Phoenix 2025

– First SEMICON in Arizona was great- should make it permanent
– Congress finally wakes up to China issues long after cows are gone
– Memory cycle in support of AI could be huge but scary at same time
– AI demand seems bottomless- but may distort chip industry dynamics

Phoenix SEMICON was wonderful!

The crowds… Read More