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Can RISC-V Help Recast the DPU Race?

Can RISC-V Help Recast the DPU Race?
by Jonah McLeod on 08-26-2025 at 10:00 am

Can RISC V Help Qualcomm

ARM’s Quiet Coup in DPUs

The datacenter is usually framed as a contest between CPUs (x86, ARM, RISC-V) and GPUs (NVIDIA, AMD, custom ASICs). But beneath those high-profile battles, another silent revolution has played out: ARM quietly displaced Intel and AMD in the Data Processing Unit (DPU) market.

DPUs — also called SmartNICs… Read More


Breaking out of the ivory tower: 3D IC thermal analysis for all

Breaking out of the ivory tower: 3D IC thermal analysis for all
by Admin on 08-26-2025 at 6:00 am

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Todd Burkholder and Andras Vass-Varnai, Siemens EDA

As semiconductor devices become smaller, more powerful and more densely integrated, thermal management has shifted from an afterthought to a central challenge in modern IC design. In contemporary 3D IC architectures—where multiple chiplets are stacked and closely arrayed—power… Read More


Intel’s Pearl Harbor Moment

Intel’s Pearl Harbor Moment
by Daniel Nenni on 08-25-2025 at 10:00 am

Pearl Harbor Memorial Hawaii

There is a lot of talk about where Intel went wrong, the latest is missing AI, but people seem to forget one of the more defining blunders in the history of Intel. In April of 2012 Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Mark Bohr, a 33+ year Intel fellow, and Brad Heaney, the Ivy Bridge… Read More


A Big Step Forward to Limit AI Power Demand

A Big Step Forward to Limit AI Power Demand
by Bernard Murphy on 08-25-2025 at 6:00 am

Power estimation

By now everyone knows that AI has become the all-consuming driver in tech and that NVIDIA GPU-based platforms are the dominant enabler of this revolution. Datacenters worldwide are stuffed with such GPUs, serving AI workloads from automatically drafting emails and summarizing meetings to auto-creating software and controlling… Read More


Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook

Free and Open Chip Design Tools: Opportunities, Challenges, and Outlook
by Admin on 08-24-2025 at 10:00 am

OPen EDA Ecosystem 2025 SemiWiki

Designing semiconductor chips has traditionally been costly and controlled by a few major Electronic Design Automation (EDA) vendors—Cadence, Synopsys, and Siemens EDA who dominate with proprietary tools protected by NDAs and restrictive licenses. Fabrication also requires expensive, often export-controlled equipment.… Read More


Chiplets: providing commercially valuable patent protection for modular products

Chiplets: providing commercially valuable patent protection for modular products
by Robbie Berryman on 08-24-2025 at 6:00 am

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Many products are assembled from components manufactured and distributed separately, and it is important to consider how such products are manufactured when seeking to provide commercially valuable patent protection. This article provides an example in the field of computer chip manufacture.

Chiplets

A system-on-a-chip

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Podcast EP304: PQC Standards One Year On: The Semiconductor Industry’s Next Move

Podcast EP304: PQC Standards One Year On: The Semiconductor Industry’s Next Move
by Daniel Nenni on 08-22-2025 at 10:00 am

Dan is joined by Ben Packman, Chief Strategy Officer of PQShield. Ben leads global expansion through sales and partner growth across multiple vertical markets, alongside taking a lead role in briefing both government and the supply chain on the quantum threat. He has 30 years of experience in technology, health, media, and telecom,… Read More


WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design

WEBINAR: Functional ECO Solution for Mixed-Signal ASIC Design
by Daniel Nenni on 08-22-2025 at 6:00 am

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This webinar, in partnership with Easy-Logic Technology, is to address the complexities and challenges associated with functional ECO (Engineering Change Order) in ASIC design, with a particular focus on mixed-signal designs.

The webinar begins by highlighting the critical role of mixed-signal chips in modern applications,… Read More


Taming Concurrency: A New Era of Debugging Multithreaded Code

Taming Concurrency: A New Era of Debugging Multithreaded Code
by Admin on 08-21-2025 at 10:00 am

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As modern computing systems evolve toward greater parallelism, multithreaded and distributed architectures have become the norm. While this shift promises increased performance and scalability, it also introduces a fundamental challenge: debugging concurrent code. The elusive nature of race conditions, deadlocks, Read More


Perforce Webinar: Can You Trust GenAI for Your Next Chip Design?

Perforce Webinar: Can You Trust GenAI for Your Next Chip Design?
by Mike Gianfagna on 08-21-2025 at 6:00 am

Perforce Webinar Can You Trust GenAI for Your Next Chip Design?

GenAI is certainly changing the world. Every day there are new innovations in the use of highly trained models to do things that seemed impossible just a short while ago. As GenAI models take on more tasks that used to be the work of humans, there is always a nagging concern about accuracy and bias. Was the data used to train the model … Read More