Senior Staff Engineer I – VLSI
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Website Alphawave Semi
What You’ll Do
- Deliver standards-compliant IP blocks for use in UCIe / PCIe / CXL / HBM.
- Lead ASIC or FPGA projects.
- Refine ASIC development process with advancing tools/scripting.
- Creating micro-architecture and detailed design documents for design keeping in mind performance, power, area requirements.
- Perform RTL coding for complex design blocks in Verilog.
- Function/performance simulation check and debug.
- Understanding on Lint/CDC/Synthesis checks, power analysis and LEC check.
- Understanding and defining constraints.
- Issue and track bug reports from beginning to closure.
- Work with the team to deliver quality designs.
- Work very closely with verification and back-end team.
- Mentor junior engineers.
What You’ll Need
- B.E/M. Tech with 10+ years of experience in ASIC or FPGA development.
- Protocol knowledge (UCIe, PCIe, CXL, HBM, AMBA SoC bus Protocols).
- Solid experience with Verilog and System Verilog.
- Experience with Lint, CDC, Synthesis, Power analysis, and LEC tools.
- Experience with simulation tools.
- Experience in ASIC tape outs is plus.
- Experience in UCIe / PCIe / CXL.
- Experience with PERL, TCL, and Python programming.
“Hybrid work environment”
As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes:
- Competitive Compensation Package
- Restricted Stock Units (RSUs)
- Hybrid Working Model
- Provisions to pursue advanced education from Premium Institute, eLearning content providers
- Medical Insurance and a cohort of Wellness Benefits
- Educational Assistance
- Advance Loan Assistance
- Office lunch & Snacks Facility
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