Standard cell optimization is an important problem, because the speed, power, and area of cells has a direct impact speed, power, and area of the whole chip. Typically, standard cell optimization been done with simple in-house local-optimizer scripts. However, these optimizers have had several flaws: they don’t properly capture the variation, they get stuck in local optima, and they are serial and wasteful of simulations. The result is circuits with suboptimal power, speed, and area; from a design process that took longer than necessary.
At TSMC’s recent OIP Symposium (October 1, 2013), Solido Design Automation exhibited and had a paper about a new approach to standard cell optimization, which addresses these issues and is being used in production with leading TSMC customers. There are two keys to this: a world-class global optimizer, and an appropriate design flow. We now discuss each further.
The figure below left elaborates on the issues of previous local script-based optimizers. Below right describes how Solido Cell Optimizer overcomes these issues.
To be efficient at global optimization, Solido Cell Optimizer uses nonlinear regression models to data-mine all previous simulations, and efficiently choose new simulations. Unlike many script-based approaches, the Cell Optimizer can optimize across any number of testbenches, any number of corners, and fully exploits parallel processing.
The second key is a flow that handles variation quickly and accurately. It turns out that we can actually preserve the well-known corner-based design flow. Only now, corners are better: they capture the bounds of the circuit performances rather than device performances. Given that standard cells need failure rates of 1/1M or less, then to properly capture the variation without needing millions of simulations, we use Solido High-Sigma Monte Carlo (HSMC). The steps in the flow are: (i) extract high-σ corners using Solido HSMC, (ii) optimize on those corners using Solido Cell Optimizer, and (iii) verify to high-σ using Solido HSMC. This flow accurately captures variations, while still enabling rapid iterations of sizing variables. The figure below illustrates.
The figure below shows the flow in practice, on a flip flop. The right side shows the first step, where Solido HSMC was run, returning the high-sigma tail distribution (in red), and along with it, a 5-sigma corner for setup time. Then, Solido Cell Optimizer was run, to minimize setup time. Finally, Solido HSMC was re-run, to characterize and verify the final design.
Mutual Solido and TSMC customers have been using this flow, which combines Solido Cell Optimizer and Solido HSMC, in various cases, including:
- Efficiently optimizing a bitcell design for optimal read margin and write margin simultaneously, using a different testbench for each measurement. This is for both nominal and high-sigma variation conditions. The bitcell design is in both 20nm and 16nm.
- Tuning, porting, retargeting, and migrating large standard cell libraries, to support a large designer base. This task is extremely time consuming and simulation intensive to do manually. Furthermore, these cells need to be optimized to work well under high-sigma conditions. Technologies used include 16nm, 20nm, and 28nm.
- In a large library of standard cells, while all of the cells perform well under nominal conditions, identifying which cells fail under high-sigma conditions and automatically fixing them via resizing.
In summary, mutual Solido and TSMC customers have been exploiting the benefits of a new flow for high-sigma standard cell optimization. Through the combination of Solido Cell Optimizer and Solido High-Sigma Monte Carlo, the flow properly captures variation, provides globally optimal results, doing so in an extremely efficient fashion.
For more information, visit www.solidodesign.com.