Design Technology CoOptimization at SPIE 2020

SLiC Library tool dramatically accelerates DTCO for 3nm and beyond

In advanced technology nodes below 10nm, Design and Process Technology development have become increasingly intertwined. In older nodes the traditional technology roll-out was done mostly in a sequential manner with clear geometry scaling targets set by process technology and then handed down to designers, determining the resulting scaling of area, power and performance.

This is no longer the case: Nowadays and going forward there are too many choices to be made between different materials, different patterning options, different device structures and different library architectures. The impact of each combination of variables and choices on design capabilities and performance is impossible to intuitively estimate or quantify.

In addition, the DTCO analysis needs to go beyond the device or library level. For example, a seemingly tighter library can prove to be very hard to place and route, causing routing congestion that would make it effectively much worse than a more relaxed library architecture. Effective DTCO today requires a feedback loop and negotiations between technology and design, and the assessment loop encompasses the entire flow: from technology capabilities and limitations, to logic cells, to placement and routing and analysis at the block level, and back.

As seen in the above diagram, the centerpiece of this flow is the standard cell library. Developing a DTCO flow requires having a representative compact logic library that has frequently used logic building blocks (usually less than 200 cells would do). To accomplish an effective and streamlined flow one needs to be able to quickly create variants of this library and use them to implement a few logic designs or blocks that are characteristic to the specific target markets and product applications. Each implementation is analyzed for performance, power, area and cost (PPAC) and is evaluated against other technology and library architecture variants.

DTCO flow bottleneck and the SLiC solution
The DTCO flow must be quick and streamlined to evaluate multiple technology and architecture choices in a reasonable time. Most of the steps (e.g. synthesis, P&R) are automated but creating the library has been the bottleneck of this flow until recently. This critical gap has now been filled by SLiC (Standard-cell Library Compiler), a new tool that solves this problem by automating library creation and cutting the library physical design time from months to less than a day. SLiC has been recently introduced by Sage Design Automation and has proven extremely efficient, creating libraries very quickly with optimal results that are as good and sometimes better than handcrafted.

Unlike past generations of library creation or migration tools, setting up each new technology for SLiC takes less than a day and the run time is measured in hours. SLiC was designed from the ground up for new and advanced technologies. Its inherent versatility accommodates novel devices and logic design concepts including LGAA, CFETs and even more exotic 3D structures and cell architectures.  SLiC has already been used and proven in both DTCO and production flows for 7nm, 5nm, 4nm technologies and 3nm pathfinding DTCO work.

Summary
Standard cell libraries are at the center of the process technology and design development for advanced nodes. SLiC enables very quick creation of optimal quality libraries that can be used both for production in advanced nodes and for pathfinding DTCO of future technologies.

Come and see SLiC at SPIE:   SLiC will be presented at the SAGE-DA booth #103 on the exhibit floor at the 2020 SPIE Advanced Lithography Conference in San Jose (Feb 25th-26th). You are also encouraged to attend the paper “DTCO acceleration to fight scaling stagnation” (Paper 11328-11), showing advanced DTCO work done using SLiC.

https://www.sage-da.com