MIPS Warrior Goes Into Battle

You are probably aware that Imagination Technologies, perhaps most well known for creating the GPU that is in the iPhone and iPad, acquired MIPS, which was originally a spinout from Silicon Graphics and licenses a line of general purpose microprocessors.

MIPS considers that they have a purer implementation of the RISC philosophy built around the fact that simple instructions provide higher performance. An interesting experiment from way back when was when IBM took the PL/I compiler for the IBM 801 (the first RISC microprocessor, why on earth did they not put it in the first PC?) and retargeted it to the IBM 360 architecture. Since the compiler didn’t have the concept of complex instructions, or accessing memory except by a load or store instruction, it actually used a small subset of the IBM 360 instructions. Nonetheless, it turned out to run code faster than the industrial strength PL/I compiler designed for the IBM 360 that took advantage of the entire instruction set. RISC won even on a very CISC architecture.

The result of this pure implementation is that MIPS have a higher CoreMark/MHz than the competition and uses only 60% of the area. So a superior performance/area. CoreMark is a much better benchmark than the old Dhrystone benchmark with about 700,000 instructions versus 350. It stresses CPU’s branch prediction and L1 cache performance in a way that Dhrystone never did. It is much closer to a modern workload. By the way, an interesting little story on the Dhrystone name. There was a floating point benchmark called Whetstone named after the town in England where it was developed. So when a fixed point benchmark was created, the obvious name was Dhrystone, a play on words wet/dry plus the odd extra inserted “h”.

This means that a MIPS proAptiv design can fit a quad core into the same area as other competitors can fit a dual core, achieving a CoreMark score over twice as high in the same area.

interAptiv is a smaller less power hungry core with in-order execution. It supports multi-core and coherent caches, it is also multi-threaded. Its focus is supporting Linux and other embedded operating systems. Then, for really minimal area there is microAptiv, with a 5-stage pipeline that optimizes PPA. It has performance/area over 45% more efficient that its main competito and much higher DSP performance.

Today MIPS have announced the interAptiv single core CPU IP designed for small footprint parallel processing intensive applications such as networking, baseband, protocol processing. It has a smaller area and lower dynamic power consumption. It removes the extra logic associated with multi-core coherency, and the L2 cache-controller so providing a very efficient multi-threaded single core processor.

Features include:

• MIPS multi-threading
• Extended Virtual Addressing (EVA)
• ECC on L1 cache and scratchpad RAM
• DSP Application Specific Extensions rev 2, eliminating need for separate DSP for voice and audio
• Un-Cached Accelerated (UCA) writes

An example is building an LTE stack (true 4G wireless) using a multi-threaded core with optimized baseband stack and a multi-thread aware RTOS. This delivers multicore performance in the area/power envelope of a single core. The multithreading gives a performance boost of up to 2X versus single thread.

MIPS also gave a sneak preview of the future. First there were the classic MIPS cores, then the Aptiv cores, and next will be the Series5 Warrior series of cores. These will have:

• hardware virtualization across the entire range of cores, providing compelling benefits for applications from compute-intense enterprise environments to energy efficient mobile platforms
• MIPS hardware multi-threading technology, enabling better overall throughput, quality of service (QoS), and power/performance efficiency in select ‘Warrior’ cores
• Imagination’s unique, extensible and highly scalable security framework for applications including content protection on mobile devices, secure networking protocols and payment services
• MIPS SIMD architecture (MSA), built on instructions designed to be easily supported within high-level languages such as C or OpenCL for fast and simple development of new code, as well as leverage of existing code
• a consistent and comprehensive toolchain across the ‘Warrior’ series for fast, easy development and debugging
• full compatibility with existing legacy 32-bit and 64-bit code