SemiWiki – Page 941 – The Open Forum for Semiconductor Professionals

May 24, 2012June 14, 2019

3D Transistors and IC Extraction Tools

Have you ever heard of a Super Pillar Transistor? It’s one of many emerging 3D transistor types, like Intel’s popular FinFET device.

In the race to continuously improve MOS transistors, these new 3D transistor structures pose challenges to the established IC extraction tool flows.

Foundries have to provide an Effective Profile to EDA companies that describes the shapes used to fabricate any MOS device plus all of the interconnect levels. TCAD tools can be run to simulate what the shapes of an effective profile should be.

How can foundries keep their process proprietary yet provide a geometry for extraction tools to actually use?

Now that’s a constant challenge. I met with Carey Robertson of Mentor Graphics to better understand how the challenges of 3D transistors are being met with the latest generation of IC extraction tools like Calibre xACT 3D.

Q: Intel has an early lead in production-ready 3D FinFETs. When will the Foundries offer FinFETs?
A: The foundries are saying that FinFETS will be used at the 14nm node, however there is much speculation that we could see FinFETS at the 20nm node.

Q: How does a 3D transistor effect the job of IC extraction?
A: The complexity of the effective profile is always increasing, so we have to use more elaborate 3D models that in return require more processing time for detailed extraction used by memory and analog designs.

Q: Will rule-based methods be sufficient in IC extraction?
A: Only for the M1 and higher interconnect layers, for the lower layers near the MOS device you need to really use a field solver to get the accuracy.

Q: How is extraction changing now with 3D?
A: Before we could have a wide distinction between interconnect models and transistor models for parasitics. Now we are using a 3D field solver to extract the R and C values for the MOS source and drain connections.

With 3D devices the MOSFET can even be broken up into multiple fins. We are moving from a table-based and rule-based extraction approach, to explicit calculations. These calculation are just more computational and require longer run times.

Q: What is different about Mentor’s 3D field solver?
A: Our tool is called xACT 3D and is a field-solver used by designers and is well suited for FinFETS and 3D devices. Caliber xACT 3D has a deterministic field solver (similar to Raphael in the past, although faster), and the output is a SPICE netlist. The extraction input is a GDS II file and foundry decks, so it feels like a standard extraction tool.

The old Raphael was 1,000x slower than rule-based approaches so is limited to TCAD and small transistor counts.

xACT 3D is maybe 3 to 4x slower than rule-based solvers, however to get results faster you can add more hardware and still stay within 2% of TCAD tool results.

Q: What is the capacity of your 3D field solver?
A: xACT 3D has been run on multi-million transistor memory layouts (see the STARC paper at DAC), flat. It’s not meant for digital sign off. If you want to send the most accurate netlist to SPICE or Fast SPICE for circuit simulation then xACT 3D is the tool for you.

If you want to analyze multi-million digital gates into PrimeTime, then consider a selected net flow.

Q: What is new with xACT 3D this year compared to last year?
A: Well, we have performance improvements (memory up to 4X, analog about 1.5X to 2X), foundry decks at 20nm, more foundry support, plus faster and better viewing of results.

Q: Who would be interested in using a 3D field solver?
A: Memory designers using pillar transistors would need to use a field solver.

Q: Does your field solver work hierarchically?
A: No, it’s not a hierarchical tool although it can read a hierarchical layout and produce a hierarchical netlist.

Q: Will you be presenting at DAC this year?
A: We may be in a panel discussion organized by Ed Sperling, so stay tuned.

Q: What are some other trends happening in IC design today?
A: With Double Pattern Technology (DPT) being used at 20nm it is creating more corners for simulation, so at 28nm we had 5 corners and at 20nm we will have from 11 to 15 corners. More corners means more simulation time.

Q: Who else at Mentor is presenting at DAC this year?
A: Claudia Relyea is presenting with ST in a poster session on 3D extraction.

Karen Chow has a presentation on sensitivity analysis with STARC.

Summary
The DAC conference and trade show is going to be exciting this year as the EDA vendors have adapted their IC design tools to enable design with 3D transistors. Find Mentor Graphics in booth #1530 at DAC.

May 24, 2012June 14, 2019

Solido Design Automation Update 2012

Solido Design Automation Update 2012
by Daniel Nenni on 05-24-2012 at 10:27 am
Categories: EDA, Solido

Having spent a considerable amount of time with Solido, they were one of the founding members of SemiWiki, I can tell you that at 20nm the Variation Designer Platform is a critical part of the emerging 20nm design methodology. You can read more on Solido’s SemiWiki landing page HERE. It is well worth the click.

With technology rapidly going mobile, demand is driving IC development to high-integration, higher-performance at lowest power, a competitive cost, and still in time to meet market demands. In creating these SoCs at the leading edge, process nodes increased variability is a serious risk. Solido is THE leading solution provider to derisk variation, providing maximum yield at the performance edge, with specific solutions for memory, standard cell, low power and analog/RF design.

You can tell a lot about a company by their DAC content. For a relatively small company Solido is delivering a very big value proposition:

Solido Variation Designer Memory+ is used for memory design to achieve maximum yield on high-performance designs. Solido will demonstrate how Memory+ runs the billions of Monte Carlo samples needed for high-sigma (up to 6-sigma) verification of bit cells and sense amps, giving fast and accurate visibility into the increasing effects of variation on design in nanometer technologies. Using the industry-standard simulators commonly used in memory design to achieve SPICE-accurate results, Memory+ is fast enough for use in the design loop. Memory+ will be demonstrated both from the command line and from a graphical environment.

Solido Variation Designer Standard Cell+ delivers the highest-quality standard cell libraries in less time. Solido will demonstrate how Standard Cell+ optimizes a library of cells across the increasingly significant variation effects in nanometer technologies, allowing efficient migration of a standard cell library to a smaller process node or second source. Attendees will see how to leverage Solido’s meta-simulation technology to enhance standard SPICE simulation and manage performance-yield tradeoffs. Operating at the command line for full batch operation, Standard Cell+ is also used as an environment for design debug and results visualization.

Solido Variation Designer Low Power+. To minimize power in today’s portable devices, numerous power states in SoCs need to be considered and verified against thousands of corner cases. Solido will demonstrate how its Low Power+ uses Fast PVT meta-simulation technology, delivering a typical 2x-10x productivity gain in design verification coverage across power states, PVT corners, and layout RC corners. Attendees will see how Low Power+ actively finds and simulates only the worst-case corners while providing predictive results for non-worst-case conditions, giving full coverage at a fraction of the simulation cost.

Solido Variation Designer Analog+. Solido will demonstrate how its Analog+ product builds on the well-established Cadence® Virtuoso® Custom Design Platform to delivers simulation efficiency and design closure against worst-case PVT corners and extracted 3-sigma statistical corners. Analog+ delivers a 10x average efficiency increase for PVT signoff, more consistent Monte Carlo analysis with multiple stop-on-yield criteria, fast extraction of statistical corners at a target sigma, and efficient, intuitive, interactive design sizing. All capabilities provide extensive visualization and debug to assist in efficiently achieving high-yielding designs.

You can sign up for a Solido DAC meeting HERE. Send me a note and I will meet your there!

May 24, 2012June 14, 2019

Analog FastSPICE added to Tanner EDA

Analog FastSPICE added to Tanner EDA
by Daniel Payne on 05-24-2012 at 10:18 am
Categories: EDA, Tanner EDA
9 Comments

Last year when I visited Tanner EDA at DAC I heard about how they integrated the Analog FastSPICE circuit simulator from Berkeley DA.

This made sense to me because BDA has a good reputation for speeding up SPICE without compromising on accuracy, and Tanner users may want to mix and match tools from multiple EDA vendors.

This year they’ve taken that technical integration one step further by having an OEM agreement, where Tanner EDA sells and supports a version of the BDA Analog FastSPICE simulator.

As a Tanner EDA user there are a couple of SPICE simulation choices now:

T-SPICE
Analog FastSPICE

For small circuit sizes or short simulation runs the T-SPICE simulator should work out just fine however for larger circuit sizes or longer simulation runs then consider using Analog FastSPICE instead to get your simulation results quicker.

DAC
If you’re traveling to SFO in June for the DAC show then sign up for Tanner EDA at booth #1126to see demos on:

Analog design suite – now with support for Open Access
Analog FastSPICE
Layout generators
T-SPICE plus HDL simulation using Aldec Riviera PRO
Static Timing, Logic Synthesis, P&R
MEMS tools

My Futures
I know that you can simulate HDL plus T-SPICE today however I’d like to see:

A single waveform viewer instead of two
Co-simulation including Analog FastSPICE and HDL

May 24, 2012June 14, 2019

Network on Chip in Automotive: Arteris

Network on Chip in Automotive: Arteris
by Eric Esteve on 05-24-2012 at 9:20 am
Categories: Arm, Arteris, IP

The recent announcement from Arteris that iC-Logic chose FlexNoC and C2C to create a flexible and high speed communication chip to respond to the increasing demand of high speed connectivity in car infotainment systems is very interesting, as it shows that SoC designed for the Automotive market segment also require advanced IP functions which are widely used in the most advanced SoC, like application processor for smartphone or multimedia controller for Set-Top-Box. These chips from IC-Logic are supporting the infotainment segment in automotive, not the motor control, and will be used in the passenger cell, nevertheless, it’s significant to see complexes functions like NoC being used in the automotive segment, usually closer to the military or aeronautic segments than to the consumer electronic or wireless handset!

Let’s listen to the reasons why IC-Logic has selected Arteris FlexNoc and inter chip communication C2C IP: “iC-Logic licensed Arteris FlexNoC and C2C because we needed fast design cycle time and full compatibility with other SoCs. FlexNoC’s ease of use and integrated simulation and verification features helped us to optimize our SoC integration and development time,” said Martin Damrau, Managing Director at iC-Logic. “And our choice of the C2C chip to chip interconnect IP ensures our compatibility with application processors using C2C. Thanks to the collaboration with Arteris, iC-Logic added C2C integration expertise to our skill set enabling us to quickly design SoCs with this sophisticated interface.”

Just a remark: C2C is a technology initially developped by Texas Instruments… like OMAP is the flagship SoC family from TI, initially developed to support smartphone and media tablet applications.

If we look at first at C2C, and remember –or take a look at- the blog from Kurt Shulerabout the various high speed interface protocols currently used in the wireless handset (and smartphone) IP ecosystem, and cross this information with the above comment made by Martin Damrau, we realize that IC-Logic integrates C2C to ensure their chip compatibility with application processors using C2C. I have no insight information, but I would bet that this application processor could be OMAP platform from TI! If you replace the “cellular modem” chip by the chip designed by IC-Logic, that means that the system integrator could get the same benefit in automotive infotainment than in smartphone: share the same memory device between the application processor and the SoC designed by IC-Logic, and consequently save the cost of one memory devices.

Even if the production volumes in automotive are not the same than in wireless handset, these volumes are in the million units range, per year, and longevity is a lot longer: five to ten years to be compared with a dozen months. Using C2C can help to save several million of dollar during the product life. And, from a pure technical standpoint, C2C is a low latency (100 ns for a round trip), high bandwidth chip to chip connection link, allowing supporting gigabit per second range for data exchange based on standard parallel I/Os (LPDDR1 or 2) so you don’t need integrating (and acquiring the license of) SerDes based high speed PHY like MIPI M-PHY if you would use USB SSIC or MIPI LLI.

Using a chip to chip connection link to exchange data and benefiting from Bill Of Material (BOM) cost reduction makes sense, whichever the market segment your chip is serving. But I remember, back in 2006, not that long ago, that NoC was considered as a rocket science type of function, reserved for the most complexes SoC. In other words, only a few people understood how it worked! Seeing NoC being used in market segment like automotive, where the chip architect have to carefully select the function to be implemented, simply because the time to market is a lot longer than in consumer like segment, as well is the production period (five to ten years is common), is a strong sign about the democratization of the NoC. Which is very good for Arteris, and for existing Arteris’ customers, as this means that the technology is here to stay!

According with the Press Release from Arteris, iC-Logic chose FlexNoC and C2C to create a flexible and high speed communication chip to respond to the increasing demand of high speed connectivity in car infotainment systems. iC-Logic’s use of FlexNoC and C2C has helped reduce design schedules and increased the potential market for users of their SoC. “iC-Logic’s use of Arteris FlexNoC and C2C interconnect IP for its high speed communication SoC is an innovative way to reduce SoC time to market and grow the market size for application processor SoCs,” said K. Charles Janac, President and CEO of Arteris.

Eric Esteve from IPNEST

May 24, 2012June 14, 2019

After Planning Comes Implementation for Pulsic

After Planning Comes Implementation for Pulsic
by Paul McLellan on 05-24-2012 at 7:00 am
Categories: Uncategorized

Automation for digital design has been mainstream for a couple of decades but place and route for analog is still in its infancy. Many attempts have been made over the years to automate analog design in one way and another, the bodies are piled up on the hillside. Much analog design is still largely done with custom layout and circuit simulation. Analog design will probably never be automated in the same way as digital design, partially because analog designers have expertise that needs to get incorporated into the design, and partially because analog designs are often small enough that it is reasonably to partially hand-craft it, which is obviously not the case with a block of few million standard cells. But analog designs are getting larger and the process restrictions more complex meaning that a purely manual approach doesn’t scale.

Last year at DAC Pulsic announced the Pulsic Planning Solution. After planning comes implementation so this year at DAC Pulsic is announcing the Pulsic Implementation Solution providing designers with easy-to-use, guided flows to automatically implement precise, hand-crafted quality design layouts.

The products that make up the Pulsic implementation solution are the Unity Analog Router, the Unity Custom Digital Router and the Unity Custom Digital Placer. Pulsic’s customers have been running into the bottlenecks of analog and custom digital design. Throwing more engineers at the problem is not a solution, and using regular digital place and route isn’t able to handle the delicate issues in custom digital and analog design that require shielding, matching two halves of the design and so forth.

The constraint drive shape-based routing technology, based on over 200 man-years of experience in analog routing has led to a flow focused on the specific needs of analog designers to create precision routes at hand-crafted quality. The weakness of many analog solutions is that creating the constraints to drive the tools is an enormous task that doesn’t really scale any better than handcrafting the design. But proprietary geometry recognition algorithms mean that minimal set up and tool knowledge is required. There is full support for features such as mirrors, symmetry, common centroid and current density limits. The designer retains full control and can use the router interactively or automatically.

Under the hood, there is a tightly integrated suite of shape-based routing technologies. The router encompasses hundreds of specialized utilities that work together simply on the same shape-based data model to give custom digital design teams precise, handcrafted quality results with automated speed. It has been engineered to work with the latest complex process rules (28nm and below) and makes efficient use of available area, even for areas with extreme aspect ratios or high congestion.
More details are here.

May 23, 2012December 27, 2023

Software-based Wi-Fi: DSP IP core

Software-based Wi-Fi: DSP IP core
by Eric Esteve on 05-23-2012 at 10:05 am
Categories: Ceva, IP

The recent announcement from CEVA that it has joined the Wi-Fi Alliance® to further advocate for a software-based Wi-Fi® strategy shows that the new CEVA-XC4000 DSP can be used in various communication protocols, not limited to the traditional baseband processing for the wireless handset phone, where DSP IP core usage is massive. This follows on from the company’s recent announcement of a new software-based, reference architecture targeting multi-mode Wi-Fi 802.11 mobile stations (STA) and access points (AP) together with partner Antcor, S.A. CEVA’s Wi-Fi reference architecture is based on the new CEVA-XC4000 DSP architecture framework and is ideal for cost-efficient, ultra-low power applications.

If you look at the various challenges that chip makers are facing today in the market segments exhibiting the higher growth, wireless handset or media tablet for example, you realize that time-to-market is probably the most crucial. These segments are consumer oriented, the end user behavior relatively to a new product can have a stronger than ever impact on companies turnover and generate a new deal, just look at what has happened to respected OEM like Nokia or RIM within a couple of years only, simply because they did not properly “smell” their customers behavior, and have been a little too slow to react… In this environment, being able to reduce development time and minimize risk by choosing software based solution whenever it’s possible from a technical standpoint, preserving a great user experience, should be the best approach for a chip maker who need to launch a new product as fast as possible.

“The advent of the next generation of Wi-Fi standards including 802.11ac poses new challenges for the development of multi-standard, high performance Wi-Fi enabled SoCs,” said Eran Briman, vice president of marketing at CEVA. “The continuous evolvement of these standards together with greater processing requirements dictates a new silicon design approach that will enable semiconductor companies to reduce development time, minimize risk and also extend product’s life-cycle. CEVA believes that a software-based Wi-Fi approach based on the CEVA-XC4000 DSP architecture framework is the optimal way to address both the performance and flexibility issues with current hardwired designs and we look forward to sharing our expertise in this area with the Wi-Fi Alliance and its members.”
Reference architectures highlights:

Addresses both PHY and Lower-MAC with minimal complementary hardware acceleration
Built around a single CEVA-XC4210 processor with minimal complementary hardware accelerators
Offers industry’s most competitive SDR platform in terms of both cost and power consumption
Supports up to full 160MHz channel bandwidth
Maximal throughput of 867Mbps (scalable to 1.7Gbps) with up to 4×2 MIMO beam-forming, with 256-QAM support
Extremely low power solution targeting low power process for mobile Wi-Fi stations (STA)
High operating margins enabling customer differentiation by software

“We congratulate CEVA, Inc. on becoming a member of Wi-Fi Alliance,” said Edgar Figueroa, CEO of Wi-Fi Alliance. “By joining our organization, CEVA has demonstrated its commitment to advancing Wi-Fi technology while preserving a great user experience.”

The CEVA-XC4000is a fully programmable low-power DSP architecture framework supporting the most demanding communication standards including LTE-Advanced, LTE and HSPA+, alongside Wi-Fi, DTV demodulation, white space, smart grid and more. The CEVA-XC4000 architecture is offered in a series of six fully programmable DSP cores, offering modem developers a wide spectrum of performance capabilities while complying with the most stringent power constraints. Built around the highly successful CEVA-XC DSP architecture with more than 15 design wins to date, the CEVA-XC4000 delivers up to a 5X performance improvement for the most demanding communication standards over previous CEVA-XC DSPs, while consuming 50% less power.

Eric Esteve from IPNEST –

May 22, 2012August 22, 2024

Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap

Beyond 28nm: New Frontiers and Innovations in Design For Manufacturability at the Limits of the Scaling Roadmap
by Daniel Nenni on 05-22-2012 at 9:00 pm
Categories: Foundries, GlobalFoundries

The introduction of 28nm high-volume production for IC semiconductor devices will usher the era of “extreme low-k1” manufacturing, i.e. the unprecedented situation in the long history of the silicon technology roadmap, where computationally intensive (and EDA-driven) Design-Technology Co-Optimization will become the key enabler to a product success in terms of yield, time-to-market and profitability.

This talk will provide a review and technical analysis of the methodological innovations in Design Enablement flows which are being introduced for early production at 28nm, particularly advanced DFM physical verification and DFM-aware router implementations. Rule-based, model-based and the newly released pattern-matching based hybrid verification, pioneered, industry-first, at GLOBALFOUNDRIES are prominent examples of these new enablement flows.

DFM methodologies are complemented by a set of novel foundry-based flows identified as Design-Enabled Manufacturing (DEM). While DFM provides process awareness into the design cycle through accurately calibrated models and verification flows (DFM sign-off), DEM enables manufacturing/design co-optimization, using automated physical design analysis and characterization, which in turn drive process optimization, fine-tuned to specific customer product designs.

The presentation will conclude with a preview of the “variability-challenge” intrinsic in the 20nm node and with an anticipation of the innovative EDA solutions which are currently being developed in the new Foundry-supported collaborative eco-system.

Luigi is a very engaging speaker on the leading edge of process technology, you definitely do not want to miss this one. See you there……

BIOGRAPHY: Luigi Capodieci, Ph.D.
Director DFM/CAD – R&D Fellow – GLOBALFOUNDRIES

Dr. Luigi Capodieci has been working on lithographic imaging and process simulations for more than 15 years, with applications to Optical Proximity Correction, Phase Shift Masks, Resolution Enhancement Technology and Design/Process Co-Optimization.

At Advanced Micro Devices, in California, he pioneered the field of Design For Manufacturability (DFM) integrating physical design CAD flows with rigorous layout printability process modeling and novel verification algorithms.

He is currently an Engineering R&D Fellow and the Director of DFM/CADat GLOBALFOUNDRIES (www.globalfoundries.com), coordinating DFM R&D from 45 and 32/28nm, down to the next generations of 20 and 14nm technology nodes.

Dr. Capodieci holds a Doctor degree in Electronic Engineering and Computer Science from the University of Bologna, Italy and a Ph.D. in Electrical Engineering, from the University of Wisconsin-Madison, where he worked at the Center for Nanotechnology (CNTech, formerly Center for X-Ray Lithography).

Dr. Capodieci has authored and co-authored more than 35 journal and conference technical publications and is the principal inventor or co-inventor in more than 30 U.S. Patents. He is also an active member of the IEEE and ACM technical organizations.

May 22, 2012June 14, 2019

The Midwestern Hedge Fund Manager

The Midwestern Hedge Fund Manager
by Ed McKernan on 05-22-2012 at 7:06 pm
Categories: General

Four years ago, a VC friend of mine was invited to a get together with a prominent Hedge Fund Manager from the Midwest. The meeting was an arrangement between fellow Harvard Grads. The Fund Manager was looking to make investments in the valley, to diversify away from his heavily weighted financial positions. Though, not recognized at the time, the Manager had a few months to rearrange his portfolio away from the coming collapse and into “growth” engines that would excite his Limited Partners. The discussions boiled down to Social Media, “Green” and traditional valley firms. The Manager chose “Green” because of the balance between valuation, growth prospects and requirement for significant capital. The story continues….

Moore’s Law is relentless and unforgiving, even when it comes to “Green.” In good times it can provide great returns, but only for short periods. In bad times, it seems the losses are never ending and you beg to be cut loose from the toxic waste. The Austrian economist Joseph Schumpeter was the first to describe the process of Creative Destruction that well summarizes what Moore’s Law does to an economy that tries to stand still. He wrote the book in 1942.

For the last four years, the valley has operated under a dual economy. Social Media has roared ahead on the backs of cheaper computers, servers, storage and networking. Apple likewise has built a new platform that leverages low cost hardware to create the multitude of synched devices that households find necessary and irresistible. This morning I did a check on the performance of leading semiconductor firms from May 2008 to today. Of the list of firms (Analog Devices, Texas Instruments, Xilinx, Altera, Broadcom, Qualcomm, Marvell, Nvidia, Micron, and Linear Tech) only Altera, Xilinx and Qualcomm are up by more than 15%. I looked at a second group that supports the Mobile Tsunami marketplace (ARM, Cirrus, Cypress, Sandisk, Atmel). They are all up big except Sandisk who was up big until two months ago. Such is the travails of FREE memory.

The Hedge Fund Manager, who moved part of his investments out of the financials and into the Solar Field went from bad to worse (would have been much better throwing a dart at a list of S&P500 companies). If our Manager would have bought from the traditional basket of semiconductor companies, he would have been fine. But better yet, our Manager could have outperformed all of his peers if he would have just invested in the Mobile Tsunami basket of stocks (AAPL, ARMH, QCOM, CY, CRUS, ATML) and gone away for four years. The performance would be so top notch he would probably make the cover of reputable magazines.

The semiconductor industry is no longer seen as glamorous, and has the feel of the automobile market pounding away metal day after day. The lack of attention shows in their compressed P/Es. A turn though is in the offing as we in our field have been trained to expect.

Hedge Fund Managers don’t last if they can’t adapt to a changing environment. The last time the country encountered an “End of the World” Scenario like the 2008-2009 financial crises was at the beginning of WWII. Franklin Roosevelt had shepherded the country through a partial recovery from the Great Depression when we were attacked at Pearl Harbor (unemployment was 9.9%). His greatest triumph, winning WWII, was made possible by his willingness to make concessions to big business that enabled the war machine to ramp beyond what was considered possible. It led to the outfitting of not only the 12M man American Army, but to that of Britain and to a degree – Russia. It was an “All In” strategy against two well armed enemies that were on the verge of winning the war.

Our Hedge Fund Manager, the President, could have from the first day in office taken steps to reduce risk across the board. The financial crises dramatically increased the cost of capital. In addition to the $1T stimulus, he could have implemented tax and regulatory relief that would have led to greater employment in the valley and the US over all. The cost would have been minimal especially in light of the alternative scenario that has developed. The articles about Apple, Google and the rest of the companies in the Silicon Valley off shoring their revenue to avoid taxes is a very big deal because they are tied into well paying operations jobs (think manufacturing, test and shipping) that follow with them. A consumption tax, as one alternative to the corporate tax, would have created economic growth and jobs stateside. Imagine the upside we would be enjoying if our World Class, Export Oriented Semiconductor Industry were going Great Guns!

With negative returns and a flight of capital from Limited Partners, the Hedge Fund Manager has no choice but to take on greater risks for the balance of the year. Let us hope that we get to work off a Pro Growth Playbook starting next year.

Full Disclosure: I am Long AAPL, INTC, QCOM, ALTR

May 22, 2012June 14, 2019

Intel Tri-Gate is in Trouble?!?!?!

Intel Tri-Gate is in Trouble?!?!?!
by Daniel Nenni on 05-22-2012 at 6:00 pm
Categories: Foundries, Intel Foundry
11 Comments

Since the last Intel logo parody went over so well here is another one! Not so much a parody in light of the recent PR from Intel that the fabless semiconductor business model is doomed. As one of the doomed little people inside the fabless ecosystem I take exception to this but I digress….

The word around Silicon Valley is that Intel is having manufacturing issues at 22nm. The first indication is product launch delays, but more importantly, the dissection of the 22nm silicon. The conclusions being made are:

[LIST=1]

Tri-Gate power consumption is higher than expected

A 22nm mobile SoC optimized process will be expensive

The 22nm to 14nm migration is not scaling as expected

Bottom line: Moore’s Empirical Observation (Law) is coming back to haunt Intel.

“What would you like your legacy to the world to be? Anything but Moore’s Law!” Gordon Moore May 2008.

If true, this does not surprise me at all. It is common Silicon Valley knowledge that Intel uses ultra-restrictive process methodologies. That is why they get different results than the foundries using the same semiconductor manufacturing equipment. Ultra-restrictive methodologies work fine when you are manufacturing one product (microprocessors), but the foundry business and mobile SoCs do not have that luxury.

The troubling part of this whole thing is that Intel’s problems with Tri-Gates have a much broader implication as there really is no major distinction between Intel’s term “Tri-Gate”, and the industry standard “FinFET”. The thin oxide on the top of the fin enables a (small) increment to the device width, when added to the height of the fin sidewalls — a third, or “Tri-” gate, if you will.

The term “FinFET” refers to either the three thin-oxide surfaces or a different fabrication option that results in a thick oxide on the top of the fin, and thus a “dual” gate device consisting of the two fin sidewalls only.

However, in practice, there are some unique characteristics of Intel’s implementation that are coming to light. There are some interesting Transmission Electron Microscope (TEM) photographs of Intel’s Ivy Bridge devices that have been posted by the engineering analysis team at Chipworks.

The design community (outside Intel) is a little surprised at the extent to which the fin sidewall profile on Intel’s devices is very sloped, almost resulting in a triangular rather than rectangular cross-section. No doubt, that simplifies fabrication, but most certainly complicates the extraction and device modeling requirements.

Other than that “unique” profile chosen by Intel for their “Tri-Gate” implementation, there really is no key distinction between “Tri-Gate” and the industry standard term “FinFET”.

Intel is absolutely on the bleeding edge of FinFET manufacturing so I hope we are all sympathetic to their plight. Lets minimize the drama, learn from it, and move this technology forward as quickly as possible.

May 21, 2012June 14, 2019

DAC 2012…need caffeine?

DAC 2012…need caffeine?
by Paul McLellan on 05-21-2012 at 5:00 pm
Categories: EDA, Events
1 Comment

You are in San Francisco for DAC and you want a coffee. OK, if your booth duty is 5 minutes away you pretty much have to take the Moscone coffee. Tastes good, hot, has caffeine. As Meatloaf used to sing (showing my age here) two out of three ain’t bad.

Yes, there are Starbucks all over the city, one on 4th Street just by Moscone Center, from where Steve Jobs famously ordered 2000 lattes to go during the iPhone launch.

But better imho is Peets coffee, everywhere (founded in 1966), and who sold Starbucks their beans for their first year or two of operation. I find their coffee better than Starbucks and like Starbucks they have free wireless (but just for an hour per drink).

My favorite place for coffee is Four Barrel Coffee at 375 Valencia. They roast their own coffee in the store and it is incredibly good. They are pretty fast too, so even if the line is to the door you won’t have to wait long. I love the coffee but I’m perhaps biased since I live a block away. But it is regularly picked as the best coffee in the city. And the apparently the coffee blogs (who knew there were coffee blogs?) rate it amongst the best in the entire western US. They only play vinyl so all those LPs I used to have are fashionable again. The only minor niggle is that they are too hipster to let you know their wireless password.

But that’s a long way from Moscone and probably a long way from where you are staying (but it is just a block from Zeitgeist if you decide to go and grab a beer there).

Another great coffee place is Blue Bottle Coffee. They roast their own coffee too, but not in the stores. There are two near Moscone. One on Mint Plaza (66 Mint Street along Mission just past 5th Street). The other is in SFMOMA on the top floor, but you have to be visiting the museum to get to it. The Mint Plaza one can get very busy but the coffee is worth waiting for. There is one in the ferry building but don’t even think about trying to get a coffee there during the Saturday farmers’ market, you will have a 45 minute wait.

If you prefer your coffee with a bit of something extra, you should visit the Buena Vista Café at 2765 Hyde Street (near Fisherman’s Wharf and at the end of the Powell & Hyde cable car). This is the first place Irish coffee was served in the US and they still serve a lot, often making a dozen simultaneously (symmetric multiprocessing!). And the initials for Irish Coffee are IC. It sounds a little familiar…can’t think why.