SemiWiki – Page 92 – The Open Forum for Semiconductor Professionals

March 11, 2024April 2, 2025

2024 Outlook with Hassan Triqui CEO of Secure-IC

Hassan TRIQUI has over 20 years of experience in the technology sector. Prior to spearheading Secure-IC’s development into a major player in embedded cybersecurity solutions, Hassan was a former senior executive at Thales and Thomson. Hassan is a pioneer, a Brittany Tech patriot, and passionate about providing solutions that generate the real trust that clients deserve.

Secure-IC is the rising leader in embedded cybersecurity for embedded systems and connected objects. Established back in 2010, the company has accomplished major milestones such as more than a billion IPs (Intellectual Properties) deployed, and more than 250 patents and 350 scientific publications.

Secure-IC offers cutting-edge technologies that are fully digital, certifications compliant, and silicon proven (Securyzr™), complemented by its cybersecurity evaluation tools (Laboryzr™) and its expertise for certifications and consulting services (Expertyzr™). All being backed-up by a strong and experienced team making it the only one-stop-shop for embedded security solutions.

Tell us a little bit about yourself and your company.
Today, Secure-IC is proud to be the security provider for numerous renowned customers around the world in different applications. For instance, MediaTek with its flagship Dimensity 9300 implementing AI for mobile, or UnseenLabs with its satellites fleet implementing PQC (Post-Quantum Cryptography) to ensure a safer world.

This incredible story relies on its co-founders who supported this project and conveyed it straight to success thanks to all Secure-IC’s workforce along the years. Our leadership and management ensure every day that Secure-IC continues to develop best of breed security solutions and satisfy its customers by guiding the company towards its ‘Chip-to-Cloud’ vision. One key success factor that enabled the company to succeed was and still is its commitment to its global ecosystem.

What was the most exciting high point of 2023 for your company?
Secure-IC has been showing a high growth rate for a couple of years and therefore is starting to check major milestones.

Indeed, one exciting milestone for 2023 was the construction of its brand-new international headquarters based in Rennes, France. This new HQ has for objectives to offer the best conditions to its engineering workforce with high-tech laboratories and top performance datacenter for faster and safer data. Moreover, customers and security partners will be able to observe what Secure-IC has been achieving for the last years with its showroom displaying top-notch technologies from around the world.

What was the biggest challenge your company faced in 2023?
From a start-up to a global corporation with more than 150 employees nowadays, Secure-IC’s biggest challenge in 2023 was managing the growth. Indeed, not only did the workforce keep on growing fast across the globe, but the company’s revenues also kept the pace to a 2-digit growth each year, making Secure-IC one of the key players in the industry.

Such growth implies ‘change management’ at both corporate and operational levels, required for the corporation to scale-up and better serve its customers while minimizing the impact on people by making it as smooth as possible. At Secure-IC, action plans and long-term vision have been established to ensure this transition is realized in the best way possible.

How is your company’s work addressing this biggest challenge?
As explained before, this challenge was long before predicted by Secure-IC’s management team and therefore being handled carefully.

Hence, one objective that has been identified was the streamlining of internal processes. By doing so, the company ensures that its customers have the best experience with its project management team and that they are well served across the world. As a result, Secure-IC is proud of its 95%+ satisfaction rate, showing the strong relationship that exists between the company and its customers, as intended by its mission being to partner.

On top of that, Secure-IC aims at remaining the leader in terms of technology. Therefore, the company also addresses its challenge of growth by keeping on sharpening its differentiating technologies, as well as developing a clear product portfolio coupled with ambitious roadmaps to make sure that it offers best of breed technology and products including PQC and AI for instance.

What do you think the biggest growth area for 2024 will be, and why?
The 21^st century is marked with its non-stop hockey stick curve-based technological improvements, which is especially illustrated through Moore’s law for semiconductors. As a result, not only pure software-based technologies were brought out to every application of our daily lives, but semiconductors too.

One example is the automotive industry. Moving from simple architectures with limited embedded systems on board to complex architectures (ECUs for each function to ZCUs controlling parts of the vehicle), cars from tomorrow are now being completely reinvented. Such technological improvements require from global organizations and governmental administrations to converge on global standards for ensuring optimized autonomous driving systems connected with the environment (V2V – Vehicle to Vehicle and V2X – Vehicle to Everything communications) as well on certifications to ensure both the security and safety of drivers and their environment (ISO 21434, ISO 26262…).

Such complexity opens doors to more attacks, being as complex as their target. One example, the successful attack targeting a Tesla shows the world how critical it has become to secure embedded systems against both physical and software attacks.

We also foresee other key driving forces in the industry. One example that keeps on growing every day is the rising popularity of Artificial Intelligence (AI) (esp. generative AI) and the explosion of the associated use cases. These functions will have to be implemented in devices and leverage the acceleration of hardware.

Security is an absolute must-have for any AI-application and its implementation in chipsets and devices in general since data must be protected, from the cloud all the way down to the chip (as described by Secure-IC’s Chip-to-Cloud vision), from the training data to the model itself, while preserving privacy, etc. Chipmakers and system companies are already starting to develop and produce ‘AI-chips’, which must be ‘trustworthy’ to be adopted.

AI will also make some attacks easier to perform and threats more dangerous.

Of course, AI is also an incredible technology to enhance security functions and design security policy.

Last, datacenter security and chiplets will be key trends to be closely followed-up.

How is your company’s work addressing this growth?
To address the evolution of the automotive space, Secure-IC’s teams produce significant efforts in understanding the needs of the whole value chain including the OEMs and Tier 1 with key partnerships and projects. In other words, Secure-IC not only listens to its customers but also to its customers’ customers to make sure its long-term vision and product roadmaps are accurate and maximizes the value it brings to the table.

As a matter of fact, Secure-IC is proud to offer its customers safe and secure technologies, such as ISO 26262 ASIL-D compliant security solutions ensuring them best of breed security according to global standards.

Regarding AI, Secure-IC already has its Securyzr™ solutions adapted to the AI-threat models. We are also deeply and constantly investigating on how the use of AI can enhance our portfolio and productivity (both on the protection and analysis sides), as proven by the launch of our Intrusion Detection System IDS (attached to our integrated Secure Element S700 Series for Automotive), leveraging AI.

What conferences did you attend in 2023 and how was the traffic?
Secure-IC has a very unique positioning of thought leadership in embedded cybersecurity and works by definition in an international stage. Therefore Secure-IC participate and speak at more than 4 events per month, which is very special for a company our size.

In 2023, Secure-IC actively participated in major global conferences, including CES Las Vegas, DAC, Mobile World Congress, Embedded World, ICCAD in China, Indocrypt in India, or Chipex in Israel. Secure-IC’s presence is aimed at showcasing cutting-edge technologies, connecting with customers, and gathering industry insights, but also to leading technology and scientific conferences worldwide.

These conferences provided a great platform to engage with diverse audiences and contribute to the cybersecurity community. The launch of the Security Science Factory (Secure-IC’s innovation engine) underlines the commitment to knowledge dissemination and cybersecurity awareness. The response was overwhelming, with booths and sessions attracting substantial traffic, reinforcing the impact of Secure-IC in the cybersecurity landscape.

Will you attend conferences in 2024? Same or more?
Absolutely, in 2024, Secure-IC is poised for even greater visibility and presence on the global stage. As a fast-growing company, our commitment is to align our growth with an increased presence at industry events. To achieve this, our executives and representatives are planning to attend approximately 50 conferences worldwide.

Also, we are planning our important product announcements alongside those key moments in the year.

We encourage you to visit our booth at Mobile World Congress in Barcelona this February (booth 5B41-2), at FIC (International Cybersecurity Forum) in March or Embedded World next April.

Additional questions or final comments?
In this multi-connected world, embedded security is needed everywhere. Secure-IC positions itself in a way that customers can find a unique answer encompassing multiple security concerns of theirs while keeping in contact with only one provider: One-Stop-Shop.

Secure-IC successfully served more than 250 customers across the globe since its incorporation and will continue to do so by providing security solutions that go one step further from Chip-to-Cloud with a key goal: enabling trusted data.

If you want to learn more information about Secure-IC we invite you to subscribe to our monthly newsletter here.

Also Read:

Rugged Security Solutions For Evolving Cybersecurity Threats

Cyber-Physical Security from Chip to Cloud with Post-Quantum Cryptography

How Do You Future-Proof Security?

March 11, 2024March 4, 2024

How Sarcina Technology Makes Advanced Semiconductor Package Design Easier

For a long time, package engineering was part of the cleanup crew for chip design. The glory was all around the design of advance monolithic chips on the latest technology node. Once the design was done, the package/test team would take the design over the finish line, adding the required I/O specs, lead frame, load board and test program. It wasn’t a glorious job. Over the past decade or so, that has all changed. Today, packaging requires the integration of many parts of the system, with demanding thermal and performance characteristics. Testing and qualification are also a lot more complex and difficult, requiring the coordination of many supply chain entities to get it right. Simply put, the package engineer is now a rock star. These skills are quite valuable. In this context, read on to see how Sarcina Technology makes advanced semiconductor package design easier.

The Last Mile Problem for Advanced Semiconductors

As mentioned, packaging/test/qual for advanced chip designs is no longer straight-forward. The semiconductor part of the system isn’t just a monolithic chip. Multiple dice typically implement various advanced algorithms with dedicated designs. Add to that chiplets for communication protocols and massive 3D memory stacks on some kind of interposer and you start to see the complexity of the problem.

These devices have stringent power budgets and massive performance demands. Signal integrity, power integrity and thermal management all play an important role as well, both during design and during test and production qualification. This whole process demands a large variety of skillsets, software, and hardware.

During my time at eSilicon, we delivered several advanced designs like this. I can tell you from first-hand experience the skills, software and hardware required are massive. And the production qualification can be daunting as well, requiring the involvement of many supply chain partners who contributed to the design. Until the design successfully entered volume production, none of these companies made money.

The last mile problem occurs when organizations that do a small number of tapeouts try to assemble a team needed to get this job done. It is NOT cost-effective to assemble such an operation for small numbers of designs. It is also close to impossible to keep the best talent engaged in such an environment.

What Sarcina Technology Does

Founded in 2011 in Palo Alto, CA, Sarcina Technology offers a broad range of package, test, and qualification services. The company created the Application Specific Advanced Packaging, or ASAP category. It provides advanced package design, test, assembly and production management services with proven resources and a noteworthy 100 percent first-time silicon success track record.

Digging a bit deeper, Sarcina partners with major OSATs and foundries around the world. Its engineering and production teams are in Taiwan, where many of its manufacturing partners are located. The company also collaborates with Intel Foundry Services and maintains offices in North America and Europe in addition to Taiwan. It aims to reduce overhead and accelerate time-to-volume for its customers with a boutique, collaborative experience. Unique, one-stop wafer-in, product-out (called WIPO) services are delivered.

Sarcina’s customers include tier 1 system, network, comms and AI companies. The company offers an impressive portfolio of advanced technology and a track record in many application areas. You can learn more about these details at the Sarcina website here. To whet your appetite, here are a few examples of their work:

AI 2.5D Silicon Interposer Package

5 mm x 47.5 mm HFCBGA with 2019 BGA balls
1 ASIC + 2 HBMs on a silicon interposer
12 substrate layers
320 Watts
32 lanes of 25 Gbps SerDes
16 lanes of 16 Gbps PCIe-4

Data Center High Power, Pin-Count, Performance Flip-Chip BGA Package

65 mm x 65 mm HFCBGA with 4092 BGA balls
1 ASIC
16 substrate layers
200 Watts
96 lanes of 56 Gbps PAM4 SerDes
384 bits of LPDDR5 at 6400 Mbps

Photonic IC Package

14 mm x 18 mm SiP with 336 BGA balls
1 PIC, 1 ASIC and 1 MCU
10 substrate layers
4 lanes of 56 Gbps PAM4 SerDes

Bio-Compatible Medical Package

5 mm x 81.5 mm with 392/784 leads
2-4 substrate layers
Bio-compatible dielectric material
Bio-compatible plated gold as electrodes
Small electrode openings to hold molecules
Tight opening tolerance for accurate test

How Sarcina Does It

Successfully delivering such a wide range of services begins with talent and experience. Thanks to the varied technology challenges and high velocity of workflow at Sarcina, the best-of-the-best finds a rewarding career there. Achieving such stellar results goes beyond raw talent, however.

Sarcina also has access to best-in-class tools for package/PCB design and porting, as well as 2.5 and 3D modeling and simulation. For 2.5D silicon interposer packaging, interposer design, O/S test pattern insertion, fab, and interposer wafer sort are provided. In addition,

package substrate design, power and signal integrity analysis, thermal simulation, and substrate fabrication are provided. ASIC wafer sort, assembly, final test, and production services are also part of the package.

For 3D applications, SiP (system-in-package) and WLP (wafer level package) are part of the offering, as is 3D X-ray technology to prevent wire-to-wire shorts. Sarcina also offers experience with chiplets. The company has MCM/chiplet packages in production. Stringent power integrity/signal integrity channel simulation maximizes device yield and rigorous DFM drives high assembly yield. Integrated testing services make chiplets “single-die simple”.

Support for photonic IC packaging is also provided to increase digital network transmission speed and bandwidth. Integrating the photonic IC with optical fiber delivers energy efficiency and lowers cost. The company also has experience in automotive and space grade packaging to survive stretched temperature ranges, operate under harsh environmental conditions, and pass stringent qualification standards.

In the analysis area, power integrity channel simulation analyzes the entire channel: chip-package-PCB-VRM to assure power supply minimum voltage meets spec at die bump. Signal integrity channel simulation ensures a quality eye diagram, supporting state-of-the-art advanced high speed I/O protocols. The company has production-proven results for LPDDR5, 56G SerDes and PCIe-5. Thermal simulation is also performed at the system level to accurately predict silicon junction temperatures.

And extensive wafer sort and final test hardware services are provided. ATE platforms include 93K, UltraFlex, J750EX, and Catalyst.

What’s Next?

The challenges discussed here are substantial. An organization with experience and track record across all these areas can provide the margin of victory. It’s good to know Sarcina Technology has already built the team, infrastructure, and track record that so many design teams need. Drop them an email at sales@sarcina-tech.com to find out how they can complement your team on your next project. And that’s how Sarcina Technology makes advanced semiconductor package design easier.

March 10, 2024July 17, 2025

Intel and TSMC IDM 2024 Discussions

Intel and TSMC IDM 2024 Discussions
by admin on 03-10-2024 at 8:00 am
Categories: Events, Foundries, Intel Foundry, TSMC
6 Comments

In December 2023, we published the Intel Revenue forecast for external wafer sales, gave a breakdown on how customers plan to ramp the foundry. The forecast is still valid (it assumes Intel executes on all plans) but since then we have a better understanding of Intel’s strategy and scenarios that could unfold.

The scenarios are based on Intel’s strengths and weaknesses which are quite different than TSMC and quite different than what we expected 2-3 years ago.

Background:

In 2019-2021, it became clear that Intel was a distant follower to TSMC in technology and that they needed to catch up or just outsource everything to TSMC/Samsung/others. Intel BUs complained about technology delay and cost and wanted to work with TSMC.

• It seemed like Intel would move to outsource, but Pat changed the plans based on discussions in 2021. Intel would allow BUs to choose Internal or TSMC. They would (and still do) come up with dual sourcing options and plans until later in the product development lifecycle.

• Intel cannot lead in tech with the small scale of current Intel (Times change, Intel is the third priority for equipment companies). Equipment vendors do much of the process and all of the tool development. You need scale to get their support. So Intel needs to offer foundry services to roughly double the scale of Intel wafer output. Intel needed to go “all in” on being a leading foundry.

• Pat [hypothetically] said: “…Business units say manufacturing is the problem. Manufacturing say BU is the problem. Fine …. Each of you can do what you want…. BUT we will make major decisions based on your execution.”

Hence where we are today: Intel is ramping TSMC on chips for processors of all types. Some leading products are 100% TSMC. And Intel is promoting foundry for others at the same time. 5 nodes in 4 years (not really, but that is a different report).

The BUs are extremely happy with this. So far multiple products have been moved to TSMC and the flexibility in using N5,N3,N2 is something they love. TSMC price is about the same as Intel’s cost, so BU margins will increase.

But how does Intel compete cost effectively with TSMC and ramp foundry and pay for all these fabs?

We overlooked a couple things until our IEDM discussions with various people in December 2023.

• Intel still wants to win and be better than TSMC. It seems unlikely… but it might not matter.

• The US government buys chips for internal products and DoD items. No strategic DoD product has TSMC parts in it. TSMC does not meet the criteria. As a result, those products have technologies that are not close to leading edge. IBM (past), GF and other defense approved companies make chips for those products but they are nowhere near leading edge. They would love to use leading edge but they need a DoD approved US company. While DoD parts are relatively low volume, the government could expand this to any Government supply chain (they track detailed supply chain and factories for all parts). IRS, Social Security, etc. TSMC cannot fill this today and it would require massive regulation to even have Samsung US or TSMC US support it. Trust me, I have done the audits with government products before, it can be extremely painful.

Also, While Intel is not set up from a scale or from a cultural perspective to be a leader in cost, US Government pays cost plus and incredibly high prices for products. Intel could have half filled fabs and still have great margins. You can see this at some government suppliers today.

• The third one also could have been predicted but was missed. Leading edge is too expensive and complex. So many foundries…. GF, UMC, SMIC, Grace, Tower have no ability to provide leading edge or even 2 generations behind technology. Intel can partner with them, provide “more modern” technologies, provide scale etc. All companies not named TSMC or Samsung could GREATLY benefit from partnering with Intel and this allows them to compete with Samsung and TSMC.

Based on the above strategies. Intel could outsource most of its silicon to TSMC to keep the BUs happy and STILL be a leader in foundry just based on being the “US Fab company” and “advanced fabs to other foundries”. These customers are much more compatible with Intel than selling to Apple, AMD, Nvidia, and Broadcom.

This is a different foundry model but one where Intel has a strength and can potentially dominate. This all may or may not work. We have quantitative milestones you can track to see if Intel is successful.

The Three Potential Foundry Scenarios are:

• *Intel Foundry Success*: Intel has competitive processes at competitive prices and ramps up to be another dominant leading edge foundry. Intel is leader and Intel BUs use Intel processes. Revenue and profits grow.

• *Intel fills TSMC gaps*: Intel supplies all other foundries, Intel supplies government. Both have few other options so they pay the price needed. Revenue grows steadily over then next 10-15 years.

• *Intel is IDM2.0 = IBM2.0*: Intel struggles to ramp government work and factories. Intel’s foundry partners decide it’s not worth it to work with them and the processes are unsuccessful. The fabs are given away, or cancelled, or underloaded. Eventually Intel foundry is absorbed.

We have more details on each and in the next few years, the probability of each scenario will change. We have updates on the probability and what tactics, models, and strategies Intel is using. More importantly we provide milestones so others can track progress…. and we track the impact to P&L and Capex.

Foundry Day Update (BREAKING NEWS): All of the presentations and commitments support the background we show, the strategies, and the scenarios.

Mark Webb
www.mkwventures.com

Also Read:

Intel Direct Connect Event

ISS 2024 – Logic 2034 – Technology, Economics, and Sustainability

Intel should be the Free World’s Plan A Not Plan B, and we need the US Government to step in

How Disruptive will Chiplets be for Intel and TSMC?

Podcast EP211:A Look at the Inner Workings of the CHIPS and Science Act with Mike O’Brien

Podcast EP211:A Look at the Inner Workings of the CHIPS and Science Act with Mike O’Brien
by Daniel Nenni on 03-08-2024 at 10:00 am

Dan is joined by Mike O’Brien. Mike was recently the vice president of aerospace and government at Synopsys, He has 40 years of experience in the semiconductor, software and computer industries. In his 27 years in EDA and IP at Synopsys and Cadence, Mike helped build new lines of business including outsourced design services, research collaborations and a government focused vertical.

Currently, Mike is part of a team working for the US Department of Commerce that will play a key role to implement the CHIPS and Science Act’s historic investments in the semiconductor industry.

Mike explains how the significant investments in semiconductor technology are being managed by the US Department of Commerce, both the $39B for semiconductor manufacturing and $11B for semiconductor R&D. He details the infrastructure that manages the programs between government, private sector and financial organizations to achieve the supply chain coordination required to grow and strengthen US semiconductor capabilities from an economic and national security perspective.

Mike explains how the various organizations work together and how private industry can get involved to harness the investments being made. Details of current and future programs are also discussed.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

March 8, 2024February 27, 2024

International Women’s Day with Christelle Faucon VP Sales Agile Analog

International Women’s Day with Christelle Faucon VP Sales Agile Analog
by Daniel Nenni on 03-08-2024 at 6:00 am
Categories: Agile Analog, IP

Born in France, now living in the Netherlands, Christelle Faucon has over 25 years’ experience of working across the global semiconductor ecosystem. Currently she is VP of Sales at Agile Analog, the analog IP innovators. Following a Master’s Degree in Electronics Engineering, Christelle began her career as a Design Engineer. She has since held senior product and commercial positions, including 10 years at TSMC and 10 years as President of GUC (Global Unichip) Europe. Dedicated to empowering women in the semiconductor industry, Christelle is also involved in the GSA Women’s Leadership Initiative.

What was your first job in the semiconductor industry?
My first job was working as a Design Engineer for VLSI Technology, an American company with a division in the South of France. I was focused on developing DSP behavioral models and providing related technical support. I also worked on designing SoC blocks, writing Verilog, performing synthesis, place and route, as well as verification tasks. It was a varied job that enabled me to gain great hands-on technical experience, which has helped me throughout my career as I moved into more commercial roles.

Why do you enjoy working in the semiconductor industry?
The semiconductor industry is a really interesting place to work. In recent times we have seen innovative electronic devices that impact positively on everyday lives. IoT, healthcare sensors, automotive safety systems, remote monitoring solutions – all made possible by advances in semiconductors. And there are many new applications in development. When you work in the semiconductor sector you never get bored! I am delighted to now be working at Agile Analog. Our ground-breaking analog IP technology simplifies semiconductor design and speeds up integration, and looks set to transform the world of analog IP.

What is your main professional goal for 2024?
It’s great to be working with the Agile Analog team to help accelerate adoption of our customizable analog IP products across the globe. I find it so exciting that the company has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications, for any foundry and on any process. Demand is growing fast, especially for our data conversion and power management solutions. My own background as a chip designer will help me to understand the challenges that our customers are facing. My industry experience and strong technical knowledge will also be beneficial. It is very rewarding to be part of Agile Analog at such a pivotal time.

Outside of work – what hobbies do you have?
I love to travel and experience new cultures. I also enjoy horse riding in my spare time. Last November, before I started at Agile Analog, I had the chance to do both during an amazing trip to Nepal which included horse riding in some remote areas. My wish list of countries still to visit is very long!

What advice would you give to your younger self?
The best advice I could offer my younger self would be: don’t be afraid to step outside of your comfort zone. Believe in yourself. You can achieve much more than you expect. Embrace every opportunity to learn new things.

Tell us about the GSA Women’s Leadership Initiative you are involved with.
March 8^th is International Women’s Day. To me it is so disappointing that less than 30% of engineering graduates are female, and quite shocking that less than 5% of leadership positions in the semiconductor sector are held by women.

That’s why I am committed to empowering women in the semiconductor industry, by championing the creation of impactful programs through the Global Semiconductor Alliance GSA Women’s Leadership Initiative that foster diversity. The primary goal is to help cultivate a strong community of women that provides mentoring and calls for equal opportunities. Joining the GSA EMEA Women’s Leadership Council means that I can use my experience to help women in the sector.

The first GSA Women’s Leadership Initiative EMEA event will take place in London on March 13^th – the Women in Semiconductors Conference – on day 1 of the GSA International Semiconductor Conference. This aims to highlight the achievements of some of those women who have succeeded in navigating a traditionally male-dominated environment. It should be a really interesting and informative event.

What advice would you give to experienced female engineers and female leaders in the semiconductor industry?
My advice for senior female engineers and women in leadership positions across the global semiconductor industry would be – don’t hide – please come forward to share your experiences and expertise. If possible, speak at career fairs and industry events. Role models are required to inspire the younger generation. It is also vital to support each other and to encourage more women to take on leadership roles in semiconductor companies. That’s why I feel the work of the GSA Women’s Leadership Initiative is so important.

Also Read:

2024 Outlook with Chris Morrison of Agile Analog

Agile Analog Partners with sureCore for Quantum Computing

Agile Analog Visit at #60DAC

March 7, 2024July 18, 2025

Complete 1.6T Ethernet IP Solution to Drive AI and Hyperscale Data Center Chips

Complete 1.6T Ethernet IP Solution to Drive AI and Hyperscale Data Center Chips
by Kalar Rajendiran on 03-07-2024 at 10:00 am
Categories: AI, EDA, IP, Synopsys

Synopsys 1.6T Ethernet IP Solution Image 2

The demand for high-bandwidth, low-latency networking solutions has never been greater. As artificial intelligence (AI) workloads continue to grow exponentially, and hyperscale data centers become the backbone of our digital infrastructure, the need for faster and more efficient communication technologies becomes imperative. 1.6T Ethernet will rapidly be replacing 400G and 800G Ethernet as the backbone of hyperscale data centers.

Hyperscale data centers, which power everything from cloud computing and big data analytics to AI and machine learning, require high-bandwidth, low-latency chips and interfaces to process petabytes of data quickly and efficiently. As the demand for computing power continues to grow, so does the energy consumption of data centers. High power consumption by interconnects leads to increased heat generation, which in turn requires more robust cooling systems to maintain optimal operating temperatures. By reducing interconnect power consumption, less heat is generated, overall energy efficiency can be improved, leading to cost savings and reduced environmental impact. In essence, when it comes to AI and data center infrastructure, it is the latency, power and size trifecta that are of critical importance, in addition to the speed.

Synopsys recently unveiled the industry’s first complete 1.6T Ethernet IP solution that addresses all of the above requirements. Enabling up to 40% latency reduction, 50% interconnect power reduction and 50% area reduction compared to existing solutions, Synopsys’ complete solution includes a pre-verified subsystem, giving a head start to chip designers.

Complete Solution

The complete 1.6T Ethernet IP solution from Synopsys includes a range of innovative technologies designed to optimize performance, reduce power consumption, and accelerate time-to-market for AI and HPC networking chips.

Following is a contextual quote from Mick Posner, VP of Product Management, High Performance Computing IP Solutions at Synopsys.

“The silicon providers behind data center units require adoption of the latest generation of interconnect protocols so that they can optimize their silicon to scale with new workloads. And this is exactly where 1.6 Ethernet comes in.”

Offering customers a complete Ethernet IP solution simplifies integration, reduces complexity, optimizes performance, eases deployment, provides consistent support, enables scalability, and helps mitigate risks. These benefits ultimately lead to greater customer satisfaction and success in deploying and maintaining Ethernet IP networks.

The Synopsys 1.6T Ethernet IP solution features new, optimized MAC and PCS IP

1.6T MAC and PCS Ethernet Controllers

Forward Error Correction (FEC) mechanisms play a pivotal role in enhancing the reliability of data transmission over high-speed links, particularly in the context of 1.6Tbps traffic. While FEC helps combat errors and ensures data integrity, its implementation introduces additional considerations such as area, power consumption and latency. Striking the right balance between Bit Error Rate (BER), power efficiency, and latency becomes imperative in designing efficient communication systems for the 1.6T era. By implementing a patented Reed-Solomon FEC architecture, Synopsys is able to decrease area by 50% and reduce latency by 40% on the 1.6T Ethernet MAC and multi-channel, multi-rate PCS Controllers without sacrificing reliability across Ethernet rates from 10G to 1.6T.

224G Ethernet PHY IP

Synopsys’ silicon-proven Ethernet PHY IP delivers robust link performance with exceptional signal integrity, supporting chip-to-chip, chip-to-module, and copper cable connections. The customizable PHY IP optimizes power and performance tradeoffs, providing seamless ecosystem interoperability for multiple channel lengths.

Verification IP

Synopsys’ verification IP for up to 1.6T Ethernet speeds accelerates time-to-market by speeding up the verification process. Implemented in native SystemVerilog and Universal Verification Methodology (UVM), the verification IP provides a comprehensive set of protocol, methodology, and productivity features, ensuring reliable and efficient testing of Ethernet designs. As the industry’s first Ethernet verification IP for up to 1.6T, it helps speed time to first test.

Backward Compatibility

Synopsys’ 1.6T IP solution is backward compatible with 400G and 800G Ethernet solutions, allowing users to upgrade or expand their systems at their own pace without facing costly disruptive changes. Backward compatibility is vital for preserving investments, ensuring smooth transitions, and promoting interoperability in software, hardware, and protocols. By allowing users to seamlessly integrate new technologies with existing systems, the Synopsys solution’s backward compatibility minimizes disruption and reduces the learning curve.

Silicon to Systems Design Solutions

Synopsys’ complete solution includes pre-verified subsystems enabling customers to streamline their development process and reduce time-to-market and development risks. These subsystems, rigorously tested and validated by suppliers, ensure high reliability and adherence to industry standards. Equipped with these, customers can focus on their core competencies while enjoying scalability and flexibility. The accelerated time-to-market enhances the overall return on investment, making pre-verified subsystems a valuable asset for efficient product development by customers large, medium and small alike.

The Synopsys 1.6T Ethernet IP solution subsystem integrates pre-verified MAC, PCS, and PHY

Summary

Synopsys’ complete 1.6T Ethernet IP solution represents a significant milestone in the evolution of networking technologies for AI and hyperscale data centers. By offering innovative solutions that optimize performance, lower latency, reduce power consumption, and accelerate time-to-market, Synopsys is helping to drive the future of AI and high-performance computing, enabling customers to meet current and future demands of the most data-intensive workloads.

For more details, visit Synopsys Complete 1.6T Ethernet IP Solution.

You can access Synopsys’ press release on their complete 1.6T Ethernet IP solution here.

Also Read:

2024 Signal & Power Integrity SIG Event Summary

Navigating the 1.6Tbps Era: Electro-Optical Interconnects and 224G Links

Why Did Synopsys Really Acquire Ansys?

March 7, 2024March 4, 2024

2024 Outlook with Da Chuang of Expedera

2024 Outlook with Da Chuang of Expedera
by Daniel Nenni on 03-07-2024 at 6:00 am
Categories: Expedera, IP

Expedera provides customizable neural engine semiconductor IP that dramatically improves performance, power, and latency while reducing cost and complexity in edge AI inference applications. Da is co-founder and CEO of Expedera. Previously, he was cofounder and COO of Memoir Systems, an optimized memory IP startup, leading to a successful acquisition by Cisco. At Cisco, he led the Datacenter Switch ASICs for Nexus 3/9K, MDS, CSPG products. Da brings more than 25 years of ASIC experience at Cisco, Nvidia, and Abrizio. He holds a BS EECS from UC Berkeley, MS/PhD EE from Stanford. Headquartered in Santa Clara, California, the company has engineering development centers and customer support offices in the United Kingdom, China, Japan, Taiwan, and Singapore.

Tell us a little bit about yourself and your company.

My name is Da Chuang, and I am the co-founder and CEO of Expedera. Founded in 2018, Expedera has built our reputation of providing the premier customizable NPU IP for edge inference applications from edge nodes and smartphones to automotive. Our Origin NPU, now in its 4^thgeneration architecture, supports up to 128 TOPS in a single core while providing industry-leading processing and power efficiencies for the widest range of neural networks including RNN, CNN, LSTM, DNN, and LLMs.

-What was the most exciting high point of 2023 for your company?

>>2023 was a year of tremendous growth for Expedera. We added two new physical locations to our company, Bath (UK) and Singapore. Both of these offices are focused on future R&D, developing next-generation AI architectures, plus other things you’ll be hearing about in the months and years to come. While that is very exciting for us, perhaps the most significant high point for Expedera in 2023 was our customer and deployment growth. We started the year with the news that our IP had been shipped in over 10M consumer devices, which is a notable number for any Semiconductor IP startup. Throughout the year, we continued to expand our customer base, which now includes worldwide Tier 1 smartphone OEMs, consumer devices chipsets, and automotive chipmakers. Our NPU solution is recognized globally as the best in the market, and customers come to us when they want the absolute best AI engine for their products.

-What was the biggest challenge your company faced in 2023?

>>The biggest challenge in 2023, along with the biggest opportunity, has been the emergence of Large Language Models (LLMs) and Stable Diffusion (SD) in the edge AI space. LLMs/SD represent a paradigm shift in AI – they require more specialized processing and more processing horsepower than the typical CNN / RNN networks most customers were deploying in 2022 and prior. The sheer number of LLM/SD-based applications our customers are implementing has been incredible to see. However, the main challenge of LLMs and SD on the edge has been allowing those networks to run within the power and performance envelope of a battery-powered edge device.

-How is your company’s work addressing this biggest challenge?

>> Our customers want to feature products that are AI-differentiated; products that bring real value to the consumer with a fantastic user experience. However, significant hits to battery life aren’t accepted as part of the user experience. As we integrated LLM and SD support into our now-available 4^th generation architecture, our design emphasis was focused on providing the most memory efficient, highest utilization, lowest latency NPU IP we could possibly build. We drilled in the underlying workings of these new network types; data movements, propagations, dependencies, etc… to understand the right way to evolve our both our hardware and software architectures to best match future needs. As an example of how we’d evolved, our 4^th generation architecture features new matrix multiplication and vector blocks optimized for LLMs and SD, while maintaining our market-leading processing efficiencies in traditional RNN and CNN-style networks.

-What do you think the biggest growth area for 2024 will be, and why?

>> One of our biggest growth areas is 2024 is going to be supporting an increasing variety of AI deployments in automobiles. While most are likely familiar with the usage of AI in the autonomous driving stack for visual-based networks, there are a lot more opportunities and uses that are emerging. Certainly, we’re seeing LLM usage in automobiles skyrocketing, like many other markets. However, we’re also seeing increased usage of AI in other aspects of the car – driver attentiveness, rear seat passenger detection, infotainment, predictive maintenance, personalization, and many others. All of these are aimed at providing the consumer with the best possible user experience, one of the key reasons for the implementation of AI. However, the AI processing needs of all of these uses vary dramatically, not only in actual performance capabilities but also in the types of neural networks the use case presents.

-How is your company’s work addressing this growth?

>> Along with the aforementioned LLM and SD support, Expedera’s 4^th generation architecture is also readily customizable. When Expedera engages in a new design-in with a customer, we seek to understand all the application conditions (performance goals, network support required, area and power limitations, future needs, and others) so that we can best customize our IP – essentially, give the customer exactly what they want without having to make sacrifices for things they don’t. If the customer desires a centralized, high-performance engine handing a number of different uses and support for a variety of networks, we can support that. If the customer wants to deploy decentralized engines handling only specific tasks and networks, we can support that as well – or anywhere in between. And this is all from the same IP architecture, done without time-to-market penalties.

-What conferences did you attend in 2023 and how was the traffic?

>>Expedera exhibits at a targeted group of conferences focused on edge AI, including but not limited to the Embedded Vision Summit and AI Hardware & AI Summit, as well as larger events like CES. Traffic at these events seemed on par with 2022, which is to say respectable. AI is obviously a very hot topic within the tech world today, and every company is looking at ways to integrate AI into their products, workflows, and design process. Accordingly, we’ve seen an ever-increasing variety of attendees at these events, all of whom come with different needs and expectations.

-Will you attend conferences in 2024? Same or more?

>>2024 will likely see a slight expansion of our conference plans, especially those focused on technology. As part of the semiconductor ecosystem, Expedera cannot afford to exist in a vacuum. We’ve spoken at past events about our hardware and software stacks, as well as implementations like our security-centric always-sensing NPU for smartphones. This year, we’ll be spending a lot of our time detailing edge implementations of LLMs, including at upcoming conferences later this Spring. We look forward to meeting many of you there!

Also Read:

Expedera Proposes Stable Diffusion as Benchmark for Edge Hardware for AI

WEBINAR: An Ideal Neural Processing Engine for Always-sensing Deployments

Area-optimized AI inference for cost-sensitive applications

March 6, 2024April 9, 2024

Ansys and Intel Foundry Direct 2024: A Quantum Leap in Innovation

Ansys and Intel Foundry Direct 2024: A Quantum Leap in Innovation
by akanksha soni on 03-06-2024 at 2:00 pm
Categories: Ansys, Inc., EDA, Events

In the dynamic realm of technological innovation, collaborations and partnerships often serve as catalysts for groundbreaking advancements. Continuing along this trajectory, Ansys, a global leader in engineering simulation software, has forged a partnership with Intel Foundry to enable multiphysics chip design. The two companies share the same set of values: a commitment to science and innovation. To further strengthen this unprecedented collaboration, Ansys proudly participated in the Intel Foundry Direct 2024 event that happened on 21^st February in San Jose, USA.

At the event, John Lee, Vice President and General Manager of the Electronics, Semiconductors, and Optics business unit at Ansys, delivered an Executive Keynote address, along with Keynotes from the other Big-4 EDA suppliers: Synopsys, Cadence, and Siemens. Lee started his talk by eloquently discussing the transformative journey of the semiconductor industry and its pervasive influence across diverse sectors such as high-tech, healthcare, and automotive. He emphasized the critical role of semiconductors in meeting the escalating technological demands of the modern world.

In addressing the evolving demands of the modern world, Lee highlighted how current chip design methodologies are insufficient for handling today’s intricate 2.5D/3D-IC designs. Lee identified three primary challenges facing the EDA industry in crafting intricate architectural chip designs: multi-physics, multi-scale, and multi-organizational challenges. He calls these the 3Ms of 2.5D/3D-IC design.

Multi-physics hurdles arise from novel physical effects that are not within the experience of most monolithic chip designers. Lee gave Thermal Integrity, EM Signal Integrity, and Mechanical/Structural Integrity as examples of new multiphysics challenges.
Multi-scale challenges manifest due to the blurred boundaries between chip, package, and system design. Multi-die assemblies involve the designer at the nanometer device scale, the micrometer chip layout scale, the millimeter packaging scale, all the way to the cm/m system scale. This multi-scale reality across 6 orders of magnitude means that physical effects fundamentally change how they behave at each level. Thermal was given as a good example of a physical simulation that has very different requirements at the chip, package, and system levels.
Multi-organizational challenges emanate from the necessity to revamp traditional company structures to align with the demands of contemporary design. This may be the most intractable problem as companies try to fit the physics to the org chart rather than adapting the org chart to match the physics requirements.

Lee suggests that by adopting strategic thinking, the challenges of multi-physics, multi-scale, and multi-organizational aspects can be turned into valuable opportunities. A considered approach is t suggest the three ‘P’s – physics, platforms, and partnerships – as keys to unlocking the complete benefits arising from the transformative shifts in the industry. John Lee highlighted Ansys’ multiphysics broad and mature array of physics simulation solutions, designed to equip designers with the tools necessary to overcome the hurdles of modern chip design. He stressed the need for the EDA industry to provide open and extensible platforms that allow customers to bring together the best-in-breed solutions from the entire industry and enable these on the cloud.

In a strategic collaboration, Ansys has recently partnered with Intel to deliver multiphysics signoff solutions tailored for Intel’s innovative 2.5D chip assembly technology. Ansys was able to list its products as certified by Intel in supporting their cutting-edge technology for 18A ribbonFETs, Power Vias for backside power delivery, and EMIB (Embedded Multi-die Interconnect Bridge) to establish flexible connections between multiple dies without relying on through-silicon vias (TSVs).

As another example of successful partnership in the EDA industry, John Lee gave the example of the 3-way collaboration between Intel, Synopsys, and Ansys to solve the multiphysics challenge that links IR-drop and timing closure. The joint solution combines golden signoff technology from both companies to deliver IR-STA and IR-ECO integration flow.

The entire event was exciting and high-energy, devoid of any dull moments. Pat Gelsinger, the Chief Executive Officer at Intel, infused the gathering with his visionary outlook for the Intel foundry and a conviction that Moore’s Law is far from dead. He articulated a compelling vision to catapult this iconic company, reinstating its pivotal position in the realm of technology. Gelsinger’s aim was not merely to revitalize Intel but also to spearhead the restoration of Western chip manufacturing on a grand scale. His vision emphasized the creation of a resilient, sustainable, and trusted supply chain, signaling a strategic commitment to a future marked by innovation and reliability.

Over 30 partners, including the ARM, UMC, MediaTek, and Broadcom took part in the Intel Foundry Direct event. Intel orchestrated an outstanding showcase, featuring special speeches from well-known names in the industry such as Sam Altman, Co-founder and CEO of OpenAI, Secretary Gina M. Raimondo, United States Secretary of Commerce, and Satya Nadella, Chairman and Chief Executive Officer of Microsoft.

In conclusion, the event hosted by Intel Foundry stood out as a remarkable gathering, uniting professionals from various sectors of the semiconductor industry to share insights and envision the future. John Lee’s notable presence underscored the robust partnership between Ansys and Intel. As the collaborative efforts between simulation and fabrication continue to evolve, the Ansys-Intel alliance is poised to make a lasting impact on the technological landscape, pushing boundaries and serving as inspiration for the next wave of breakthroughs.

Learn more about the multiphysics analysis and simulation solutions offered by Ansys here: Ansys Semiconductor Solutions | Datasheet

Also Read:

Why Did Synopsys Really Acquire Ansys?

Will the Package Kill my High-Frequency Chip Design?

Keynote Speakers Announced for IDEAS 2023 Digital Forum

March 6, 2024January 24, 2025

Accelerate AI Performance with 9G+ HBM3 System Solutions

Accelerate AI Performance with 9G+ HBM3 System Solutions
by Kalar Rajendiran on 03-06-2024 at 10:00 am
Categories: AI, Alphawave Semi, IP

In the technology realm of artificial intelligence (AI) and high-performance computing (HPC), the demand for higher throughput and efficiency has never been greater. To meet these evolving demands, innovative memory solutions have emerged as critical enablers, paving the way for transformative advancements in computing capabilities. Among these solutions, High Bandwidth Memory (HBM) technology has risen to prominence, offering unparalleled performance, efficiency, and scalability.

Alphawave Semi recently hosted a webinar on the topic of accelerating AI performance with HBM3+ systems solutions and Alphawave Semi’s comprehensive IP offerings enabling it. The webinar also covered the inherent challenges in implementing HBM3 technology and the system challenges to overcome.

AI Disruption and the Need for Higher Throughput

The AI revolution has ushered in a new era of computing, where machine learning algorithms power everything from virtual assistants to autonomous vehicles. These AI applications rely heavily on data-intensive tasks such as deep learning and neural network training. As AI algorithms demand rapid access to vast datasets for real-time decision-making, they place immense strain on memory systems. Memory-centric architectures are an ideal choice for unmatched levels of bandwidth and energy efficiency for such applications.

Motivation for HBM Memory

Traditional memory architectures, such as DDR and GDDR, have long been the backbone of computing systems. However, the exponential growth of AI workloads has exposed their limitations in handling vast amounts of data with low latency. Traditional memory architectures struggle to keep pace with the demands of AI and HPC workloads, leading to performance bottlenecks and inefficiencies. HBM memory addresses this challenge by stacking multiple memory dies vertically, dramatically increasing memory bandwidth while minimizing power consumption and footprint.

Components in a HBM System

A comprehensive memory system comprises several critical components, each playing a vital role in ensuring optimal performance, power efficiency and reliability. These components include the HBM memory dies, physical layer (PHY), controller, interposer, and packaging techniques. The PHY serves as the interface between the memory dies and the rest of the system, while the controller manages data transfer and access. Interposers provide the necessary connections between memory dies, enabling high-speed communication, while advanced packaging techniques ensure thermal management and signal integrity. The integration of these components into a cohesive system architecture is essential for achieving optimal performance and reliability in AI and HPC applications. Alphawave Semi’s expertise in these components enables customers to deploy robust and efficient HBM memory systems that meet the demands of AI and high-performance computing workloads.

System Challenges: Overcoming Hurdles to Adoption

Despite its transformative potential, the adoption of HBM memory presents several challenges, including thermal dissipation, signal integrity, and power delivery. As memory bandwidth increases, so too does the need for efficient cooling solutions to dissipate heat generated by high-speed data transfer. Signal integrity becomes paramount to ensure reliable communication between memory dies, while optimized power delivery architectures are essential to meet the stringent power requirements of AI applications. Managing heat dissipation, mitigating signal distortion, and optimizing power distribution are critical considerations in designing HBM-based systems. Addressing these challenges requires innovative solutions and close collaboration between chip makers, memory vendors, and package technology providers.

Alphawave Semi addresses these challenges through continuous research and development, providing customers with the tools and expertise needed to overcome system-level obstacles and unlock the full potential of HBM memory technology.

Alphawave Semi IP Offerings

Alphawave Semi offers a comprehensive suite of HBM IP solutions tailored to meet the diverse needs of AI and HPC applications. From high-performance HBM PHY and Controller IP to advanced interposer and package design solutions, Alphawave Semi provides the essential building blocks for creating cutting-edge computing systems. By delivering best-in-class PHY and controller IP, Alphawave Semi enables customers to optimize memory subsystem performance, scalability, and power efficiency for their specific application requirements.

What’s Coming Next with HBM4

Looking ahead, HBM4 promises to further elevate the performance and efficiency of memory-centric architectures. HBM4 will enable even faster and more energy-efficient AI and high-performance computing systems. As the industry continues to innovate and evolve, HBM4 represents the next frontier in memory technology, driving advancements in computing capabilities. Alphawave Semi is at the forefront of HBM4 development, driving innovation and shaping the next generation of memory technology.

Summary

HBM memory solutions offer unparalleled performance, efficiency, and scalability, making them indispensable components of modern computing systems. With Alphawave Semi’s expertise and industry-leading IP offerings, semiconductor companies can harness the full potential of HBM memory to accelerate innovation and drive the next wave of AI disruption. By addressing the challenges of AI disruption, empowering system designers with advanced solutions, and driving the development of future technologies like HBM4, Alphawave Semi is shaping the future of computing and unlocking new possibilities for AI and HPC applications.

The entire webinar can be accessed on-demand here.

For more details about Alphawave Semi’s HBM related IP offerings, visit http://www.awavesemi.com/silicon-ip

Also Read:

Alphawave Semiconductor Powering Progress

Will Chiplet Adoption Mimic IP Adoption?

Unleashing the 1.6T Ecosystem: Alphawave Semi’s 200G Interconnect Technologies for Powering AI Data Infrastructure

March 6, 2024March 15, 2024

Siemens Promotes Digital Threads for Electronic Systems Design

Siemens Promotes Digital Threads for Electronic Systems Design
by Bernard Murphy on 03-06-2024 at 6:00 am
Categories: EDA, Siemens EDA

Many years ago, I remember discussions around islands of automation/silos. Within the scope of any given silo there is plenty of automation to handle tasks relevant to that phase. But managing the full lifecycle from concept through manufacturing to field support must cross between silos, and those transitions are not as clean and automated. Over time more attention was paid to merging silos, through M&A and tighter integration, so now there are fewer but still bumpy and incompletely automated transitions.

Courtesy Siemens

The merging strategy will only take us so far. OEM system architecture, digital design, validation, manufacturing, and OEM product lifecycle management live in worlds which are too different to be pulled into one over-arching platform. Better connecting these phases in the lifecycle must rely on new interoperability standards and ideas. In the ideas department, Siemens proposes a concept of digital threads to interconnect data between silos.

What is a digital thread?

As Siemens puts it:

(Digital threads) collect, integrate, and manage data across the different stages of a product’s lifecycle. The goal is to then to harness that data in more advanced and interactive ways, which is achieved through a digital twin. While the digital thread provides a structured pathway of data across the lifecycle, the digital twin utilizes this data to dynamically mirror the real-world state, behavior, and performance of a particular product.

The digital twin is the engine to mirror the behaviors of a real-world capability (chip, car, factory), and digital threads are bi-directional data pathways weaving through the twin all the way from architecture to deployment. These act as a common source of truth between different product development and manufacturing/deployment phases, connecting both downstream and upstream, aiming to keep all phases through the lifecycle in sync with the most current expectations, assumptions, and implementation choices.

As described in their whitepaper, Siemens divides digital thread types into those originating or centered in architecture, components, design data, verification, and manufacturing/deployment. Remember that all these threads connect through the digital twin model (enabling shift-left design and optimization) and to the physical implementation (enabling cross correlation between the model and real-world prototype/deployment behavior).

The architecture, component, and design data threads

For me a perfect example (though not the only example) of the kind of data for which a thread makes sense in architecture is for traceability, a topic of great importance in automotive, aerospace and defense among other domains. Here the goal is to trace compliance with original OEM requirements, all the way through the lifecycle. And conversely to reflect unavoidable non-compliant changes made in design, so these become visible and actionable by all stakeholders through the lifecycle. Today much of this is accomplished through human review of natural language documents and spreadsheets. More sophisticated traceability systems aim for better mechanized compliance checking so that for example a requirement is matched to a design feature (with change notices if required) and to tests to validate compliance.

A second thread connects component data through the lifecycle. In component design, significant detail is generated for functional behavior, electrical, thermal, and other characteristics. After manufacturing, this data is heavily abstracted into PDF datasheets, losing almost all of the detail that an OEM might sometimes need to see, forcing information communication back to the stone age through human-only readable documents. System developers must craft their own databases to attempt (incompletely and inaccurately) to capture some of this detail from other documents and to add their own metrics such as cost and sourcing risk. Standards such as JEDEC JEP30 Part Model Guidelines aim to upgrade from this mess, to make a true component data thread possible. Another very important factor here is trust and (again) traceability for components. A digital thread can be signed, unlike the mess of documents on which we currently rely.

The design thread as I read it in this white paper primarily connects across the system implementation, from multi-die designs, PCB, module, and full electronic system, although I imagine similar value would extend to domain specific SoC design as a component in the overall system. This thread connects electronics, electrical and MCAD to provide a single source of truth for all requirements at this level, to guide design (including cabling), multiphysics analysis, EMC and even security. It also governs accessibility requirements so that sensitive data is available only to those who have been approved to have access to that data.

The verification and manufacturing/deployment threads

For the verification thread, emphasis in this white paper is on the system above the chip/chiplet level and on physical, parametrics and compliance. One example here is full system optimization based on AI methods, in sync with offerings from other vendors. The Siemens solution is called HyperLynx Design Space Exploration, which I’m guessing uses some form of automated Design of Experiments technique through covering arrays (I have talked about this elsewhere). The other important aspect of verification here is traceability, which I mentioned earlier. Mechanized traceability enables repeated and accurate checks against requirements derived directly from the original OEM requirements. This also enables checks to trigger automatically on a design checkin, facilitating continuous integration and deployment (CI/CD) for faster response time to changes.

For the manufacturing (and deployment) thread, the authors point out that while there are well-established standards and processes in support of handing off designs to manufacturing, there is no standardized feedback loop for issues discovered in manufacturing, such as product yield or component solderability. Nor is there a standardized mechanism to feed field discoveries back into the digital twin. We already know that reproducing post-silicon failures in a digital twin is much easier if a trace of circumstances leading up to the failure is available. Supporting post-manufacturing debug on a twin should be a priority at the board/system level as much as at the SoC level. Thinking further ahead, the paper also mentions growing importance of sustainability and recyclability; both concerns will inevitably reach back into earlier stages in the lifecycle chain.

Nice paper with much food for thought. You can access the paper HERE.