SemiWiki – Page 875 – The Open Forum for Semiconductor Professionals

May 18, 2013June 14, 2019

SoC Optimization Using FPGA Prototyping

SoC Optimization Using FPGA Prototyping
by Daniel Payne on 05-18-2013 at 11:00 am
Categories: EDA

As an engineer I learn new concepts best by seeing a demonstration, in this case it was a demo of how to optimize SoC performance by using an ASIC prototyping debug process. SoC designers that use FPGAs to prototype their new ASIC often encounter debug issues, like:

Limited observability of internal nets required for debug, maybe only 1,000 nets for 1,000 clock cycles
Adding new internal probes requires a re-run of logic synthesis, causing delays of 8 or more hours
Partitioning RTL to fit into FPGAs automatically or manually can be error prone, or non-optimal

The demo on YouTube comes from the embedded instrumentation group at Tektronixand shows how their technology adds observability into your FPGA prototype that remove the three debug bottlenecks listed above. The product name for this technology is called Certus, and with it you can:

[LIST=1]

Get full RTL-level visibility during debug without rerunning logic synthesis.

View millions of clock cycles for debug.

See time-correlated debug data even if your SoC has multiple clock domains, and multiple FPGAs.

Demo Steps
An FPGA prototype was created using the Xilinx ML509 development board, and contains:

A 32 bit microprocessor, the SPARC V8
Ethernet MAC
JTAG port
Compact Flash
AMBA bus
DDR2 DRAM Controller, 256 MB of DRAM
SVGA output
Serial ports for keyboard and mouse
UART
LCD controller
PROM controller

Performance Optimization
The system level goal was to minimize the round trip time from issuing a Ping command, to when packets are received.

To start this optimization a ping command is issued which starts the Ethernet traffic, and the connected router triggers the condition that we specified. Certus Analyzer captures about 6 seconds of realtime data from our SoC (millions of clock cycles), then presents it as VCD waveforms. Zooming into the waveform viewer we can see the trigger condition where the cursor points to the red line, and validate that the trigger address we requested is displayed as well:

System-level values like the latency between transmit packet and receive packet can be debugged in great detail, allowing measurements down to each clock edge. With this type of debugging you can now start to optimize your SoC to reduce latency because you can fully see all RTL signals and see from the waveforms what the bottlenecks are in the system.

Debugging State Machines
Now that we know more about our Ethernet MAC signals, we next focus our attention to a new set of signals, like the state machine signals. With just a few clicks in Certus Analyzer you can change the group of signals and in a few seconds start to analyze state machine signals for the Receive FSM:

Selected signals can be grouped together into a configuration, and for this design there were four configuration groups. You can quickly jump to a new configuration and immediately debug:

The CPU Pipeline stage configuration is selected, and we trigger when the state goes to run:

Summary

ASIC prototyping with FPGA devices is a great way to debug your new SoC design and then optimize the hardware and software. The SoC debug process can be significantly improved if you have full RTL-level visibility with millions of clock cycles and can correlate across multiple clock domains and FPGAs. The Certus technology from Tektronix is unlike anything else out there.

DAC
To see Certus at DAC visit Booth #819, or for more info send an email to EIG-info@tektronix.com

lang: en_US

May 17, 2013June 14, 2019

5G – Reality or Fiction

5G – Reality or Fiction
by Pawan Fangaria on 05-17-2013 at 7:30 pm
Categories: General

Early in this week, I was reading news about Samsung announcing its breakthrough 5G mmWave technology. Well, this can bring fastest smart phone in the world which could enable several functions of day-to-day life and become revolutionary. The technology is not ready for commercial use, its building blocks seems to be working. There is an article by Ed Sutherland – Samsung unveils 5G mmWave tech for ‘tens of gigabits per second’ wireless downloads

It has claimed downloads and uploads at the speed of “tens of gigabits per second”. Wow!! That appears like a fiction! A whole movie could be downloaded in seconds!! Below is an official snippet from the article –
“Once commercialized, 5G mobile communications technology will be capable of ultra-high-speed data transmission up to several hundred times faster than even the 4G LTE-Advanced technology due for launch later this year.

Samsung’s new technology will allow users to transmit massive data files including high quality digital movies practically without limitation.

As a result, subscribers will be able to enjoy a wide range of services such as 3D movies and games, real-time streaming of ultra high-definition (UHD) content, and remote medical services.”

It’s a wonder, even 4G is supposed to be tens of times faster than 3G. I want to ponder a bit on 5G technicalities before I talk about the commercial and business aspects of this important innovation. When do we call 5G a 5G? At least I do not know of any standard to define that. What should be the criteria? Of course, at the core of technology is a transmitter with 64 antennae transmitting more than 1 GB data per second. The test was conducted in a range of 2 KM over a very high frequency band of 28GHz; far away from the band used in cellular services today (4G works under 800 to 1800MHz). Capacity of data increases with higher frequency. In last December, a similar experiment was done by NTT DoCoMoin Japan with 24 antennae over a frequency of 11GHz. It’s a millimeter wave, works well in space for satellite, but can it penetrate physical world of trees and buildings we live in? Looking at the Samsungtest site and the way tests were done, it appears so.

As usual, with every innovation, there comes plenty of bottlenecks and I am sure those will be overcome in due course of time (Samsung says, 5G can become commercially available by 2020). Obviously, other than antennae and frequency band, there are multiple technologies and components which will need to be assembled together to make it far reaching and available to people. Semiconductor has become an important and essential ingredient into every technology; not to mention it drives the smart phone business of today. Since DAC is around the corner, I was wondering whether there would be more announcements towards 5G and allied technologies related to 5G. Samsung is also among the exhibits; let’s see what’s more in store.

Now coming back to whether it’s a reality or fiction. In my personal opinion, all major innovations have started with fiction which became realities. The first electric arc was invented by Humphry Davy in 1800. Much later in 1879 (in between several other experiments by other scientists were done), Thomas Alva Edition, after experimenting with several materials, discovered that a carbon filament could glow without burning in an oxygen free bulb for more than 40 hours. Later he invented materials lasting for more duration. The point is, once there is a spark; the ideas will keep generating to cash on that.

In case of 5G, my view is that the idea has come much early in the phase, as 4G itself is yet to be widely realized. When 4G arrived, it appeared that 3G will not see the day, 4G will override. Now that 5G has seen the spark, it will become available, but when? Couple of questions come to mind –

[LIST=1]

Is 2020 a realistic date for it to be commercially available?

Will all components of technology (I guess several mobile technology IPs) be ready by then?

3G is able to satisfy the needs of video streaming, conferencing, live music and so on and then there is 4G. What more and unique services 5G can provide? How much people can and should spend on 5G? Both producers and consumers?

As we see in telecommunication, electronics, semiconductors…. economy of scale plays a big role. Considering that, can we say that 5G will override all others and can become available to all around the world at affordable prices?

Of course, there can be many other questions; can we get answers to some of these inDAC 2013?

May 17, 2013June 14, 2019

RTL Power Estimation at DAC

RTL Power Estimation at DAC
by Daniel Payne on 05-17-2013 at 7:22 pm
Categories: Ansys, Inc., EDA

If you design with ARMCores and need to estimate dynamic power early in the flow, then consider what STMicroelectronics has done with their high performance, power-efficient subsystems. Anne Merlande is a Processor Micro Architecture technical expert, and will be presenting in Booth #1346 at DACon June 4th, 2:00PM. Her topic is: STMicroelectronics: RTL Power Estimation on ARM Core Sub-systems. You have to register for this suite session.

Continue reading “RTL Power Estimation at DAC”

May 17, 2013June 14, 2019

IC Design with No Clocks Used in a SMART Card

IC Design with No Clocks Used in a SMART Card
by Daniel Payne on 05-17-2013 at 5:21 pm
Categories: General

My IC design career started at Intel with DRAM chips, so I’m very familiar with clockless design because we used self-timed techniques to get maximum performance. I remember blogging about an asynchronous design company called Tiempo back in 2010, while blogging at Chip Design Magazine. A few weeks ago there was a press release that caught me eye: French Consortium Announces Development of a Clockless SMARTcard chip. Steve Svoboda is my contact at Tiempo and he sent me an email, which turned into a blog interview to satisfy my curiosity.

Steve Svoboda, Tiempo

Interview

Q: Why did the partners choose a clockless design approach?

The partners (Tiempo, Gemalto, CEA-Leti, Invia, Presto Engineering, and L Foundry) wanted to explore ways to generate the next level “breakthrough” in performance for contactless smartcards, while achieving equivalent or higher security. Tiempo proposed that using their technology to develop a clockless smartcard chip, the partners could realize a chip with substantially higher performance than other chips currently on the market, along with greater security and resistance to hacking, and monitoring attacks.

Q: What benefits did clockless provide that the previous chip approach did not?

In contactless smartcards, the chip is powered by the magnetic field strength received from the reader. This field strength varies with the cube of the reader-distance (making it extremely sensitive to the distance from the reader), as well as the orientation of the card relative to the reader (the card must be parallel to the reader for maximum field strength.)

The clockless chip Tiempo developed for the ASMART project should run at substantially higher speeds than conventional chips on the market today, with equal or lower magnetic field strength from the reader. In addition, the speed of the clockless chip is able to vary dynamically and continuously as the magnetic field strength would vary.

These technical advantages would enable OEMs using the chip to deliver contactless smartcards that process transactions faster, and more reliably (i.e. not requiring “reswipes” as often) than contactless smartcards currently on the market, without making any compromises on the security of executed transactions.

Q: How long was this design project from concept to tape-out?

ASMART is an ongoing multi-phase project, with delivery of progressively more advanced prototypes scheduled at the end of each phase. For security reasons, the effort/scope of the different phases in the project remains confidential. However the partners can say the design effort so far has never exceeded that for a conventional synchronous design (i.e., using a clockless approach has not added to the cost, labor effort, or schedule of the project.)

Q: What were the design challenges, and how was each challenge met?

The main design challenges were related to the “front-end”, i.e. modeling/synthesis, functional verification, and test.

The Tiempo team modeled the entire digital portion of the chip in System Verilog, and then used Tiempo’s Asynchronous Circuit Compiler (“ACC”) synthesis tool to generate gates.

Functional verification was performed with the SystemVerilog and gate-level models, using Synopsys VCS.
Test was also challenging, as the design was entirely clockless. Tools for automatically inserting DFT for clockless designs don’t yet exist today, so Tiempo engineers had to rely on a handcrafted approach, heavily based on functional-test: in this circuit, test was almost entirely based on BIST.

Notably, the clockless, delay-insensitive nature of the logic proved a big advantage during the backend stage, as timing-closure became much more simple/straightforward than would have been the case with a conventional-logic clocked design. Integration of the Digital with the Analog/RF portions is substantially easier due to the clockless nature of the digital logic (much reduced interference, and much smoother/more uniform power consumption.)

Q: Which specific tools were used?

Modeling – SystemVerilog
Synthesis – Asynchronous Circuit Compiler (Tiempo)
Verification – VCS (Synopsys)
Place & Route – IC Compiler (Synopsys)

Q: What did the design team learn along the way?

The team learned:
– how to apply a delay-insensitive, clockless design flow in the context of developing an entire SoC.
– how clockless design makes backend timing-closure much easier than with equivalent synchronous logic.

Summary
It looks like Tiempo is finding it’s way in the world by becoming more of an IP company than an EDA company. They were able to create an EDA tool flow from tools that expected a clocked methodology, plus added their own for logic synthesis.

lang: en_US

May 17, 2013July 18, 2025

Are you going to the plug fest?

Are you going to the plug fest?
by Eric Esteve on 05-17-2013 at 10:16 am
Categories: IP, Synopsys

PCI Express 3.0 specification is 1000 pages long. Most of us, and most of the designers integrating PCIe gen-3 into their latest ASIC, FPGA or system will probably never read it completely, or even open it. In fact, they don’t need to read it completely, but they should care about one point, whether they buy an ASSP or a PCIe design IP: is this precise IP being certified? For the IP vendor, this certification can be obtained by submitting the freshly designed PCIe IP to a “Plug Fest”, or interoperability program organized by PCI Special Interest Group (PCI-SIG). Because PCI Express is defined as an Interface Protocol, the PCIe agent, Root Port (the equivalent of the Host in USB) or Endpoint (the Device equivalent), is supposed to be interfaced with any PCIe agent, Device or a Root Port respectively, not necessarily coming from the same design source, IP vendor or ASSP chip maker. During the Certification program, your PCIe IP will be plugged in front of various systems being used as reference, like Motherboards, and will have to pass a pre-defined operation test list. For an IP vendor, obtaining the PCI-SIG certification is the first step for successful market introduction, especially if you sale PCI Express Design IP.

Synopsys has just announced that their PCI Express® 3.0 is the first complete solution from a single vendor to pass compliance testing at the first PCI-SIG compliance workshop for PCI Express 3.0. According with Synopsys, this means that “to achieve compliance, the DesignWare PHY and controller IP passed PCI-SIG’s three required Gold Tests: the electrical tests, the Protocol Test Card (PTC) and the PCIeCV software tests. In addition, the DesignWare PHY and controller IP demonstrated interoperability with more than 80 percent of the devices at the workshop, exceeding interoperability requirements.” For Synopsys customer being in the decision process for sourcing the PCIe PHY, Controller or Verification IP, knowing that these IP has obtained certification will dramatically increase the level of confidence into the product, and ease taking the decision. But not only, as the PCI-SIG certification is “associative” (think about your old algebra lesson!), the chip integrating this Design IP will be certified as well!

Let me tell you a short story about plug fest. When PCI Express gen-1, the very first specification, has been issued in 2004, the market was still using PCI or PCI-X, both being parallel based interface protocol. PCIe gen-1 has introduced the bidirectional, dual simplex concept, supported by a SerDes based PHY, and the Controller was also based on something new in the PC space, the layered based protocol, including the Media Access Layer (MAC), the Transmission Link Layer (TLL) and the Application Layer (AL). Nevertheless, the PCI-SIG had to organize the very first plug-fest, as demonstrating interoperability was crucial to start a successful market introduction campaign.

Guess who had designed the PCI Express Controller to be used as a reference? A small IP vendor named Cascade… that Synopsys bought almost immediately, ringing the start of a very successful PCIe IP sale decade, as you can see on the graphic below, as Synopsys has made almost $150 million in PCIe IP sales since Cascade acquisition. But if you read Semiwiki, you have seen this post and already know this story.

Remark: this graphic has been extracted from the “PCIe IP Survey”, very recently updated by IPnest (the very last buyer is a well-known FPGA vendor, who has integrated SerDes supporting PCIe very early… and continue to do so!).

Eric Esteve from IPNEST

lang: en_US

May 16, 2013January 27, 2022

Atrenta CEO on RTL Signoff

Atrenta CEO on RTL Signoff
by Daniel Nenni on 05-16-2013 at 9:00 pm
Categories: CEO Interviews, EDA

Most EDA companies sell tools into the main chip design and implementation flow such as simulation, synthesis, place & route, custom design and mask data prep. Atrenta is different. Nothing the company sells is in this main design flow. Instead, Atrenta focuses on pre-synthesis design analysis and optimization. Everything associated with developing RTL that is implementation-ready. Atrenta’s DAC story is all about RTL signoff. I recently met with Atrenta’s CEO, Dr. Ajoy Bose to find out more about Atrenta’s unusual place in the design flow and what RTL signoff really means.

Q: What design challenges does Atrenta address?
There are two primary themes here – complexity and time-to-market.
Complexity challenges result from very large SoCs pushing the limits on design size, number of IPs, power, performance, etc. These designs are typically targeted for applications such as smartphones, tablets, networking and graphics.

Time-to-market challenges result from mid to small size designs targeting applications such as automotive, consumer, industrial automation and medical devices. These are not very complex designs but they require a very quick turnaround, with design cycles in the order of 2-3 months.

There are many ways to address these problems, but we’ve found one of the most powerful methods is to find and fix as many issues as possible at RTL, before detailed implementation begins. Problems such as routing congestion or low test coverage can be found and fixed in a matter of hours with the right tools at RTL. Those same problems take many weeks to find and fix if you’re in a gate-level implementation flow. The benefits are clear.

Q: What specific problems can you find and fix at RTL?
There are many. With our SpyGlass product, we can analyze an RTL design across many domains. Most customers start with LINT. This analysis will find basic errors in the design, such as power connected to ground or unconnected nets. It will also flag RTL structures that can give synthesis tools a hard time, or ones that will cause synthesis/simulation mismatches. We also have an advanced LINT tool that uses formal technology to look deeper into the design for things like unreachable states in a finite state machine.

We also use formal technology to prove that clock domain crossing circuits will perform correctly. This is a very popular product, since CDC bugs are very hard to find in simulation and can either kill a chip or increase its field failure rate. Power is another important area for SpyGlass. The tool will verify CPF/UPF files for correctness, estimate power consumption and recommend ways to reduce power for both logic and memory. We’ll even make circuit changes automatically if desired and use a sequential equivalence tool to prove the circuit functions the same after power reduction.

SpyGlass also looks at timing constraints and ensures they are correct and consistent. We use formal technology again to prove that false and multi-cycle paths have been correctly identified. We also help with estimating test coverage and helping to improve it, both for stuck-at as well as at-speed testing. SpyGlass also helps to reduce physical design challenges such as routing congestion.

On the functional verification front, we recently added a new tool called BugScope which automatically generates assertions. This technology helps determine if there are any coverage holes in the verification plan and creates correct-by-construction assertions to help with debug.

The last part of our tool suite comes from GenSys – a chip assembly environment that automates RTL assembly and re-structuring. We find every design needs to be modified for things like test or power planes, added logic or logical/physical hierarchy divergence, etc. These tasks are very time-consuming and error-prone. GenSys makes them all easy to do.

Q: You talk about RTL signoff in your DAC positioning this year – what does that mean?
We define RTL signoff as a design flow that has “must pass” requirements for the RTL such that the design will not be moved to the next stage of implementation until those requirements are verified. It provides very high confidence that the design is robust, implementable and will meet the design goals. The growing use of “must pass” design flows is an indicator of the maturity of the RTL design process. We’ve seen a growing proliferation of these flows over the past couple of years. I think 28nm and below is driving the trend. The complexity of those designs demands air-tight RTL before hand-off to implementation and an RTL signoff flow is the easiest way to achieve that result.

Q: Who uses RTL signoff flows?
There are really two primary areas of use. First, at the IP level. Here, you want to ensure that your IP choices will work in the final design in a predictable way. There is a lot of analysis around the quality and completeness of the IP deliverables. The goal is to minimize iterations between IP development/procurement and SoC assembly. The soft IP qualification work that Atrenta is doing with TSMC is an example of this use model.

The second area is at SoC assembly. Here, you want to ensure that your design will meet its power, performance and area requirements when implemented. The goal is to minimize iterations between SoC assembly and back-end implementation. The entire design is checked at this stage, so files can be very large. We’re deploying more hierarchical capabilities to address this issue.

Q: What will Atrenta be doing at DAC?
As you mentioned, RTL signoff is a major focus area for us this year. We’ll be hosting interviews in the RTL Signoff Theater in our booth where customers and partners will discuss their experiences with RTL signoff flows. We’ll also have detailed presentations for all our products in our suites.

There are three Designer Track presentations that discuss hierarchical CDC verification, structured assembly and 3D design. Atrenta will be quite visible at the main DAC party on Monday evening as well as a special, invitation-only party on Tuesday evening. You’ll have to come to DAC to learn more about those activities.

Q: Where can our readers find out more about Atrenta at DAC?
Easy, just go to www.atrenta.com. There are prominent links on the home page where you can learn more about our product sessions and sign up for one. You can also find out what other activities we’re involved in at DAC. I hope to see many of your readers at the show.

Also Read:

Sanjiv Kaul is New CEO of Calypto

CEO Interview: Jason Xing of ICScape Inc.

CEO Interview: Jens Andersen of Invarian

May 16, 2013June 14, 2019

AMD Reduces Power by 20%

AMD Reduces Power by 20%
by Paul McLellan on 05-16-2013 at 4:12 pm
Categories: EDA

Steve Kommrusch of AMD wrote a white paper with Calypto on how AMD reduced power by 20% on the Jaguar SoC using Calypto’s PowerPro. Dan Nenni blogged about it on SemiWiki back in February here. And now, drumroll, Steve will present the story live and in person at DAC, on Monday June 3rd at 3pm and on Wednesday June 5th at 11am. This is a private suite presentation for which you must register (here).

The AMD Jaguar X86 core is a flexible, high-frequency, processor aimed at system-on-a-chip designs for low- power markets and cloud clients. It uses 28nm process technology and has a small die area (3.1mm[SUP]2[/SUP]). Compared to the previous generation of this core, AMD Bobcat, many blocks were redesigned for improved power efficiency, including the IC loop buffer, store queue, and L2 clocks. The AMD Jaguar compute unit (CU) includes four independent Jaguar cores and a shared-cache unit with four L2 databanks and an L2 interface tile.

The starting point was the previous design known as Bobcat which was already optimized for power and so already heavily gated. The diagram below shows the number of flops that were still being clocked during a CPU halt, and how this amount decreased over a period of a few months using the PowerPro methdology.

One new block, the shared L2 cache controller, was not from the earlier design. The diagram below shows how the number of flops that are not gated falls dramatically as the focus of doing the design shifts from getting the functionality right to reducing the power.

AMD worked with Calypto to create and efficient RTL clock-gating analysis flow. RTL analysis could run over a weekend and analyze key power benchmark tests. The output was easy for designers to parse and make use of, and included recommendations for improvement and possible optimizations. Correlation between active clock count and total power was good. Ultimately the approach reduced dynamic power by approximately 20%, compared to an already power-optimized design.

Steve was the architect on this design for the clock, reset and power control signals for the Jaguar. All of these products made extensive use of clock gating to improve battery life. Steve’s white paper is available to download from here.

Full details of the DAC presentation, including links to register for either session are on the Calypto website here.

May 16, 2013June 14, 2019

Cadence Technical Sessions @ #50DAC (Free Food!)

Cadence Technical Sessions @ #50DAC (Free Food!)
by Daniel Nenni on 05-16-2013 at 10:00 am
Categories: Cadence, EDA

Cadence is a DAC anchor, everyone will visit their booth, so lets look at their technical sessions and put our agendas together. Lets start with the breakfast/lunch sessions because Cadence usually puts out quite a spread, we all gotta eat and free food tastes even better:

Has “Timing Signoff Innovation” Become an Oxymoron? What Happened and How Do We Fix It? Lunch
In this panel fielded by leading-edge technologists and venture capitalists, we will discuss the technology advances, or lack thereof, in the area of timing signoff. Timing signoff and closure is becoming the largest pole in the design flow tent with the increase in MMMC timing analysis views, lack of integrated signoff closure tools, and increasing variation factors. Each panelist will provide their insight into what’s needed from the EDA industry, academia, and users to ensure that innovation keeps pace with design needs.

The Cadence System-to-Silicon Verification Breakfast
Join us for a free breakfast to learn how next-generation system and SoC verification offerings from Cadence accelerate your system integration and reduce time to market. Learn about the newest capabilities of the Cadence System Development Suite, including Virtual System Platform virtual prototyping, Incisive® advanced verification, Palladium® acceleration and emulation, Rapid Prototyping Platform FPGA-based prototyping, and the Verification IP catalog, which adds new communication protocols and now supports acceleration and emulation. Listen to discussion about the latest methodologies for advanced verification and example applications from key Cadence customers. Be sure to bring your toughest questions for our experts panel.

Next lets look at the in-depth technology and methodology presentations targeted at creating the highest-quality silicon chips, systems-on-chip devices, and complete systems at lower costs. Sessions include the latest in signoff, mixed signal, low power, RTL-to-GDSII, custom, functional verification, verification IP, system development and hardware-software integration, high-level synthesis, PCB, and IC packaging:

lang: en_US

May 16, 2013June 14, 2019

Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification

Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification
by Eric Esteve on 05-16-2013 at 1:26 am
Categories: Uncategorized

We have seen last week in a first post how crucial was the IP qualification process (TSMC 9000) to increase the probability of successfully Tape Out a chip. Being able to discriminate between dangerous and safe IP is the first step of TSMC 9000 Quality process, IP tagging is the complementary step, almost as essential as the first one. That’s why, for every IP or Library going through TSMC 9000, an unique IP tag is created and inserted into its GDSII stream for identification.

IP tagging is supported by using VSIA standard specification, which can be found here

The IP Tag allows carrying the IP vendor information and IP denomination, and also all the quality information and production status of the specific IP or Library. When TSMC customer tapes out a chip, the GDSII data base will include for every IP the physical information used to generate masks, as usual, and also the information previously included in the tag (Vendor name, IP denomination, TSMC 9000 qualification process results, production status, etc.). Any designer who has participated in the tape-out phase knows that during these crazy days, where everybody is working under heavy stress, it sometimes happens that, for example, a wrong IP version can be used instead of the right one. TSMC IP tagging policy, linked with TSMC 9000 qualification process, will ensure that such a wrong IP will NOT pass through and lead to a “fatal” error, or failed prototypes.

Including soft-IP partners, TSMC IP Alliance counts more than 40 IP vendors (you can see the various company logos above). But what’s happen if you integrate an IP from a vendor not part of IP Alliance Partners? Does this necessarily mean that your design will not benefit from TSMC IP tagging? For the first time, TSMC enables “open access” to its TSMC9000 IP tagging “specification“, and non-IP Alliance members and IP industry can now have full access to the IP tagging specification, thus enjoy the full benefits of the program. As far as the vendor you have sourced the IP from decides to use the IP tagging (supported by using VSIA standard specification), your GDSII chip description can now completely support IP tagging!

IP vendors being part of the TSMC IP Alliance are supporting a total of 5500+ IP titles: remember that that mean that each of these IP have passed TSMC 9000 Qualification process. On the other hand, semiconductor is a fast moving industry, we see new protocols or mixed-signal functions emerging every year, and new IP vendor offering innovative products emerging, not yet being part of the TSMC IP Alliance just because joining the Alliance is a process which take time. With the IP tagging contribution (“TSMC9000 IP tag specification”), TSMC extends its Open Innovation Platform® (OIP) ecosystem to non-IP Alliance members, for the final benefit of the common customers.

For these IP vendors not yet part of the IP Alliance, accessing to TSMC IP tag specification can be a good way to build up quality/production track records within TSMC (OIP).

As a remark, the TSMC9000 IP Tag specification can be freely downloaded from:
http://www.tsmc.com/english/dedicatedFoundry/services/tsmc9000_iptag.htm
and the associated IP Tag utility will be provided upon request.

It will enables customers to have full visibility into the vendor IP’s quality and production status and from a market positioning point of view, enables the vendor to be on a faster track to become IP Alliance member. In other words, accessing “TSMC9000 IP Tag specification” program, is not only good for an IP vendor customers, but it’s also a good way to faster join TSMC IP Alliance, which in turn is certainly good for developing business!

Eric Esteve

May 15, 2013June 14, 2019

One-Stop Shop for Complete MIPI IP Solution

One-Stop Shop for Complete MIPI IP Solution
by Pawan Fangaria on 05-15-2013 at 8:00 pm
Categories: Arasan, IP

As we know mobile industry is one of the fastest growing in the electronics arena, and it has led to the emergence of several standards of interfaces between processors, devices, storage, camera, keyboard and so on. The interfaces can involve hardware as well as software and can be complex. The standards are still evolving, often leading to interoperability problems. We know, MIPI (Mobile Industry Processor Interface) Alliance, with several of its working groups is promoting open specifications for such interfaces. Well, that can ease out the interoperability problems and also optimality in terms of low power and pin count between multiple interconnections of mixed-signal devices, still one (the SoC integrator) has to deal with searching right vendors for different components; analog, IP, software with right standards; and this is a significant task considering plenty of suppliers with various offerings on various standards available in the MIPI IP market.

What’s the alternative? Close on a vendor who can provide all ranges of hardware, software, interfaces with matching versions of standards and in fact can act as your design partner to accelerate the process. When I came across the website of Arasan Chip Systems, there I found a whitepaper on MIPI and was impressed that they offer all IPs required for implementing complete MIPI standards. Following picture shows how Arasan IPs can be used to build an entire mobile device.

Arasan’s offering includes digital and analog IP, ESL models, software, VIP, test benches, compliance test vectors and so on. Arasan acts as a companion who designs and supports all its products ensuring complete interoperability between all IPs in the system.

It supports all important standards such as UFS (Universal File System), DSI (Display Serial Interface), CSI (Camera Serial Interface), SLIMbus (Serial Low-power Inter-chip Media Bus), PHY (Physical Layer Devices, D-PHY, M-PHY), UniPro (Unified Protocol) and DigRF (Digital Radio Frequency) including their physical layers and system side DMA and bus interfaces.

A standard MIPI architecture with UniPro having all layers (L1.5 to L4) can be represented as –

The PHY and UniPro products provide bus connections and are common to different standards controllers. Sample CSI-2 system architecture is represented as –

Sample DSI-2 system architecture is below –

Arasan offers both Host and Device SLIMbus cores that are fully compliant with the SLIMbus specification.

It also provides a SLIMbus Analyzer which is a versatile tool to assist in developing and debugging SLIMbus products. The system consists of hardware and software with user friendly GUI run on a PC.

Overall, Arasan provides complete range of IPs for mobile products with latest, powerful standards and can help accelerate time-to-market for these products. It’s worth looking at their portfolio of offerings.

Details of all these products can be found in Arasan’s whitepaper here.