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TSMC and Xilinx on the FinFAST Track!

TSMC and Xilinx on the FinFAST Track!
by Daniel Nenni on 06-23-2013 at 2:00 am

The power of the fabless semiconductor ecosystem never ceases to amaze me. On one hand you have the Intel backed press crowing about Intel stealing Altera from TSMC. On the other hand you have Xilinx and TSMC crowing about a new ‘one-team’ approach. If you are interested in the real story you’ve come to the right place.

“Altera’s FPGAs using Intel 14 nm technology will enable customers to design with the most advanced, highest-performing FPGAs in the industry,” said John Daane, president, CEO and chairman of Altera. “In addition, Altera gains a tremendous competitive advantage at the high end in that we are the only major FPGA company with access to this technology.”

“I am extremely confident that our ‘FinFast’ collaboration with TSMC on 16-nanometer will bring the same leadership results that we enjoyed at previous advanced technologies,” said Moshe Gavrielov, President and CEO of Xilinx. “We are committed to TSMC as the clear foundry leader in every dimension, from process technology to design enablement, service, support, quality, and delivery.”

The one disadvantage of the fabless semiconductor ecosystem and crowd sourcing in general is that you are working with companies that also work with your competitors. That is certainly the case with TSMC since just about every fabless semiconductor company manufactures at TSMC and TSMC is bound by honor (The Trusted Technology and Capacity Provider) to provide a level playing field for all customers. The only thing worse would be if the company that manufactures your product competes directly with you, just ask Apple!

“We look forward to collaborating with Altera on manufacturing leading-edge FPGAs, leveraging Intel’s leadership in process technology,” said Brian Krzanich, chief operating officer, Intel. “Next-generation products from Altera require the highest performance and most power-efficient technology available, and Intel is well positioned to provide the most advanced offerings.”

“We are committed to working with Xilinx to bring the industry’s highest performance and highest integration programmable devices quickly to market,” said Morris Chang, TSMC Chairman and CEO. “Together we will deliver world-class products on TSMC’s 20SoC technology in 2013 and on 16FinFET technology in 2014.”

This was certainly the case for Altera and Xilinx at TSMC. The flow of information and collaboration was definitely guarded knowing full well that any process improvement would benefit both companies. Altera moving to Intel changed that of course, a change for the better in regards to the greater good of the fabless semiconductor ecosystem. Putting the number one foundry (TSMC) in close collaboration with the number one provider of programmable technologies and devices (Xilinx) could be a serious game changer, absolutely. Look for a Xilinx flavored version of the 16nm process for higher performance applications like FPGAs, CPUs, and GPUs. Just my opinion of course.

Let’s look at the FUD side of this:

  • Intel as a foundry is an unknown
  • How fast will Altera be able to build a competitive Intel based ecosystem?
  • Intel as an FPGA manufacturer is an unknown
  • Will Intel eat crow and sign an ARM Manufacturing deal? (ARM cores are big in the FPGA world)
  • Or will Intel force Atom on Altera?
  • What happens to the other Intel FPGA partners Tabula and Achronix?

I’m not questioning Altera’s decision to partner with Intel. It was definitely the right thing to do given Xilinx seriously challenged them at 28nm and will again at 20nm. Competition fuels our industry and Intel/Altera are a competitive threat so it is for the greater good.

I do however question the Intel biased spin on the situation and the constant bashing of the fabless semiconductor ecosystem. My opinion, Intel will rue the day they openly attacked QCOM, ARM, TSMC, and the rest of the fabless crowd, believe it. Hey Mr. Intel, this is not the microprocessor world you have controlled since the beginning of time. You are not in Kansas anymore Dorothy.

lang: en_US


Pat Pistilli: the first cell library, the first computer-printed label and more

Pat Pistilli: the first cell library, the first computer-printed label and more
by Paul McLellan on 06-22-2013 at 1:45 pm

At the DAC 50th anniversary banquet, Pat Pistilli won the award for most tenacious attendee, having been to all 50 DACs. Well, and for creating DAC and sustaining it. He was general chair for the first DAC (not yet called DAC) and, of course, would eventually form MP Associates with his wife Marie, which still runs DAC today. In 2010 he won the Kaufman award and I interviewed him back then about the early days of EDA. Here it is again:

Pat, who was at Bell Labs, started DAC (then called SHARE, the Society to Avoid Redundant Effort) in 1964 along with a co-conspirator from IBM. The first conference was in Atlantic City in 1964. This eventually became DAC. When the availability of commercial EDA tools made DAC too big to manage as an all-volunteer organization as it had been, Pat left the technical side of design automation to form MP Associates along with his wife Marie. I think that the history of DAC has been well-covered elsewhere so instead, I asked Pat, what was “design automation” back when he started in the business. After all, transistors were fairly new, printed circuit boards hadn’t been invented, integrated circuits were in research and so on.

He told me about the design system he worked on, known as BLADES (for Bell LAbs DEsign System). It ran on an IBM704 with 32K of memory. Think about how little that is: 32 gigabytes (too big for a notebook but not for a high-end server) is a million times as much. The computer had 32 tape-drives (disks were another thing that hadn’t yet been invented). They built the design system to work on a specific project, the Safeguard anti-missile system for the DoD. It was an electronic system so large it occupied 3 buildings.

The system was built like this. At the lowest level were modules which contained 3 or sometimes as many as, dramatic pause, 4 transistors with wire-wrap terminals (if you are too young to know what wire-wrap is, then more than you want to know is here). Boards 33″ by 24″ were covered in these modules with gaps in between to run the wires (because if you ran wires over the tops of the modules you’d never be able to open them again for maintenance). Originally there were 8 different kinds of modules but eventually they ended up with about 30 (that sounds familiar in libraries today). Initially these modules were hard-wired into the code but Pat came up with the idea of putting all the components into a file on a magnetic tape and extracting them from there (the first cell-library I guess). The design rules, for example no wire could be longer than 12″, were on another tape.

These boards were stacked into refrigerator-sized units called frames with more wire-wrap to construct what today we’d call a back-plane. Then lots of these units would then be connected together with manually labeled wires until you’d filled 3 buildings.

Before Pat’s design automation it took 4-5 months to design one of these boards and then another month for the board to be wire-wrapped by hand. Afterward, using the design system, the time was cut to around a month but it still took another month for the hand wire-wrapping.
Then Gardner Denver developed an automatic wire-wrap machine. Pat designed a controller for this (complicated by the need for ‘dressing fingers’ since they couldn’t route point to point and had to avoid wires going over the modules). Now the design automation system could (effectively) directly manufacture the board. That got the time down from a month to a day or two.

This is one example of how manufacturing used to be much more connected to engineering, and delivering a system would often involve people needing to work in all sorts of areas. Software engineers today don’t have to change the design of the semiconductor manufacturing equipment!

The wires that connected the frames were manually labeled. But hand-written labels aren’t always legible, and the glue wasn’t good so they would regularly fall off leading to obvious problems. Pat decided they needed a new way of labeling where the labels could be printed automatically and would stick on the cables properly and never fall off. The only material he could find that seemed like a good starting point was the plastic sheet that 3M used to make band-aids. So he got band-aid material from 3M and would attach it to paper and print the labels using a standard line-printer. But the adhesive still wasn’t good enough so he got the chemical department at Bell Labs to invent a new super-strong adhesive and, further, to develop a coating for the plastic that would accept the ink (so it could be printed) but not dirt so the labels would stay clean and legible. They still needed 3M to supply the original plastic material and to do the die-cutting afterward. Finally, Pat modified a manual wire-wrap gun with a new chuck to create a tool that attached the labels to the wires, inspired by having seen cigarettes being made on a factory tour. These were the first ever machine-prepared labels.

3M actually branched off that part of the business to form a label-making subsidiary called Avery. Yes, the same Avery as makes labels for your inkjet today.

So what happened when three buildings worth of electronics was shipped out to an island in the Pacific? Safeguard was constructed because the US figured that they couldn’t build enough interceptors to destroy every incoming missile. But they also figured out that the USSR couldn’t afford to build that many warheads so that they would use decoys too. Safeguard analyzed the incoming missile trajectories looking for tiny differences in flight path to decide which were real and which were decoys. Pat was invited out to the Pacific for the first test and it was a complete success. The system picked out the one real missile from the five decoys and knocked it down.

Interestingly, in the early days there were big problems getting acceptance of this new technology. Designers didn’t want to use the design system since they worried it would obstruct their creativity. And the manufacturing people were worried that the automation would lose them their jobs. When Pat moved to Denver in 1969 it was the first time AT&T had both design and manufacturing under the same roof. When he arrived the manufacturing manager told him “I hate computers.” Back then the design methodology was that Bell Labs would design the system and build prototypes, then the design would be transferred to Western Electric (the manufacturing arm) who would completely re-lay it out. With the design system this became unnecessary, the prototype could be transferred direct into manufacturing and this became a model for the rest of Western Electric. The system produced cost savings of $2M per year immediately. Since AT&T was a regulated utility, the only way for them to increase profitability was to reduce their costs since they didn’t really have any way to increase their prices. So this was a big deal and the manufacturing manager changed his tune.


Can we really find a way to speed-up Processor & DSP core designs?

Can we really find a way to speed-up Processor & DSP core designs?
by Eric Esteve on 06-21-2013 at 9:05 am

Once upon a time, ASIC designers involved in Processor design, like I was, for the first time in 1987 for Thomson CSF and again in 1994 for Texas Instruments, at that time supporting height (8) ASIC designed by another French company, the Advanced Computer Research Institute (ACRI), had to re-invent the wheel almost every day. When you discover the “Set-up” and “Hold” time in a DFF feature list, at first you don’t realize that these very specific DFF features will ultimately dictate the Supercomputer minimum cycle time, so the machine most important performance (modest at that time, as the maximum frequency was 20… MHz!).

Thanks to this first experience, I was not so surprised when ACRI Engineering management had announced in 1994 to TI sales guys (including myself) that they will preferably use custom Flip Flops, designed on request by Phoenix VLSI, a very talented design team located in the UK. In fact, if you can reduce by design techniques the Set-up and Hold time to zero, or even to a negative number, you probably increase the basic cycle time by 20% or so. The only problem was that “somebody” had to run characterization on these custom cells, automatically generates the models you need to simply pass through the ASIC design flow… Somebody was again me, and I enjoyed spending 3 months in TI Bedford, in the north of the UK (during winter) that I certainly recommend to whoever thinks his life is boring: after Bedford, any location is like Disneyland.

I never forgot these very busy, but also very creative days! That’s why, when I had a look at the recent announcement of DesignWare HPC Design Kit from Synopsys (for Optimizing All Processor Cores), including specific DFF and Embedded memories targeted to design teams in charge of Processor or DSP core development, I really understand how powerful this HPC Design Kit can be. In fact, I think that designers of the 2010’s are literally spoiled, when comparing with the designers operating in the 1980’s: at that time we had to invent the wheel every day, when Synopsys just did it one time, so designers just have to use it. If you take a deep look at the above picture, you will see that Synopsys is also offering Multi-Bit DFF, which is a good way to reduce both power consumption and timing disparities (between DFF from the same data flow).

In the reality, Processor or DSP core design performance is not limited to only DFF: Synopsys has created a completely new and optimized library counting more than 125 new standard cells and memory instances. And we know that in 2013, for a Processor, a GPU or a DSP, the most important feature is nor raw performance, but power efficiency. Better to compare delivered MIPS per consumed Watt or portion of Watt than only pure MIPS. Especially when the Processor, GPU or DSP is going to be used in a mobile application, which, in fact, is most often the case, as all of us tend to buy a Notebook, a smartphone or a Media tablet instead of these heavy (computer) machines which have made Intel very rich in the 1990’s and b/o 2000’s. HPC Design kit has been developed to take into account all 3 dimensions of the mid 2010’s design:

  • Performance: giving up to 10% performance improvement on Host CPU
  • Power: up to 25% less power consumption for a GPU
  • Area: lower by 10% on the same GPU example

It’s important to notice that Synopsys has developed this Design Kit in collaboration with Imagination Technologies (GPU cores), CEVA (DSP cores) and Verisilicon (CPU cores and ASIC Design Services). Being directed by the future customers is always a good practice! They seems to be satisfied, according with their feedback:

“The physical IP used for implementing processor cores has a tremendous impact on the achievable power, performance and area of the design,” said Nianfeng Li, corporate vice president of design methodologies and program management at VeriSilicon. “When we consider all the factors that contribute to an optimized implementation, the DesignWare Duet Embedded Memories and Logic Libraries have been a primary contributor to the performance gains we realized on the recent hardening of a leading CPU core. The new DesignWare HPC Design Kit contains the specialty cells and SRAMs we need to achieve the highest possible performance on advanced processor cores while minimizing area and power consumption.”

“DSPs are a fundamental component of every advanced electronic product, from smartphones and tablets to smart TVs and base stations, and each design has unique optimization requirements,” said Eran Briman, vice president of marketing at CEVA, Inc. “In addition to extreme performance, designers rely on our DSP cores to consume as little power and occupy as little silicon area as possible. We look forward to continued collaboration with Synopsys in helping our mutual customers achieve their strict design goals.”

For those who are skeptical, and just think this is simply a post-DAC announcement, you should have a look at the above picture, listing the measured characteristics of a dual-port Register File used in a GPU design.

If you want to can get an exhaustive summary and precisely see which Library cell or specific memory to use to improve Performance (purple bullet), Area (orange bullet) or Power consumption (green bullet), the table below will give you a quick direction:

Just a last point: Synopsys also offer associated Design Services, very specific to HPC Design Kit and Processor, GPU or DSP core design.

By Eric Esteve from IPNEST

lang: en_US


Agilent ADS Users, Find Out About Design Data Management

Agilent ADS Users, Find Out About Design Data Management
by Paul McLellan on 06-20-2013 at 1:47 pm

In May, ClioSoft and Agilent announced that Agilent’s Advanced Design System (ADS) was now integrated with ClioSoft’s SOS Design Data Management. I interviewed Greg Peterschmidt of Agilent at that time. The information page for the combined product, known as SOS viaADS is here.

 

Next week ClioSoft is presenting a webinar to help users of Agilent’s ADS with version control and enterprise-wide design data management. The webinar will introduce and demonstrate ClioSoft’s SOS viaADS, a new product resulting from a joint development effort between ClioSoft and Agilent Technologies. The webinar will be presented by Karim Khalfan, Technical Marketing Engineer of ClioSoft.

The webinar is on Wednesday June 26th at 10am Pacific Time. It is targeted to RF, microwave and high-speed digital design engineers who use ADS (or are thinking of doing so) and their supporting CAD engineers and managers.

Topics to be covered in the webinar.

  • Design management (DM) features to be covered include:
  • Version control of libraries, cells and views
  • Auto check-out and check-in when a view is edited
  • Check-out locks to prevent concurrent changes
  • Easy rollback to previous revisions
  • Data management operations for an entire design hierarchy
  • Multi-site global collaboration

Register for the webinar here.

ClioSoft is the premier developer of hardware configuration management (HCM) solutions. The company’s SOS™ Design Collaboration platform is built from the ground up to handle the requirements of hardware design flows. The SOS platform provides a sophisticated multi-site development environment that enables global team collaboration, design and IP reuse, and efficient management of design data from concept through tape-out. Custom engineered adaptors seamlessly integrate SOS with leading design flows – Cadence’s Virtuoso® Custom IC, Synopsys’ Galaxy Custom Designer, Mentor’s IC flows, and SpringSoft’s Laker™ Custom Layout Automation System. ClioSoft’s innovative Universal DM Adaptor technology “future proofs” data management needs by ensuring that data from any flow can be meaningfully managed. The Visual Design Diff (VDD) engine enables designers to easily identify changes between two versions of a schematic or layout by graphically highlighting the differences directly in the editors.

Also Read

The Only DM Platform Integrated with All Major Analog and Custom IC Design Flows

Supporting the Customer Is Everyone’s Job

Cliosoft CEO on Design Collaboration Challenges!


DAC by the Numbers

DAC by the Numbers
by Paul McLellan on 06-20-2013 at 12:03 pm

The attendance numbers for DAC are out. Unless you have been living under a stone you know that DAC was in Austin Texas a couple of weeks ago. Attendance was:

  • full conference passes: 1589
  • exhibits-only passes: 2364
  • booth staff: 1998

The registration is slightly lower than last year when DAC was in San Francisco (as it will be again for the next two years). However, there was an increase in technical session attendance. The combined keynote attendance was way up from 2012 but I think that probably is mostly due to having more keynotes this year. The numbers were also higher than 2011 numbers in San Diego, the last time DAC was held outside the bay area.

On Monday, walking around the exhibit hall, DAC felt just as busy as usual. As always, later in the week it felt less busy but talking to several companies, everyone seemed very happy with attendance, with no shortage of people from the Austin area itself and no shortage of people who had come from the bay area. International attendance did seem to be down, however.

Networking opportunities were one of the highlights at the 50[SUP]th[/SUP] DAC, with a well-attended kick off reception on Sunday night, a jam-packed musical evening at Austin City Limits on Monday for DAC’s 50th anniversary party and daily receptions at the Austin Convention Center. Not to mention the Denali party and various press events. The DAC Anniversary Banquet on Wednesday evening was sold out before the conference started. The banquet gave recognition to the volunteers and contributors that have made DAC successful for the past 50 years.

To see the SemiWiki DAC coverage click HERE.

The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), the Electronic Design Automation Consortium (EDA Consortium), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design.


SEMICON West: My Top Picks

SEMICON West: My Top Picks
by Paul McLellan on 06-20-2013 at 11:21 am

I will be at Semicon West from 9th to 11th July in Moscone, San Francisco. Of course there are lots of interesting sessions but here are two that I think are especially important to get a good impression of the way things are going in the future from experts. The two most interesting questions about the future are what comes after 14nm, and is EUV ever going to work for volume manufacturing. These two sessions look at exactly these issues.

On Tuesday 9th from 10.30 to 12.30 in TechXpot South (in the south hall) is Leveraging Non-Planar Transistors and New Materials to Power Mobility Apps Beyond 20nm. The session is actually divided into 6 subsections:

  • Michael Haond, FD-SOI Technology Director for STMicroelectronics on Main Features and Benefits of 14nm Ultra Thin Body and Box (UTBB) FD-SOI Technology. FD-SOI is the alternative to FinFET for getting the channel thin enough to get good control by the gate, and ST is the leading company developing the technology (GlobalFoundries will also have FD-SOI as well as FinFET).
  • Subrmani Kengeri, VP Advanced Technology Architecture of GlobalFoundries, on Enabling SoC Level Differentiation Through Advanced Technology R&D. Global as the #2 foundry has to differentiate itself from TSMC in technology, not just price.
  • George Gomba, VP Semiconductor Process R&D at IBM on Meeting the Challenges of Next Generation Scaling. I always learn a lot listening to IBM talking about the futures of process development. And IBM is in the Common Platform Alliance with Global and Samsung.
  • Paul Kirsch, Director of Front-end Processes at Sematech on Non-silicon R&D Challenges and Opportunities. I’m not sure if he is going to be talking about carbon nanotubes or just germanium, gallium etc.
  • Adam Brand, Director of Transistor Technology Group at Applied Materials on Precision Materials to Meet FinFET Scaling Challenges Beyond 14nm. The FinFET roadmap to 14nm is pretty clear but beyond it is definitely murky.
  • Joe Sawicki, VP Design to Silicon Division of Mentor Graphics on New Approaches to Improving Quality and Accelerating Yield Ramp for FinFET Technology. Since Calibre is the de facto standard for RET, hearing what Mentor has to say about this area is important.

Full details on the session here.

On Wednesday, same time same place, 10.30am to 12.35pm in TechXpot South, is Still a Tale of Two Paths: Multipatterning Lithography at 20nm and Below: EUVL Source and Infrastructure Progress. If you want to know if EUV or DSA are ever going to be real, this is the place to come and find out. I learned a lot at the equivalent session last year.

  • Stephen Renwick, Sr Research Scientist at Nikon on ArF Lithography Extension Through Advanced Overlay and Imaging Solutions.
  • Stefan Wurm, Director of Lithography at Sematach, on EUV Status and Outlook. If anyone knows what is actually happening, he does.
  • Skip Miller, Director of Strategic Marketing at ASML on ASML’s NXE Platform Performance and Volume Introduction. ASML with investments from Intel, TSMC and Samsung is the company developing EUV lithography steppers, light sources etc
  • Ben Rathsack, Manager Clean Track Advanced Technology Group at Tokyo Electron America on Advances in Directed Self-Assembly Integration and Manufacturability on 300mm Wafers. DSA involves mixing non-mixable polymers and having them align themselves into rows or grids. It has gone from an academic research of little practical interest to a serious contender for how we might manufacture below 10nm.
  • Mike Rieger, Group Director of R&D in the Silicon Engineering Group at Synopsys on Collaboration to Deliver Lithography Solutions.

Full details on the session here.


What does 3D IC, FinFETs, and EUV have in common?

What does 3D IC, FinFETs, and EUV have in common?
by Daniel Nenni on 06-19-2013 at 6:00 pm


They are three of the top trending terms on SemiWiki and three of the hot topics at this year’s Semicon West:

In its 43rd year, SEMICON West is the flagship annual event for the global microelectronics industry. It is the premier event for the display of new products and technologies for microelectronics design and manufacturing, featuring technologies from across the microelectronics supply chain, from electronic design automation, to device fabrication (wafer processing), to final manufacturing (assembly, packaging, and test). More than semiconductors, SEMICON West is also showcase for emerging markets and technologies born from the microelectronics industry, including micro-electromechanical systems (MEMS), photovoltaics (PV), flexible electronics and displays, nano-electronics, solid state lighting (LEDs), and related technologies.

The semiconductor ecosystem is showcased at SEMICON West with over 50 hours of technical programs and 600+ exhibitors. To see what’s new check out theSilicon Innovation Forum which brings together new and emerging companies with the semiconductor industry’s top strategic investors and leading technology partners. Paul McLellan and I will be blogging live from SEMICON West this year so stay tuned to SemiWiki if you can’t make it.

3D IC: What the leaders are saying about the techniques, technologies, trends and applications for stacked chips

[TABLE] style=”width: 579px”
|-
| colspan=”2″ style=”width: 25%” | Tuesday, July 9, 2013
|-
| valign=”top” style=”width: 25%” | 10:30am-12:30pm

| Generation Mobile: Enabled by IC Packaging Technologies
Hosted by the Advanced Packaging Committee, SEMI Americas TechXPOT North, North Hall
|-
| style=”width: 25%” |

|

|-
| valign=”top” style=”width: 25%” | 1:30pm-4:45pm

| IEEE/CPMT Workshop on:“THIN IS IN”: Thin Chip & Packaging Technologies as Enablers for Innovations in the Mobility Era
San Francisco Marriott Marquis
|-
| style=”width: 25%” |
|
|-
| colspan=”2″ style=”width: 25%” | Wednesday, July 10, 2013
|-
| valign=”top” style=”width: 25%” | 1:00pm-3:30pm
| Advancing 2.5D and 3D Packaging through Value Engineering
Hosted by the Advanced Packaging Committee, SEMI AmericasTechXPOT North, North Hall
|-
| style=”width: 25%” |
|
|-
| colspan=”2″ style=”width: 25%” | Thursday, July 11, 2013
|-
| valign=”top” style=”width: 25%” | 10:30am-1:00pm
| MEMS & Sensor Packaging for the Internet of Things
Hosted by the Advanced Packaging Committee, SEMI AmericasTechXPOT North, North Hall
|-
| style=”width: 25%” |
|
|-
| valign=”top” style=”width: 25%” | 1:30pm-3:35pm
| ITRS Back End of Line Technologies (Partner Event)
TechXPOT North, North Hall

|-

Leveraging Nonplanar Transistor Architectures and New Materials
to Power Mobility Apps Beyond 20nm

Tuesday, July 9, 2013
10:30am–12:30pm
South Hall, Moscone Center

[TABLE] style=”width: 100%”
|-
| colspan=”3″ valign=”top” style=”width: 10%” |
|-
| colspan=”3″ valign=”top” style=”width: 10%” | The mobile market is driving the semiconductor industry to continue its move to transistor architectures that offer greater performance and power benefits than traditional planar architectures. There is not, however, only one way to achieve the required performance. IC manufacturers are pursuing different strategies including leveraging innovations in design rules. To continue the pace of development below 20nm, however, the industry will need to find suitable new channel materials and processes (e.g., MOCVD). This session will present various transistor architecture options below 20nm and the status of channel materials development. Additionally, inspection and metrology challenges associated with new materials will be discussed.
|-
| valign=”top” |
|
|
|-

[TABLE]
|-
| valign=”top” style=”width: 22%” | 10:30am-10:50am
| valign=”top” style=”width: 20%” |
| valign=”top” | Main Features and Benefits of 14nm Ultra Thin Body and BOX(UTBB) Fully Depleted SOI (FD-SOI) Technology

Michel Haond(Biography)
FD-SOI Technology Director
STMicroelectronics

|-
|
|

|

|-
| valign=”top” | 10:50am-11:10am
| valign=”top” |
| valign=”top” | Enabling SoC Level Differentiation Through Advanced
Technology R&D


Subramani Kengeri (Biography)

Vice President, Advanced Technology Architecture, Office of the CTO
GLOBALFOUNDRIES
|-
|
|

|

|-
| valign=”top” | 11:10am-11:30am
|

| Meeting the Challenges of Next-Generation Scaling

George Gomba
VP, Semiconductor Process R&D
IBM

|-
|
|

|

|-
| valign=”top” | 11:30am-11:50am
|
| Non-Silicon R&D Challenges and Opportunities

Paul Kirsch, Ph.D. (Biography)
Director, Front End Processes
SEMATECH
|-
|
|

|

|-
| valign=”top” | 11:50am-12:10pm
|
| valign=”top” | Precision Materials to Meet FinFET Scaling Challenges Beyond 14nm

Adam Brand
(Biography)

Director, Transistor Technology Group
Applied Materials
|-
| valign=”top” |
|

|
|-
| valign=”top” | 12:10pm-12:30pm
|
| valign=”top” | New Approaches to Improving Quality and Accelerating Yield Ramp for FinFET Technology

Joe Sawicki (Biography)
Vice President and General Manager, Design-to-Silicon Division
Mentor Graphics

|-
| valign=”top” |

|

|
|-
| valign=”top” | Session Moderator:
| colspan=”2″ | Debra Vogler (Biography)
President, Instant Insight

|-

Still a Tale of Two Paths: Multi-patterning Lithography at 20nm and Below:
EUVL Source and Infrastructure Progress


Wednesday, July 10, 2013
10:30am–12:35pm
South Hall, Moscone Center

[TABLE] style=”width: 100%”
|-
| style=”width: 25%” |

|
|
|-
| colspan=”3″ style=”width: 10%” | DescriptionThough progress to take EUVL into the realm of high-volume manufacturing continues to be made, the readiness of the source technologies to take on HVM are still not known with a high degree of certainty. The challenges facing source development are still average power, dose stability and uptime. EUV mask and resist infrastructure readiness activities must also come together in time and address such challenges as defect density (for masks), and line edge roughness, sensitivity, and resolution for resists. No doubt, there will be multiple opportunities to insert EUVL into lower volume production lines – such opportunities will be based on specific products and device applications. Until EUVL is ready for HVM, the industry must continue to rely on double-patterning and even multiple-patterning lithography schemes using 193 immersion lithography to take it beyond 22nm. Speakers will present the current status of EUVL readiness, as well as discuss the current plans and challenges of extending 193i with double and multiple-patterning.

|-
|
|
|
|-

[TABLE]
|-
| style=”width: 22%” | 10:30am-10:55am
| style=”width: 22%” |
| ArF Lithography Extension Through Advanced Overlay and Imaging Solutions

Stephen Renwick, Ph.D. (Biography)
Sr. Research Scientist
Nikon Research Corporation of America


|-
|

|

|
|-
| 10:55am-11:20am
|
| EUV Status and Outlook

Stefan Wurm, Ph.D. (Biography)
Director of Lithography

SEMATECH


|-
|

|

|
|-
| 11:30am-11:45am
|

| ASML’s NXE Platform Performance and Volume Introduction

Skip Miller(Biography)
Director of Strategic Marketing
ASML


|-
|

|

|
|-
| 11:45am-12:10pm
|
| Advances in Directed Self-Assembly Integration and Manufacturability on 300mm Wafers

Ben Rathsack, Ph.D. (Biography)

Manager, CLEAN TRACK Advanced Technology Group, Member of Technical Staff for the Semiconductor Production Equipment (SPE) Division

Tokyo Electron America


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| 12:10pm-12:35pm
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| Collaboration to Deliver Lithography Solutions

Mike Rieger (Biography)
Group Director, R&D, Silicon Engineering Group
Synopsys

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| Session Moderator:
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Vivek Bakshi (Biography)
Founder and President of EUV Litho, Inc

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lang: en_US


Static Low-Power Verification in Mixed-Signal SoC Designs

Static Low-Power Verification in Mixed-Signal SoC Designs
by Daniel Payne on 06-19-2013 at 2:02 pm

IC designer Shubhyant Chaturvediof AMD used EDA tools from Mentor Graphicsand Concept Engineeringto perform static, low-power verification of a mixed-signal SoC design with a combined CPU and GPU. Shubhyant presented a poster session at DAC two weeks ago in Austin, and I wanted to share it with my readers here at SemiWiki.
Continue reading “Static Low-Power Verification in Mixed-Signal SoC Designs”


A New STA Tool at DAC, No Not Cadence

A New STA Tool at DAC, No Not Cadence
by Daniel Payne on 06-19-2013 at 12:15 pm

The big EDA companies get big attention at DAC, however sometimes the little EDA start-ups like Arcadia Innovationhave a new product that can be overlooked. On Tuesday at DAC I met with Joey Lin, founder of Arcadia Innovation and learned about his new STA (Static Timing Analysis) tool called TimeHawk .

Continue reading “A New STA Tool at DAC, No Not Cadence”