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Can we really find a way to speed-up Processor & DSP core designs?

Can we really find a way to speed-up Processor & DSP core designs?
by Eric Esteve on 06-21-2013 at 9:05 am

Once upon a time, ASIC designers involved in Processor design, like I was, for the first time in 1987 for Thomson CSF and again in 1994 for Texas Instruments, at that time supporting height (8) ASIC designed by another French company, the Advanced Computer Research Institute (ACRI), had to re-invent the wheel almost every day. When you discover the “Set-up” and “Hold” time in a DFF feature list, at first you don’t realize that these very specific DFF features will ultimately dictate the Supercomputer minimum cycle time, so the machine most important performance (modest at that time, as the maximum frequency was 20… MHz!).

Thanks to this first experience, I was not so surprised when ACRI Engineering management had announced in 1994 to TI sales guys (including myself) that they will preferably use custom Flip Flops, designed on request by Phoenix VLSI, a very talented design team located in the UK. In fact, if you can reduce by design techniques the Set-up and Hold time to zero, or even to a negative number, you probably increase the basic cycle time by 20% or so. The only problem was that “somebody” had to run characterization on these custom cells, automatically generates the models you need to simply pass through the ASIC design flow… Somebody was again me, and I enjoyed spending 3 months in TI Bedford, in the north of the UK (during winter) that I certainly recommend to whoever thinks his life is boring: after Bedford, any location is like Disneyland.

I never forgot these very busy, but also very creative days! That’s why, when I had a look at the recent announcement of DesignWare HPC Design Kit from Synopsys (for Optimizing All Processor Cores), including specific DFF and Embedded memories targeted to design teams in charge of Processor or DSP core development, I really understand how powerful this HPC Design Kit can be. In fact, I think that designers of the 2010’s are literally spoiled, when comparing with the designers operating in the 1980’s: at that time we had to invent the wheel every day, when Synopsys just did it one time, so designers just have to use it. If you take a deep look at the above picture, you will see that Synopsys is also offering Multi-Bit DFF, which is a good way to reduce both power consumption and timing disparities (between DFF from the same data flow).

In the reality, Processor or DSP core design performance is not limited to only DFF: Synopsys has created a completely new and optimized library counting more than 125 new standard cells and memory instances. And we know that in 2013, for a Processor, a GPU or a DSP, the most important feature is nor raw performance, but power efficiency. Better to compare delivered MIPS per consumed Watt or portion of Watt than only pure MIPS. Especially when the Processor, GPU or DSP is going to be used in a mobile application, which, in fact, is most often the case, as all of us tend to buy a Notebook, a smartphone or a Media tablet instead of these heavy (computer) machines which have made Intel very rich in the 1990’s and b/o 2000’s. HPC Design kit has been developed to take into account all 3 dimensions of the mid 2010’s design:

  • Performance: giving up to 10% performance improvement on Host CPU
  • Power: up to 25% less power consumption for a GPU
  • Area: lower by 10% on the same GPU example

It’s important to notice that Synopsys has developed this Design Kit in collaboration with Imagination Technologies (GPU cores), CEVA (DSP cores) and Verisilicon (CPU cores and ASIC Design Services). Being directed by the future customers is always a good practice! They seems to be satisfied, according with their feedback:

“The physical IP used for implementing processor cores has a tremendous impact on the achievable power, performance and area of the design,” said Nianfeng Li, corporate vice president of design methodologies and program management at VeriSilicon. “When we consider all the factors that contribute to an optimized implementation, the DesignWare Duet Embedded Memories and Logic Libraries have been a primary contributor to the performance gains we realized on the recent hardening of a leading CPU core. The new DesignWare HPC Design Kit contains the specialty cells and SRAMs we need to achieve the highest possible performance on advanced processor cores while minimizing area and power consumption.”

“DSPs are a fundamental component of every advanced electronic product, from smartphones and tablets to smart TVs and base stations, and each design has unique optimization requirements,” said Eran Briman, vice president of marketing at CEVA, Inc. “In addition to extreme performance, designers rely on our DSP cores to consume as little power and occupy as little silicon area as possible. We look forward to continued collaboration with Synopsys in helping our mutual customers achieve their strict design goals.”

For those who are skeptical, and just think this is simply a post-DAC announcement, you should have a look at the above picture, listing the measured characteristics of a dual-port Register File used in a GPU design.

If you want to can get an exhaustive summary and precisely see which Library cell or specific memory to use to improve Performance (purple bullet), Area (orange bullet) or Power consumption (green bullet), the table below will give you a quick direction:

Just a last point: Synopsys also offer associated Design Services, very specific to HPC Design Kit and Processor, GPU or DSP core design.

By Eric Esteve from IPNEST

lang: en_US

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