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ARM Signs 48 New Licenses in Q3

ARM Signs 48 New Licenses in Q3
by Paul McLellan on 10-22-2013 at 3:15 pm

ARM announced their quarterly results early this morning. ARM’s results are a funny mixture of backward looking information such as royalties which are reported a quarter late since they have to wait for their licensees to work out how many they shipped, and some very forward looking such as new licenses, which bring some current revenue but are also setting up a future revenue stream at least a few quarters out.


On the licensing front, which is perhaps the best indication of how rosy the future of ARM is, they had a record number of new licenses at 48. Previously the record wasn’t even close, in the mid 30s. Perhaps even more importantly, 11 of these new licensees were new companies taking out their first ARM license. Who are they? There are 14 licensees to mobile and computing applications including entry level smartphones, tablets and 2-in-1 laptops. 18 liceenses for microcontrollers and sensors for the internet of things applications, 7 licensees for wide wireless enterprise networking and 9 licensees for other consumer electronic applications such as digital TVs. One especially large multi-license deal was with MediaTak (who power a lot of low-cost Chinese smartphones).

On the 64 bit front, which was such a big deal at the Linley conference last week, AMD, Broca, Mali, announced ARM-based chips that support 64-bit for mobile infrastructure and enterprise networking applications. Included in the new licensees were further four Cortex-A50 series processors which includes above 64-bit computing. To date ARM has now signed 24 Cortex-A50 series licensees.

On the royalty front, ARM continues to outperform the semiconductor industry and despite the industry being down 2% year-on-year in the relative period, ARM royalty revenue was up by 14%. You see this in TSMC’s numbers too, that reflect the relative strength of the fabless ecosystem compared to traditional IDMs. These are royalties based on what how many cores were shipped in Q2.

Just how many? 2.5 billion. Presumably even more in Q3.


Of course a lot of these are in mobile. But not as many as you think. As Simon Segars said on the conference call:”Shipments of embedded ARM based chips well are particularly strong and non-mobile chip shipments now account to more than half of ARM’s total royalty shipments.”

And how are ARM doing in the server/networking space, which as traditionally been a MIPS/PowerPC/Intel stronghold? ARM is also beginning to see traction of shipments in enterprise networking applications as the first of the early adopters start to ramp into high volume. More than 15 million Cortex-A enterprise networking chips were reported in Q3.


I’m not that interested in the quarterly revenue numbers, compared to this more qualitative data on industry dynamics. But for the record, revenue was $287M up 26%. Processor licensing revenue was up over 50% year on year.

Transcript of the conference call at Seeking Alpha is here.

Next week it is ARM TechCon at the Santa Clara Convention Center from October 29-31. 5000 people are expected. More information is here. I’ll see you there. Here is Simon Segars previewing ARM TechCon:


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Cloud-RAN: a New Way to Build a Basestation

Cloud-RAN: a New Way to Build a Basestation
by Paul McLellan on 10-21-2013 at 11:01 pm

One thing that I learned about at the Liney Microprocessor Conference last week was C-RAN which stands for Cloud Radio Access Networks. The technology is created by ASOCS who are working with China Mobile as the driving customer. And before you dismiss that as just being one network interested in the technology, China Mobile has more subscribers than all US and European networks combined.

So what is C-RAN? The most efficient way to deliver computing power these days is using very large server farms and virtualization. Getting the whole virtualization infrastructure to work perfectly is by no means trivial, it was one of Google’s big advantages in the early days, but once you have it is easy to scale by adding another 1,000 or even 100,000 servers. C-RAN is taking that approach to all the signal processing in a cellular base-station. Normally today there is complex digital signal processing at the antenna head, and another lot in the base-station itself. With C-RAN, the simplest possible processing is done at the antenna and the resulting data is sent by high-speed fiber-optic links to the cloud datacenter where the real signal processing is done.

Gilad Garon, the CEO, presented ASOCS’s solution, which is basically add-on PCI for basic servers to do the signal processing. Think of a server farm of thousands of servers, each with its own offload board to do the specialized processing in a power and performance efficient way.

The basic idea, that computation is best done using a huge shared compute resource rather than having dedicated hardware everywhere, doesn’t seem to be in dispute. But the air interface for a cellular network has latency requirements as well as throughput requirements. This doesn’t matter for the canonical case of a Google search where a tenth of a second seems fast. But in that time hundreds or thousands of packets might be required over the radio.


My first thoughts, like everyone else’s, is that light travels a foot in a nano-second. If the datacenter is 10 miles away then that is approximately 50,000 feet so 50 microseconds. With a high-speed network that sounds like it is starting to be significant given that it is the baseband signal processing at the PHY level of the network.

Chris Rowen of Tensilica/Cadence, during the panel session afterwards, said here’s how we can tell if it works. If the electronics at the antenna remains simple, the idea is sound. If we end up having to recreate a lot of complex electronics, starting to build a significant amount of a base-station just to get it close enough, then the idea isn’t really workable.

It seems clear that if it is workable it will be in the densest areas, since the number of antennas and their distance to the cloud datacenter mean that the whole system is operating at scale. In rural areas, there are fewer antennas and they will inevitably be further from the datacenter, and a traditional base-station self-contained for compute power is probably a better idea.


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The Biggest Private EDA Company

The Biggest Private EDA Company
by admin on 10-21-2013 at 5:02 pm

I talked this morning with fellow Brit David Halliday. More importantly, he is CEO of Silvaco, which he thinks must be the biggest private EDA company in the world. He didn’t reveal their revenue numbers but they have around 250-300 people and are profitable so you can make your own estimate.

David became CEO when Ivan Pesic, the founder, died of cancer last year. David comes from a professional software management background so is more disciplined about software development. Ivan built up a great support model that is very customer-focused which is being retained.

The company has a very broad product line. Roughly half is TCAD, where they are the top player, and half is “regular” EDA. Ivan liked to have a lot of projects and although Silvaco is big and so has a measure of scale, it is not the size of a Cadence. David wants to focus on the things that Silvaco is especially good at, and de-emphasize areas that are unlikely to become leadership positions. By de-emphasize David does not mean dropping the products: they will continue to support customers but just not target them for future investment.

In particular, they plan to de-emphasize digital CMOS, keeping what they have but not broadening the portfolio. For example, there were plans, now on-hold, to internally develop synthesis but that doesn’t make sense to David (nor to me, for that matter).

On the other hand, they will invest more in analog/mixed-signal and RF, building strong partnerships with the good foundries that also focus on this area such as Tower/Jazz and GF Singapore. Meanwhile for mainline SoC foundry they have SmartSpice which is in the process of being certified at TSMC 16nm.

Silvaco is the top player in TCAD with many solutions for novel areas such as power devices including SiC and GaN, TFT including amorphous and oxide based, solar cells including silicon nanowire, CMOS image sensors. They are also working on nanometer scale FinFET including 14nm with Sematech.

David feels that at the bleeding edge process nodes the fact that they can tie some of their TCAD technology into their EDA technology gives them an edge that nobody else has. As geometry sizes get smaller this only becomes more and more of an advantage. One area of special focus is MEMS which historically has not done much simulation.

David feels this is a 2+ year transition. Focus on what Silvaco is good at and move into adjacent areas. 4 special focus areas right now are:

  • SmartSpice
  • TCAD
  • Clever (physics based parasitic extractor)
  • Layout/schematic environment moved onto OpenAccess

Financially the company is in great shape. It has no debt. It has no investors. It is profitable. So they feel that they are the independent company, able to simply do what is best for customers.

Oh, and they plan to raise their profile. David says it is incredibly disconcerting that Silvaco has virtually zero marketing presence, and very few people realize how big Silvaco is. Partially because half their business is in TCAD which is a bit off-the-grid for people in EDA but also because David’s predecessor Ivan didn’t really believe in doing any sort of marketing.

More details on everything on Silvaco’s website here.

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Analog & Mixed-Signal Design Lunch & Learn

Analog & Mixed-Signal Design Lunch & Learn
by Daniel Nenni on 10-20-2013 at 9:00 pm

I’m a big fan of lunch and learns, mainly because I’m a big fan of lunch but I also like to learn. I’m also a big fan of Tanner EDA which is why I helped organize this event. Face to face interaction amongst the fabless semiconductor ecosystem is critical to our success so stop on by and network, lunch is on me.

Take a look at the Brief History of Tanner EDA, it really is an amazing company. Over the last 25 years they have shipped over 33,000 licenses of its software to more than 5,000 customers in 67 countries. In EDA that is an incredible milestone! I consult with Tanner during the day on strategic foundry relationships and can tell you first hand they are an absolute pleasure to work with.

Seminar: Driving Innovation in Image Sensors and High Speed Analog/Mixed-Signal Design

Moderated by SemiWiki.com founder, Daniel Nenni, this live lunch and learn session will feature presentations by Eric Kurth – Design Manager – FLIR Systems and Dr. Lanny Lewyn – Principal, Lewyn Consulting. These Tanner EDA customers will share their industry experience and expertise while discussing how they’ve solved some of today’s toughest challenges in thermal imaging and high speed A/MS design. FLIR Systems is a world leader in the design, manufacture and marketing of thermal imaging infrared cameras. Their products serve industrial, commercial and government markets, internationally as well as domestically. Dr. Lewyn is a Life Senior Member IEEE, noted author and frequent invited speaker on topics related to nanoscale analog circuit design.

REGISTER HERE

[TABLE] cellspacing=”3″
|-
| Time
| Title
| Presenter
|-
| 11:00
| Registration – Tool Demonstrations available
|
|-
| 12:00
| Lunch served;
Tanner EDA Welcome / Introductions & Overview
| John Zuk, Vice President WW Marketing &
Business Strategy, Tanner EDA
|-
| 12:15
| Uncovering Secrets in Deep Space: High Speed
Analog for Astrophysics Exploration
| Dr. Lanny Lewyn, Life Senior Member IEEE
and Principal, Lewyn Consulting.
|-
| 12:45
| Seeing in the Dark: Innovative Infrared Product
Design enabled by a robust EDA tool flow
| Eric Kurth – Design Manager – FLIR Systems
|-
| 1:15
| Closing comments & Prize Drawing
| Dan Nenni, SemiWiki
|-

Tanner EDA technical staff will be on-hand to provide hands-on demos of the complete Tanner EDA mixed-signal and MEMS tool flow. Participants can view demos during the registration period (11:00am-Noon) and immediately following the customer presentations.

Thursday, October 24[SUP]th[/SUP]
Techmart, Network Meeting Center
5201 Great America Pkwy #122
Santa Clara, CA 95054
Phone (408) 562-6111


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Server Shift to ARM Becomes a Stampede

Server Shift to ARM Becomes a Stampede
by Paul McLellan on 10-19-2013 at 3:00 pm

I have been at the Linley Microprocessor Conference today. This is the one that is not about mobile: about servers, networking, base-stations. Probably the most important story about the whole industry is that the “shift to ARM becomes a stampede.”


In this market it seems to be driven by the 64-bit ARMv8 instruction set architecture. Since servers and networking had already gone to 64-bit, they didn’t want to go back to 32 bit and so couldn’t switch to ARM until recently.

Most embedded vendors have announced ARM plans:

  • AppliedMicro (powerPC) is sampling X-gene
  • Cavium developing ARM-based Thunder to complement their MIPS-based Octeon
  • Freescale (powerPC) announced an ARM-based communication at the conference
  • LSI (powerPC) is sampling an ARM-based version of Axxia
  • AMD (x86) developing Hierofalcon for embedded market
  • Broadcom announced a new CPU architecture based on ARMv8

Linley’s view is that he doesn’t think the dual architecture (ARM + another) will endure since it is too expensive to validate CPU and software for two ISAs. I’m not so sure since the cost of doing this seems to be decreasing. For example, David Hass of Broadcom said that their software stack is generally portable across instruction sets (MIPS, ARM and x86, all of which they use). There is a standard programming model, toolchain, APIs, networking specific libraries and so on. It allows network applications to run on any architecture.

Also, having two ISAs gives them a lot of negotiating flexibility and keeps everyone, including ARM, technically on their toes so that if any vendor falls behind it isn’t a big problem. MIPS-based systems had this problem a couple of years (ok, more like 10) ago when MIPS wasn’t able to invest enough to produce actual cores and the whole future of the company was uncertain. If people already had a dual-ISA strategy it would have been easier to migrate away.

It takes years for these architectural changes to work through the entire supply chain. PowerPC still dominates the architecture share today, witha share of close to 50%. x86 and MIPS are around a quarter each with ARM a trivial sliver. But, as Linley pointed out, this pie charge will look very different in a few years time.

Many IP vendors are also targeting the communications market:

  • ARM is becoming the standard for software development
  • MIPS competes for high-end networking (new announcement earlier in the week)
  • Xtensa (Tensilica/Cadence) offers instruction-set customization (and a new announcement at the conference)
  • Andes has small low-power CPUs for embedded applications (and a new announcement at the conference)
  • CEVA is the leading vendor of DSP cores (and a new announcement at the conference)
  • ASOCS optimizes its DSP cores for wireless base stations (and a new announcement at the conference)

And it is not just CPUs. SoC interconnect can be a bottleneck. A high-bandwidth network on chip (NoC) is required:

  • ARM now complements its CPU with CoreLink (and new announcements at the conference)
  • Netspeed uses directory-based coherence
  • Arterisoffer NoC interconnect, as does Sonics


GSA Memory+ Conference in Taiwan

GSA Memory+ Conference in Taiwan
by Paul McLellan on 10-18-2013 at 3:02 pm

The GSA Memory+ conference Taiwan will take place on (Halloween!) October 31, 2013 at the Regent Taipei, Taiwan. The main theme of this year is highlighting Memory—the Critical Enabler for Prominent and Emerging Applications in System Logic Solutions.

GSA Memory+ Conference is the global industry event dedicated to all memory companies, system houses, and semiconductor companies. In its fourth year, the conference will feature senior executives from leading companies in the memory, logic and system houses to share their perspectives and insights regarding future memory applications, viable business models and collaborative opportunities among Logic devices and memory technologies & solutions. The main theme(s) of GSA Memory+ Conference this year include:

  • Emerging memory technologies
  • 3D IC design and test

This event brings over 250 professionals together from memory, fabless, foundry and IDM; key suppliers including OSAT, IP, and EDA service providers; as well as OEM, ODM and system houses. It is organized by GSA in conjunction with the Taiwan Semiconductor Industry Association (TSIA) and the Smart electronics Industry Promotion Office (SIPO).

The opening keynote is by Shozo Saito, Senior Adviser, Principal Office, Toshiba Corporation on Memory Technology Challenges for the Next Innovation

Then Dr. Ronald Black, President & Chief Executive Officer, Rambus on Driving the Need for Innovative Memory Solutions

There is a keynote about memory of a different sort at lunch by Dr. Erik Chang, Associate Professor, Institute of Cognitive Neuroscience, National Central University on Brain and Memory: The Biological Foundation of Mental Time Travel

The final keynote just after lunch is by Dr. Tae-Sung Jung, Executive Vice President (CTO) of Device Solution, Samsung Electronics Co onNew Waves of Memory Technology in Mobile & Cloud Revolution

There are also featured presentations from:

  • Dr Michael Wang of Macronix (title tbd)
  • Barry Hoberman of Spin Transfer Technologies on Why Spin-Transfer-Based MRAM Will Soon Make Major Market Impact.

The day wraps up with three presentations on 3D ICs:

  • Jerry Tzou of TSMC on 3DIC enablement
  • Dr. Vassilios Gerousis of Cadence on 3DIC Design Technology: Where Are We?
  • C.H. Wu of Advantest on Stacked Memory Test Challenges

The detailed agenda is here. Registration information is here.


New at DAC: IP, Automotive, Security

New at DAC: IP, Automotive, Security
by Paul McLellan on 10-18-2013 at 12:09 pm

The deadline for panel sessions, workshops, tutorials and co-located conferences for DAC 2014 is October 21st. That’s next Monday!

DAC 2014 will not only focus on EDA and embedded systems and software but
also include:

  • design methods for automotive systems and software
  • hardware and embedded systems security
  • IP (semiconductor intellectual property)

Automotive Track
Starting in 2014, the 51st Design Automation Conference (DAC) will feature an automotive track to bring together researchers and practitioners from the automotive domain with their counterparts from the embedded systems and software (ESS) domains and the electronic design automation (EDA) space.

Modern cars have complex distributed architectures with hundreds of processors, heterogeneous communication systems and several million lines of software. Designing such hardware and software systems involves myriad challenges spanning safety, reliability, security, verification, and certification issues.

This new automotive track will cover the horizontal themes above in automotive embedded systems to address the emerging vertical areas, such as autonomous and advanced driver assistance systems, electric and hybrid vehicles, and electro-mobility. The track will showcase design methods for automotive systems and software, highlight current challenges and emerging solutions, and explore the road ahead.

Partnership with the ESS and EDA communities at DAC will drive synergy among the automotive systems, ESS and EDA communities. Furthermore, it will provide the automotive community the opportunity to capitalize on existing tools and methodologies and also to play an active role in defining solutions for future challenges.

Deadline for submissions: November 22, 2013
Notification of acceptance: February 18, 2014

Hardware and Embedded System Security Track
Integrated Circuit (IC) and embedded system design is globalized. Consequently, designers and users of ICs, Intellectual Property (IP) and embedded systems are beginning to re-assess their trust in these systems.

These systems are vulnerable to a variety of hardware-centric attacks: side channel analysis, reverse engineering, IP piracy, hardware trojans and counterfeiting. An attacker, anywhere in this globally distributed design flow, can reverse engineer the functionality of an IC/IP, steal and claim ownership of the IP and introduce counterfeits into the supply chain.

An untrusted fab may overbuild ICs and sell them illegally. Rogue elements in a fab may insert hardware trojans into the design without the knowledge of the designer or the end-user of the IC. The semiconductor industry routinely loses over $4 billion annually due to these attacks.

The Security Track at DAC highlights the emergence of security and trust as an important dimension of Hardware and Embedded Systems Design (side-by-side power, performance, and reliability).

Deadline for submissions: November 22, 2013
Notification of acceptance: February 18, 2014

IP at DAC
DAC will serve the IP industry (developers and users alike) by focusing on the following important topical areas in the design and integration of IP components:

  • Design, modeling and implementation of IP components and their representation to ensure smooth integration into SoC’s.
  • Creation of an environment where IP developers can capitalize on DAC’s attendance to enhance the existing synergistic ecosystem involving IP companies, SoC developers, foundries and EDA companies to satisfy their current and future business and engineering needs.
  • Executive presentations, keynote addresses and meetings involving leaders from the IP industry
  • Exhibit space
  • Enable IP companies to showcase their products and capabilities to support the current market opportunities and potential expanded market opportunities
  • Demonstrate EDA tools and flows that support IP development and application

DAC itself is June 1st-5th 2014 at the Moscone Center in San Francisco. Registration will open March 27th. And watch semiwiki in May for information on where to eat and drink and what to see in this great city.

And if you are the kind of person who likes to get these things in your calendar as soon as possible (like me) then June 8-12th 2015 DAC will also be in Moscone San Francisco.

More information on the DAC website here.


CEVA-XC Wireless Baseband Core

CEVA-XC Wireless Baseband Core
by Paul McLellan on 10-17-2013 at 5:51 pm

Eyal Bergman of CEVA announced their latest core yesterday at the Linley Microprocessor Conference. It’s their 4th generation CEVA-XC solution, which is the core of their offering for wireless baseband. It builds on 3 previous generations of CEVA-XC’s that were mainly targeted toward handset applications. This one is optimized for the needs of wireless infrastructure, particularly as the shift toward LTE and LTE-A happens. It has already been licensed to one tier-1 vendor.


The new core, the XC-4500 has ultra-high processing capabilities. It runs at 1.3GHz in 28nm. It has a floating point ISA offering over 40 GFLOP. It has dynamic scheduling based on DSP clusters. There is a fully featured data cache which is non-blocking with write-back and write-through.

Since pretty much every chip using a processor core from CEVA also contains an ARM processor, and because a multi-core DSP has to live in the cache coherent world, they have full hardware support for cache-coherency based on ARM’s AMBA-4 ACE technology. This is much better than software coherency (that tends to be very pessimistic flushing whole caches and is hard to program too) and makes partitioning and programming much simpler. Another trick is that the memory can be partitioned into shared and dedicated areas with cache coherency snooping only applied to shared areas, which results in an increase in performance and a decrease in power.

There is also system interconnect with automated traffic management which combines the AMBA AXI4 with proprietary FIC (Fast IC). The automated traffic management allows a single core to work with multiple queues, or resource sharing among multiple cores via a shared queue.

Of course nobody cares about performance without knowing how much power they need to pay for it. Firstly, it can optimize the hardware-software partitioning through having vector DSP and hardware extensions. This can get the power as low as 100mW for 2×2 LTE picocell baseband processing.


It really is an all-in-one infrastructure platform usable for digital front end in the remote radio head, in the basestation itself for multi-mode baseband processing, and then for wireless backhaul.

There is support for external co-processors for specialized functions:

  • Maximum Likelihood MIMO detectors
  • 3G De-spreader units
  • DFT / FFT
  • Viterbi decode
  • LLR processing and HARQ combine
  • and more, including user supplied co-processors


So the architecture is fully scalable all the way from small cells up to macro cells and Cloud-RAN.

More details are on CEVA’s website here.


TSMC Continues To Fire On All Cylinders

TSMC Continues To Fire On All Cylinders
by Ashraf Eassa on 10-17-2013 at 5:03 pm

Taiwan Semiconductor Manufacturing Corporation is the world’s leading semiconductor foundry by revenue and, by extension, profitability. While I am deeply saddened that current CEO Morris Chang will be retiring (again) shortly, I am hopeful that his successor will be able to continue the legacy of foundry industry leadership that the company has shown over the last few years. With that in mind, I’d like dig into the most recent quarterly report and the accompanying earnings call to try to construct a better picture of what TSMC’s near and long-term future looks like.

There’s No Stopping This Freight Train

TSMC reported a great quarter. Sales were up 14.9% on a year-over-year comparison (remember, year-over-year comparisons are the important ones to make in order to strip away the effects of seasonality), gross margins were 48.5% (just about what one would expect) and operating margin was 36.7% with net profit margin at 32%. Even with dramatically increased R&D and capital expenditures, TSMC continues to manage its expenses commensurate with its revenue growth.

Now, while TSMC’s management has been excellent in doing what it needs to in order to win in this space (outperforming the broader semiconductor industry), it’s also important to note that the company is very levered to the high growth, high-stakes areas of the semiconductor industry. In particular, TSMC has been a prime beneficiary of the mobile computing industry as a good chunk of the chips that go into phones get built at TSMC. Like ARM, TSMC is protected from the booms and busts of particular end customers and is instead levered to the industry as a whole.

The one and only sore-spot of this call was guidance for a sequential decline in Q4 and comments that the high end smartphone and tablet businesses are seeing slowing growth. This was inevitable (nothing grows to the sky), but still unfortunate. On the plus side, if Apple moves most/all of its chip production to TSMC for its next generation “A” series processor, then that will drive a fairly dramatic increase in revenues, even if the broader market slows.

That being said, TSMC isn’t quite as “safe” as ARM in terms of being levered to the broader industry. If you’re a company like Qualcomm, NVIDIA, or Broadcom, you don’t really have a choice for your instruction set architecture – it’s ARM or bust. While ARM and TSMC do face some threat from Intel (which designs and builds its own chips), that’s really it for competitive pressures for ARM. TSMC on the other hand has to deal with potential competition from Global Foundries and Samsung as foundries (and, to a verylimited extent, Intel). Further, TSMC has to deal with rather extensive capital expenditures that ARM – a vendor of IP – doesn’t have to deal with.

On the other hand, leadership in wafer fabrication pays handsomely. While ARM’s moat is “safe”, TSMC’s raw profitability is in the big leagues – during this quarter alone, the company raked in a cool $1.77B, which is more than ARM takes in as revenue in a year. Of course, for the privilege of these bigger profits (and by extension a bigger company) the risk profile is higher. Everything in business is a trade-off: there are no free lunches.

Can TSMC maintain its leadership?

At 28nm, TSMC was first out of the gate and ended up getting the majority of the business as a result. The question is, will this continue out in time? That’s the multi-billion dollar question. At the 20 nanometer generation, TSMC’s management sees “very little competition” and as a result is likely to own this generation. The question becomes trickier at the 14nm/16nm FinFET nodes.

What the entire foundry industry (both the IBM “fab club” members as well as TSMC) is doing here is taking the 20nm Back End of Line (that is, the portion of IC fabrication where the individual devices such as transistors, resistors, and such) and marrying that to next generation FinFET transistors. What this buys the industry is much higher performance at much lower leakage current levels. In short, this will enable faster chips at the same power or lower power chips at the same performance – the beauty of transistor advances.

Unfortunately, this doesn’t buy anybody any material increases in logic density (SRAM densities will improve). The bad news is that cost/transistor goes up, but the good news is that everyonein the foundry business has to deal with it (except Intel, but I’ll qualify that shortly). I believe that Dr. Chang explained it best on the earnings call,

It is a matter of competition or? We just want to be our cost to be lower than competitors. I mean, this — I come back to the story of 2 people in the camp and a bear, a big bear is approaching. And the first person quickly puts on his running shoes, and the second person says, “What’s the use? The bear is going to out run you anyway; it’s going to run faster than you anyway.” And the first person then starts to run and while he departs, he said to the second person, “All I have to do is to run faster than you, not the bear.” So on this price and costing, all we have to do is to run faster than the competitor.

So, will TSMC outrun Global Foundries and Samsung at the FinFET nodes? My personal expectation is that the answer to this question is “yes” based on prior track records but only time will tell. If it can, then I see no reason for TSMC to not continue to rake in the cash and to keep the lion’s share of the leading edge capacity. But if it can’t then things get more challenging. That being said, there’s another player worth discussing: Intel.

What about Intel?

There’s no denying that as far as transistors go, Intel is usually a generation or two ahead of the foundry players. Today Intel is shipping products built on its 22nm FinFET process and is gearing up to go into production of its first 14 nanometer products in 1Q 2014 – right about when TSMC goes into volume production of its 20 nanometer process. So, on the surface this looks pretty bad – TSMC won’t have FinFETs married to its 20nm BEOL until 1H 2015, while Intel already has a 14nm process in early 2014. But there’s a subtle question that has yet to be answered.

Typically speaking, Intel is much less aggressive about its M1 layer pitch (that is, the minimum metal pitch, which usually determines logic density) than TSMC is at comparably named nodes. For example, at 28nm, TSMC’s M1 pitch was 96nm (actually denser than Samsung’s/Global Foundries’ 114nm pitch, if the Chipworks teardown of the Apple A7 is to be believed) and at 20nm TSMC’s M1 pitch is 64nm. At Intel’s 22nm, M1 pitch is 80nm, but the M1 pitch at 14nm is unknown (since Intel has not yet detailed its process).

If Intel shrinks its M1 pitch from 80nm -> 64nm at its 14nm generation, then the claims that Intel has a density advantage at its 14nm node will be incorrect. However, Intel does claim a 2x density improvement from its 22nm node to its 14nm node. If these claims are accurate, then M1 pitch for Intel’s 14nm process shouldwork out to 56nm (sqrt(2) * 80nm). In this case, Intel would have a logic density advantage of about 30%, all else being equal. But if Intel moves to a 64nm M1 pitch, then Intel’s 14nm process and TSMC’s 16nm process should be roughly equivalent. But let’s take this a step further: what if Intel’s M1 pitch at 14nm is, indeed, tighter than TSMC’s?

The risk isn’t exactly from a foundry perspective. I’m not convinced that Intel wants to play in the general purpose foundry business, particularly as much of TSMC’s leading edge capacity is driven by Intel’s direct competitors. I also am not convinced that Intel is really ready to take meaningful amounts of foundry business from the more established foundry players. After all, there’s a lot of ecosystem work that needs to be done in order to enable this. While I do see Intel taking some steps here, it will be years before we can really view Intel as a competitor.

But the risk isthat Intel’s own products end up superior to those from TSMC’s customers playing in the same space. Now, there’s more to what makes a product better/worse than what transistor technology it was built on (designs matter, too), but transistors are fundamental.

What’s the bottom line?

The bottom line is that TSMC is a very high quality company that has done everything right and will likely consistently outperform the broader semiconductor industry for years to come. It has ramped up its R&D to be very competitive on the actual process development. While the other foundry players will try to play catch-up, TSMC’s revenue and profitability advantages against its peers is staggering, which positively feeds back into TSMC’s R&D and drives continued leadership. While there’s risk that Samsung and Global Foundries “catch up” at the next generation nodes, I’ll have to see it to believe it, and even then being there with technology doesn’t mean that all of TSMC’s ecosystem and design enablement work is worth nothing – it’s still a competitive advantage that can (and likely will) be capitalized on.

TSMC’s shares rose about 2% in trading following the release of its earnings report, and while I don’t have a crystal ball, I do expect TSMC to continue to out-perform the semiconductor industry as a whole and expect the shares to trade much higher over the coming years.

More articles by Ashraf Eassa…

Also Read: TSMC CEO Succession Plan


Putting the Ten in Tensilica

Putting the Ten in Tensilica
by Paul McLellan on 10-17-2013 at 3:55 pm

Chris Rowen of Cadence’s Tensilica announced the tenth generation of the Xtensa customizable processor at the Linley Microprocessor Conference yesterday. Chris was one of the founders of Tensilica…back in 1997. I believe that the first version was released in 1999. Over the years the Tensilica business changed. Originally they sold the Xtensa system to customers to build their own customized processors, and a few customers still do that today. But most customers had a problem to solve and many had the same problems. So Tensilica used the Xtensa system to build processor environments specifically for those problems: HiFi Audio, LTE modems, video processing and so on, with software stacks, codecs and anything else needed. But still retaining the capability to customize the processor further. Delivering more value tends to be a good business strategy and with a couple of billion cores out there and an acquisition by Cadence at a healthy multiple, it turned out to be.

Now they are onto the tenth generation. The problems have changed a lot over time. Well, mainly the performance requirements have only gotten higher and higher but the power budgets have…not. Tensilica’s processors are often used to offload the control processor in various applications, or to create systems with performance that cannot be approached with a general purpose processor. Terabit data rates for example. Usually the big motivation is power: offload the application processor in a smartphone to play mp3 at much lower power, or design an LTE modem without requiring a power hungry multicore general purpose processor. Back in 1997 we didn’t worry much about power.

Another thing we didn’t worry so much about back then was programmability for its own sake. We had a specification, we wrote RTL and we taped out the chip. But now designs have to be more flexible since often the chip design has to be frozen before the specification is finalized. Being first to market often means starting the design earliest. In many environments new standards or tweaks to the standard show up. The only way to make that sort of late change is for it to be in software. But a general purpose processor is much too power hungry and, often, too low performance to do the job. The sweet spot is a processor that is optimized for the job in hand but is still programmable to take account of late changes and new standards.


So what is new? I am not going to attempt to list everything or this blog would be unreadably long. There is obviously a lot of focus on power. There is a lot of dynamic clock gating. This is similar to the sequential clock gating that tools from several EDA vendors provide, except that the Xtensa system knows much better which values will be used, and in many cases this cannot be deduced from static analysis of the RTL since it is concealed in the software. A lot of unnecessary memory access can be avoided this way.


Talking of memory, there are a lot of memory subsystem improvements to improve bandwidth and to increase parallelism. This allows for a wider range of programming models.

There is a small (up to 256 bytes) L0 cache. It would seem that would be almost useless. Funnily enough one of the first computers I ever programmed was the Cambridge University Titan system. They added a 32 word cache (so about the same size) indexed off the lowest 5 bits of the PC. Again, it seems like it wouldn’t make much difference. But it can make a big difference since it ensures that any loop of less than 32 instructions runs out of cache. And algorithms often have a lot of small tight inner loops with just a few instructions. For example, mp3 decode spends 40% of its time in this sort of loop.

In summary:

  • Less core and system power
  • More data throughput
  • Lower latency
  • More flexible memory hierarchy for more flexible programming models
  • Maximum visibility and control for rapid system development and optimization