RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)
Semiconductor Expert Forum

Posted on

Enabling Technologies that Will Shape the next Wearables

Enabling Technologies that Will Shape the next Wearables
by Daniel Nenni on 06-21-2014 at 10:00 am
Categories: EDA, Events

One of the benefits of spending the last 30 years working in Silicon Valley and publishing a fabless semiconductor book is that I get invitations to speak at events I would normally be attending. Being on the other side of the podium is truly a unique experience and one worth pursuing, absolutely. This month I spoke at #51DAC about the book and last week I presented my thoughts on the competitive landscape to a private gathering of 100+ semiconductor professionals. We are entering exciting semiconductor times with immense opportunities for entrepreneurs which I would liken to the fabless gold rush of the 1990s. During that time, TSMC brought us the pure-play fabless semiconductor ecosystem that enabled hundreds of fabless companies that are now worth billions of dollars.

One of my favorite fabless success stories, which is in the book, is Chips and Technologies. At one point in time C&T had more silicon on the PC motherboards than Intel and you have to ask yourself why? Because the fabless business model enables innovation that is not available from the IDMs, simple as that. This cycle will repeat itself now that the industry is in consolidation mode which is freeing up fabless semiconductor entrepreneurs en masse.

Next month I will be speaking at the CASPA 2014 Summer Symposium. Take a look at the keynote and panel speakers below. This is an excellent opportunity to network and investigate what is next for the semiconductor industry. Calling all semiconductor entrepreneurs! I hope to see you there:

“Enabling Technologies that Will Shape the next Wearable Applications”穿戴式应用的未来的支撑技术

Create Mainstream Market Opportunities For A Broad Range of Industries 为不同行业创造主流市场的机会

Abstract:
“Now that wearables are all the craze, how to make sense of all the hype? Wearable startups are popping up everywhere with many innovative ways to address people’s lifestyles and routines in an attempt to augment our lives.

The challenge is to find that spark that will make wearables more appealing, relevant and useful to the population. Lessons learned from the first wave of wearables…Addressing the continued challenges of unobtrusiveness, simplicity of use and power management. And how to gain wider adoption outside of the Bay Area / Silicon Valley, where Google Glass and other wearable gadgets are the norm? More and more wearable applications and proof-of-concepts are beginning to emerge, but not yet widely ubiquitous around the world. What will it take to take wearables to the next level? Wearable technologies should solve problems and enhance our lives rather than hinder it.

Today’s distinguished speakers and panelists of visionaries and technologists will talk about the first generation of wearable devices, share their personal experiences and challenges they have faced, as well as give us a glimpse into what the next generation of wearables will look like.”

Date:July 12[SUP]th[/SUP], 2014 Saturday
Time: 12:00-5:30pm
Location: Intel SC12 Auditorium
3600 Juliette Ln. Santa Clara, CA 95054

Registration:Here

Speaker Roundtable: Here

Agenda:
12 pm – 1 pm Registration & Networking
1 pm – 3 pm Welcome & Keynotes
3:10 pm – 4:45 pm Panel Addresses and Discussion
4:45 pm – 5:30 pm Speaker Roundtable: CASPA Members Only (online registration w/ $5)

Keynotespeakers:

Moderator: Daniel Nenni, SemiWiki

  • Jack Young, QUALCOMM Life Fund, QUALCOMM Ventures (Wearables expert)
  • Kambiz Hooshand, Archimedes Ventures (IoT expert)
  • Hing Wong, Walden international (China start-ups expert)

Panel speakers:

  • Greg McNeil, Innovation Labs Flextronics (Wearables)
  • Kelvin Low, Senior Director Foundry Marketing SSI
  • Sam Massih, Director, Wearable Sensors
  • Jeff Tsai, Ceo Wellex (Wearables)

Founded in 1991, CASPA has developed into the largest Chinese American semiconductor professional organization worldwide. Currently CASPA has more than four thousand individual members covering multiple disciplines. Most of them are semiconductor professionals working in Silicon Valley, Southern California, Oregon, Washington, Arizona, Texas, New York, China, Taiwan, and Singapore. CASPA also has more than 70 corporate sponsors, including EDA, design, IDM, foundry, packaging / test, venture capital, science and technology development parks, legal and financial service companies located in the United States, Taiwan, Hong Kong, China, Singapore and Japan.

More Articles by Daniel Nenni…..

lang: en_US

Posted on

Noise-Coupled Analysis for Automotive ICs at DAC

Noise-Coupled Analysis for Automotive ICs at DAC
by Daniel Payne on 06-20-2014 at 2:00 pm
Categories: Ansys, Inc., EDA

My favorite method to learn about EDA tools at DAC is by listening to actual IC designers, so on June 3rd I heard Jacob Bakker from NXP talk about his experience with noise coupled analysis for advanced mixed-signal automotive ICs.


Continue reading “Noise-Coupled Analysis for Automotive ICs at DAC”

Posted on

Intel & Ansys Enable 14nm Chip Production

Intel & Ansys Enable 14nm Chip Production
by Pawan Fangaria on 06-20-2014 at 10:00 am
Categories: Ansys, Inc., EDA, Foundries, Intel Foundry

In the semiconductor industry, it feels great to hear about the process technology shrinking to lower nodes along with innovative transistor structures that offer major gains in PPA (Power, Performance and Area). However, it requires huge investment of capital, time and effort from foundries to conceptualize, prototype and prove such technology for production. In order to design large chips based on such technology, robust design automation tools are required that must confirm to the complex foundry rules and constraints imposed by such technology and also fulfil the challenging requirements of PPA and reliability for the chip. The key is to produce chips with high yield and reliability that lasts for long duration.

I think most of us know about Intel’s new fabrication technology for 3D transistors, popularly known as Tri-gate transistors which can have multiple source-drain channels and a vertical gate overlapping each channels from three sides, thus reducing leakage and power consumption significantly and increasing speed with quick switching of transistors. Since this technology is proven, we now have started hearing about reference flows for semiconductor designs involving various EDA tools qualified with this technology. I am particularly impressed with Ansysand Intelannouncementthis month about their production proven reference flow for ‘Power, EM and Reliability Sign-off’ of designs based on Intel’s 14nm Tri-gate process.

The reason I liked it is because very recently I blogged about Ansys’s RedHawk 2014 platform which addresses critical challenges of high density, high performance FinFET based designs to produce new generation of complex SoCs with high degree of reliability including power, noise, EM and ESD effects. Although FinFET and Tri-gate transistors have similar structure, it is important that Intel has qualified through its custom foundry the complete design flow based on its Tri-gate technology by involving multiple tools of Ansys and made it commercially available as reference flow for its custom foundry customers in the mobile and cloud market segments which typically need very low power consumption, high speed of operation and lower area. I’m sure this design flow and technology will prove beneficial for other market segments as well because most of the semiconductor designs are becoming PPA critical day-by-day.

This reference flow involves RedHawk[SUP]TM[/SUP]for SoC power and EM sign-off, Totem[SUP]TM[/SUP]for custom IP power and EM integrity, and PathFinder[SUP]TM[/SUP] for full-chip ESD validation, thus completing top to bottom flow for power, noise, EM and ESD reliability sign-off.

RedHawk provides chip, package and system level analysis and sign-off for dynamic power integrity, noise and reliability of low power, high performance SoCs. It checks for simultaneous switching noise, decoupling capacitance, package inductance, power and signal wire electromigration, ESD protection, RTL-to-GDS power closure and so on and signs off the design for power, noise and reliability with silicon correlated level of accuracy.

Totem is an ideal tool for IP sign-off with full-chip layout based power and noise analysis for mixed-signal designs. It can very effectively be used for early stage prototyping, designing of package and power network and signing off the chip with accuracy.


PathFinder provides ESD (Electro-static Discharge) integrity (with HBM and MM checks) to address much needed reliability of designs at such lower nodes. It can exhaustively analyze the whole design to identify potential weaknesses which may expose the chip to ESD related failure. It can be used from early prototyping to final sign-off stages of the chip to improve yield and eliminate conditions that can lead to any ESD event.

The confidence of this flow at 14nm Tri-gate process is much higher as it is production-proven and is an extension from the previous collaborative work of Intel and Ansys on 22nm technology. My feeling is that in coming days, this flow will prove very effective in bringing the main stream production on 14nm Tri-gate technology involving Ansys’s design and analysis tools for power, noise and reliability.

More Articles by Pawan Fangaria…..

lang: en_US

Posted on

On the Road from Makers to Consumers

On the Road from Makers to Consumers
by Don Dingee on 06-20-2014 at 12:00 am
Categories: Foundries

It’s time to break with conventional thinking. For decades, the measure of success for semiconductors has been OEM design wins. Most consumers haven’t known, or cared, about what is inside their electronic gadgets, as long as they work. That may be about to change, because a new intermediary is finding its voice – and being heard in high places. Continue reading “On the Road from Makers to Consumers”

Posted on

Workshop: Embedded Applications and Kernels

Workshop: Embedded Applications and Kernels
by Daniel Payne on 06-19-2014 at 6:13 pm
Categories: EDA, General

Design Automation Conference Workshop on Suite of Embedded Applications and Kernels

In June, the first Suite of Embedded Applications and Kernels, or SEAK, workshop at the 2014 Design Automation Conference in San Francisco introduced a new Defense Advanced Research Projects Agency program in the area of embedded system benchmarking for U.S. Department of Defense-related applications. SEAK aims to define a new, open suite of benchmarking with a novel methodology in terms of performance and power to evaluate end-to-end embedded systems for DoD’s application areas.

Continue reading “Workshop: Embedded Applications and Kernels”

Posted on

A Brief History of QuickLogic

A Brief History of QuickLogic
by Paul McLellan on 06-19-2014 at 10:18 am
Categories: FPGA, QuickLogic

Quicklogic was founded in 1988 as a fables semiconductor company supplying anti-fuse devices. In fact VLSI Technology, where I was working at the time, was their foundry.

Although today anti-fuse is often used as a generic word for one-time-programmability, the origins of the name are grounded in reality. In a fuse, like the things we used to use before we had circuit breakers in our houses, if the current gets to high, the fuse-wire melts and thus breaks the circuit and so protects the wiring from damage or starting a fire. Anti-fuse works the other way around. A non-conducting bit of the circuit becomes permanently conducting if a high current is passed through it, so rather than breaking the circuit, it makes the circuit. Quicklogic called their implementation ViaLink technology since it basically made a non-conducting via become conducting.

In 1991 they introduced what were then the industries highest performance, lowest power FPGAs based on this technology. A couple of years later they introduced open tool synthesis to make programming the devices more straightforward. In 1997 they introduced their first devices combining hardwired logic with programmable logic fabric.

In 1999 Quicklogic went public on Nasdaq.

In 2001 they introduced their first devices combining processors with programmable logic. In 2007 they tweaked their business model and introduced their Customer Specific Standard Product (CSSP) customer engagement model, combining both hardware and software to produce innovative products for mobile and industrial customers. This provides the flexibility of an FPGA without requiring the customer to do their own design, combined with the focus of an ASSP without the high NRE and long lead-time.

The following year they introduced the PolarPro II designed to meet the connectivity, intelligence, security and system logic requirements for mobile applications.


In 2010 they introduced ArcticLink II VX providing an innovative approach to reducing power used by the display in mobile devices, resulting in 25% batter extensions in smartphones. The technology is known as Visual Enhancement Engine (VEE). By varying the display backlight power depending on what is being displayed, power can be saved without impacting the user experience. Since then various more advanced versions of this technology have been brought to market.

The most recent product offerings have been:

  • ArcticLink 3 S1 ultra-low power sensor hub offering OEMs always-on context awareness at a cost of under 2% of battery life
  • PowerPro 3, their first one-time programmable logic-devices for mobile and industrial markets
  • The catalog CSSP product strategy

And earlier this month they announced two products, the S1 wearable sensor hub and software for recognizing tap and wrist rotation for use in watch-like wearable devices. The always-on power consumption is less than 250uW. I wrote about them in an earlier post here.

CSSPs are complete, customer-specific solutions that include a combination of silicon solution platforms, Proven System Blocks (PSBs,) customer-specific logic, software drivers and firmware. CSSPs extend battery life, provide alway-on context awareness, improve the viewability of images on mobile displays and add differentiated features to handheld mobile devices. QuickLogic supplies leading edge, low-power customizable semiconductor sub-system solutions for tablets, smartphones, broadband data cards, secure access data cards and mobile enterprise products. These solutions include storage, I/O, display, network and memory.

More about Quicklogic on their website here.


More articles by Paul McLellan…

Posted on

SpyGlass CDC: A Comprehensive solution for addressing CDC issues

SpyGlass CDC: A Comprehensive solution for addressing CDC issues
by Pawan Fangaria on 06-19-2014 at 7:30 am
Categories: EDA

About a decade ago, semiconductor designs had just a few asynchronous clocks which were easily managed by designers through the process of manual design reviews. The situation today is completely different. An SoC can have hundreds of asynchronous clocks, driving different complex functions, spread across various IPs, supplied by different vendors. It’s just not possible to analyze the interaction of all these asynchronous clocks manually, and even the traditional tools are not sufficient. Tools need special intelligence to recognize the synchronized and unsynchronized crossings between various asynchronous clocks to identify design issues. In the SoC verification arena, Clock Domain Crossing verification is at the forefront of RTL verification because a single CDC issue, if not resolved well, can result in design failure forcing an expensive design re-spin.

Knowing that Atrenta’sSpyGlass® has a comprehensive solution for CDC analysis, I fixed up an appointment with Paras Mal Jain, Director Engineering at Atrenta, to learn about their SpyGlass CDC product. Paras has been involved in the development of the SpyGlass CDC product from the very beginning when customers started demanding an automated tool for handling CDC issues. It was an interesting conversation involving intricate details about CDC in general and the SpyGlass CDC product in particular.

Q: Paras, I hear these days, CDC has become a big issue in SoC Verification. I also hear that you have a comprehensive solution for this. Tell us more about the solution.

A: Yes, CDC has become one of the most dreaded problems in SoC designs. The issue appears when signals cross asynchronous clock boundaries without being synchronized. It’s difficult to catch CDC issues precisely by using traditional tools which may either under-report real design issues and / or over-report false violations; static timing analysis and RTL simulation tools are not suitable to identify the CDC problems. We have a state-of-the-art solution with a strong structural CDC verification sign-off flow, proven across a very large number of customers. We also offer solutions for SoC level CDC analysis and functional CDC verification. Then, there is also simulation based dynamic CDC verification for certifying the SoC design to be CDC safe, i.e., CDC sign-off.

Q: What kind of structural analysis is done? More importantly, how are the identified issues resolved?

A: SpyGlass CDC provides a rich suite of rule-sets to verify all kinds of structural CDC issues. To begin with, it helps in validating the user setup to ensure that CDC verification does not result in bogus violations. Next, it identifies unsynchronized and synchronized clock domain crossings. There can be numerous unsynchronized crossings detected, but the real value of the product is in performing the protocol independent analysis to enable identification and filtering out the false negatives upfront.

For Example:

· Paths that can be between clocks of two slaves that never interact among themselves
· Crossings due to quasi-static signals and crossings between other groups of signals that don’t require synchronization
· User defined synchronizers

SpyGlass CDC provides flexibility to the user to define custom synchronizers. By eliminating the majority of false violations, SpyGlass CDC saves lots of the designers’ time and allows them to focus on real design issues.

Other structural CDC checks include convergence and reset verification. Another important aspect of CDC verification is analysis across power domains without power logic instrumentation. This helps users identify the CDC issues which would otherwise be shown after power logic instrumentation. As part of its CDC methodology, SpyGlass CDC provides guidance to users throughout the design and validation process. It also helps users identify the inputs such as the synchronous and asynchronous reset signals. Additionally, it also identifies quasi-static signals that need to be ignored during investigation and analysis for unsynchronized crossings.

Q: What is protocol independent technology?

A: SpyGlass offers low noise CDC verification using protocol independent synchronization checks. With this technology, we identify generic synchronization elements as opposed to rigid structures. We don’t need to necessarily chase around RTL specific structures which may be design style dependent. Depending on rigid RTL structures can be error-prone and it is almost impossible to detect all RTL styles; protocol independent analysis is immune to design structures and can identify FIFO, handshake, and other synchronizers that are properly designed in a generic way. It identifies critical signals for a clock domain crossing which may synchronize the crossing structurally and it also checks if it would make the crossing work functionally correct.

Our protocol independent synchronization verification is a patented technology and can exhaustively verify any CDC problems in a holistic way and provides ease of debug. This is seamlessly integrated into the SpyGlass Platform.

Q: How are the functional checks done?

A: The functional checks are done to ascertain that the circuit is working properly without any data loss, data incoherency issues, or glitches in the design. The functional checks are necessary because structural CDC analysis only makes sure that synchronizers are in place to avoid metastability, but functionality of the synchronization circuit is verified using functional verification. Assertion based verification techniques are used to perform the functional checks. The assertions are inferred automatically without requiring any user intervention and then they are verified using advanced formal engines. For example, in case synchronized signals are converging in the design, they should be gray-encoded. SpyGlass CDC automatically infers such signals and verifies them automatically, to ensure they are gray encoded using formal verification techniques. Use of a wide range of formal engines, abstraction refinement techniques, multi-core features, and support of verification languages such as OVL / SVA results in a comprehensive and productive functional verification.

We have a combined methodology for both structural and functional verification to perform early CDC sign-off.

Q: This seems quite interesting. Considering the SpyGlass RTL sign-off solution, how is the overall flow constituted? How are the issues substantiated from RTL to Gate level, because there can be a few structural changes, if not more, between the two?

A: There are primarily three types of verification – structural, functional, and dynamic, as shown in the figure below:

At the RTL, substantial structural analysis and functional analysis is performed to find all CDC issues. At the gate level, insertion of clock gating, power optimization logic, or some other net-list level changes may introduce new CDC issues. Therefore, it is mandatory to perform complete structural analysis. The functional verification is done as required depending upon the fixes done during structural analysis.

Q: What is your experience from customers with the product?

A: Our customers have been extremely positive. Most of the top 20 semiconductor companies and over 150 customers are using the SpyGlass CDC solution. It’s the market leader in the industry for identifying CDC issues at the IP level, as well as the SoC level. We have many success stories from our customers who avoided re-spins of their chips by using SpyGlass CDC.

This was a very absorbing conversation with Paras, and I could gauge the finer handling of the issues by SpyGlass CDC that provides automated and comprehensive guidance to the users.

SpyGlass CDC provides comprehensive CDC signoff including structural and functional CDC analysis, ease of debug, low noise and highest performance for very large size designs.

Atrenta has organized a free live webinar on ‘Signoff Quality CDC Solution for Billion+ Gate Designs’. Here is the schedule –

Date: Wednesday, June 25, 2014
Time: 10 AM PDT

Interested people can register to reserve the slot and know more about CDC.

More Articles by Pawan Fangaria…..

lang: en_US

Posted on

Embedded Vision Summit: the How-to and the How-to

Embedded Vision Summit: the How-to and the How-to
by John Swan on 06-19-2014 at 12:08 am
Categories: Events

When I realized I had the opportunity to attend the Embedded Vision Summit (EVS) if I would change a return flight to a day earlier, I didn’t hesitate. Thankfully I was able to change my flight without any nuisance fee from the airline, and attended EVS.
There were two “How-to’s” at this Summit:

  • The algorithmic How-to, which includes

    • Object detection
    • Object recognition
  • The design How-to, which includes

    • IP aspect
    • EDA tooling aspect

The morning Keynote presentation, “Convolutional Networks: Unleashing the Potential of Machine Learning for Robust Perception Systems” by Yann LeCun, of Facebook and New York University, was a good example of the algorithmic How-to. Object detection is difficult enough, with objects moving in several ways: translationally (across the field of view), moving closer or farther, rotationally around an axis, and changing shape – like a person reaching out their arms, or even talking. Even more difficult is object recognition.

Not a lite keynote, LeCun dug into the algorithm and experimental results. The algorithm has a brief learning process after which it is able to give good probabilities that the object matches with one for which it has gone through the learning process. LeCun demonstrated the algorithm by using an attached webcam to his PC and aiming at different scenes from the podium: His face, his shoes, the right side of the audience, the left side, etc. After aiming the webcam and pushing the Learn button he was then able to aim the camera at the various scenes and showing a probability histogram of what learned ‘object’ the scene matched with. LeCun Presented for an hour and kept the audience captivated. Just when you thought he might be wrapping up he was pushing on to something new.

Jeff Bier has the design How-to expertise, which I have been aware of since about 1997 when I was at Motorola Corporate Labs. Jeff has always been up on DSP design tooling – it fits with the traditional them of BDTi which he founded to do DSP processor benchmarking. Multimedia such as embedded vision (if you can call it multimedia) is the next higher-order of signal processing.

Jeff did 2 presentations, one entitled “What’s New in Tools for Vision Application Design and Development?” In order to extract knowledge from embedded vision we rely on the hardware: processors, sensors, etc.and the Software: algorithms, libraries, APIs – the tools to get both of them together and working. Jeff highlighted 3 main software development environments: OpenCV, OpenCL, and OpenVX, an emerging Khronos standard API providing a vision hardware acceleration (abstraction) layer. Khronos has information on OpenCL and I will leave it up to the reader to do some further research on those. Jeff also told us about development kit for support of embedded vision.

After attending this Summit I intend to attend the future Summits!

You can access the Summit presentations here if you are registered on the Embedded Vision Alliance website.

(Submitted from DAC, where there’s a lot more on the How-to)

lang: en_US

Posted on

What is Authentication and Why Should You Care?

What is Authentication and Why Should You Care?
by Bill Boldt on 06-18-2014 at 10:00 pm
Categories: Foundries

Authentication means making sure that something is real, just like it sounds.In the real world, authentication has many uses. One of the most recognizable is anti-counterfeiting, which means validating the authenticity of a removable, replaceable, or consumable client. Examples include system accessories, electronic daughter cards and spare parts. Of course, authentication is also employed to validate software and firmware modules, along with memory storage elements.

Another important and growing role for authentication is protecting firmware or media by validating that code stored in flash memory at boot time is the real item – effectively helping to prevent the loading of unauthorized modifications. Authentication also encrypts downloaded program files that can only be loaded by an intended user, or uniquely encrypt code images that are accessible on a single, specific system. Simply put, authentication of firmware and software effectively makes control of code usage a reality, which is important for IP protection, brand equity maintenance and revenue enhancement.

Storing secure data, especially keys, for use by crypto accelerators in unsecured microprocessors is a fundamental method of providing real security in a system. Checking user passwords via authentication means validation – without allowing the expected value to become known, as the process maps memorable passwords to a random number and securely exchanges password values with remote systems. Authentication facilitates the easy and secure execution of these actions.

Examples of real-world benefits are quite numerous and include preserving revenue streams from consumables, protecting intellectual property (IP), keeping data secure and restricting unauthorized access.

But how does a manufacturer ensure that the authorization process is secure and protected from attack? With hardware key storage devices such as Atmel’s ATSHA204A, ATECC108A and ATAES132 – which are all designed to secure authentication by providing a hardware-based storage location with a range of proven physical defense mechanisms, as well as secure cryptographic algorithms and processes.

The bottom line? Hardware key storage beats software key storage every time – because the key to security is literally the cryptographic key. Locking these keys in protected hardware means no one can get to them. Put another way, a system is not secure if the key is not secure – and the best way to secure a key is in hardware. It is that simple.

Bill Boldt, Sr. Marketing Manager, Crypto Products Atmel Corporation

Posted on

TSMC (TSM) is Having Another SoC Year!

TSMC (TSM) is Having Another SoC Year!
by Daniel Nenni on 06-18-2014 at 9:00 am
Categories: Foundries, TSMC

TSMC’s stock has more than doubled in the last five years. Coincidentally that is when I started blogging about TSMC. QCOM stock has experienced a similar doubling during this time as have other TSMC customers. The question is: What is next for TSMC? As I have mentioned before, you would be better off taking stock tips from your dog but this is what I see for this year and next for TSM.

Apple will become one of TSMC’s largest customers in 2014. This is simply amazing to me as I grew up with Apple as a computer hobbyist. Apple started selling mother boards before selling complete computer systems. In fact, I was at the UC Berkeley Campus when Steve Jobs entered wearing a backpack with a Macintosh computer inside ushering in a new era of personal computing. And now Apple is one of the largest fabless semiconductor companies? It boggles the mind!

The quarterly wafer ramping numbers I have read for Apple are $0 to $700M per quarter this year starting in Q2 2014 and up from there depending on the success of the iPhone6 and iPads to be announced later this year. As I have mentioned before, I predict that the iPhone6 will break revenue records and it is filled with TSMC silicon, absolutely. Given that TSMC will ship 300,000 20nm wafers in 2014, Apple will probably consume most of them. The other SoC vendors are still scrambling to get 64-bit 20nm SoCs taped-out. Apple really disrupted the SoC business with their 64-bit A7!

In 2015 Apple business could result in an additional $1B per quarter for TSM. Based on what I heard at #51DAC the TSMC/Apple relationship will continue into the FinFET era. One interesting note; I saw quite a few Apple badges at #51DAC, which was not the case at #50DAC. Those Apple engineers are becoming more plentiful and less stealthy it seems.

QCOM however is TSMC’s largest customer. QCOM consumed a record number of wafers last year, roughly a 50% YoY increase. FinFET is the big question, will they go TSMC or Samsung? I can tell you for a fact that QCOM will not use Intel Foundry, nor will any other SoC vendor that has a choice. It may have something to do with Intel flooding the market with free 22nm SoCs? Let’s see how many of those 40 million “contra revenue” parts actually make it into consumer’s hands. Ironically Intel will be using TSMC 28nm for their new Sofia SoC but I would not expect any volumes there either unless Intel goes contra revenue again.

The latest word from #51DAC is that QCOM will straddle TSMC and Samsung for FinFET wafers to get better margins. TSMC’s margins are at an all-time high (36%) and QCOM’s are at an all-time low (16%) so you do the math. A Samsung/QCOM foundry relationship seemed like a natural fit since Samsung is one of QCOM’s largest customers but with the launch of the Samsung Exynos SoC in 2010 the two companies are now frenemies. As they say, keep your friends close but your enemies closer. That is from the book “GodFather II” by the way. Michael Corleone said, “My father taught me many things here — he taught me in this room. He taught me — keep your friends close but your enemies closer.”

The other SoC vendor that I track is MediaTek. They are literally down the street from TSMC and UMC so I see them during my Taiwan travels. MediaTek is an interesting company that has done extremely well in the low end SoC business. I view MediaTek, TSMC, and UMC as brothers so I highly doubt they would use GlobalFoundries or Samsung but it is certainly possible. In this business margins are everything.