In the race to reduce verification time for ever growing sizes of SoCs, various techniques are being adopted at different levels in the design chain, functional verification being of utmost priority. In an analog-digital mixed design, which is the case with most of the SoCs, the Spice simulation of analog components is the limiting factor because it is inherently slow and cannot handle large designs. A mixed-signal simulator which integrates Spice solver with event-based (for digital) solver can be used to improve the overall speed (better than Spice) while keeping the accuracy at Spice level; however the speed is still substantially less than a pure event-driven simulator and capacity to handle large analog content is still a limitation. So, what’s the next alternative?

We do have one where analog behavioral models can be used in place of analog IPs or components and can be simulated along with digital with event-based solvers at the same speed as digital without any major capacity limitation. An analog behavioral model is the abstract representation of its analog IP or component; the behavior is captured using either RealNumber or logic data types in HDLs. Since the actual implementation of the analog IP or component is done separately through schematic and layout in the design process, it’s necessary to check the equivalence between the actual implementation and the behavioral model.

In the framework of analog behavioral model validation, verification planning is very important which brings together all stakeholders from analog, digital and verification teams, sets objectives of equivalence validation and establishes a continuous communication channel. The equivalence between behavioral model and circuit implementation must be ensured by verifying it every time any change in specification occurs which drives change in circuit implementation. The verification plan must contain all important criteria such as list of features and their tests, testplan, coverage, equivalence validation methods, review procedure, reporting, exception handling and verification closure criterion.

In the simulation environment, every test has to be simulated twice; first the Spice view of analog IP and then the behavioral model as DUV (Device Under Verification). The test scenarios are derived from the verification plan and EqVC (Equivalence Validation Component) is placed in the testbench environment to capture information that is used to compare if simulation of both types of DUVs produce similar results and decide pass/fail for each test or waive off certain failing test depending on the closure criteria mentioned in the verification plan. The comparison technique varies with the type of EqVC. The testbench can be setup either in analog-on-top (i.e. schematic driven environment) or in digital-on-top (i.e. HDL based environment) fashion.

This methodology of equivalence validation has been used and presented jointly by Mentor Graphicsand ST Microelectronicsin DVCon 2014. They used digital-on-top testbench environment and mixed-signal simulator which could handle both behavioral model as well as Spice view of analog IP without any change in testbench. To reduce simulation time, focus was on testing features relevant for functional verification; further, model with multiple functions was broken down into smaller simpler models, which aligns with the philosophy of analog circuits being modular, consisting of sub-circuits.

There are three different types of EqVCs –

For quick equivalence validation, ‘waveform compare’ method is used which can be quickly setup with a waveform tool like EZWave for comparing continuous waveforms and automating post-processing of results for reports, such as pass/fail, through scripting. This method is good for simple models such as BIAS and PLL models of HDMI IP.

Above is a snapshot of waveform mismatch between analog and behavioral model. The differences shown in red can be studied and used to fine tune tolerances and waiver criteria.

The Assertion Based Verification (ABV) is similar to the way it is used in digital circuits, that is by adding assertions in the design description to capture the design intent and verify that the intent is implemented correctly. QuestaADMS extends SVA (System Verilog Assertion) bind scope to analog objects as well. This methodology improves design quality and verification productivity by increasing observability. It’s well suited for digital-on-top verification; the testplan acts as an executable verification plan and is linked to functional checks (in the form of assertions) from simulation results. A library of commonly used checkers and monitors such as monotonicity of signal, signal crossing a threshold etc. can be reused with different models whereas specific assertions have to be written afresh based on the functional specs.

Above is an example of a testplan for a voltage regulator. The QuestaADMS allows use of scripts to link testplan and merge UCDB. The assertions from behavioral model simulation as well as Spice DUV are merged separately and then compared to ascertain failing testcases in the behavioral model.

The Advanced Verification method is based on UVM, a standard methodology promoted by Accellera, based on reusable class libraries. This method includes constrained random stimulus to increase verification coverage and supports coverage driven verification. UVM agents are extended for analog specifications to increase test scenarios and measure coverage. The basic test methodology remains identical to ABV.

Read more on coverage driven verification through UVM

ST has successfully used this validation environment for multiple of their IPs. A mix of EqVC types can be used; ‘waveform compare’ method for simple models at leaf level and ABV/UVM method for complex models and interconnected models at the top level. QuestaADMS supports RealNumber data types in Verilog-AMS, VHDL and SystemVerilog and supports the above verification methodologies for low power and mixed-signal simulations. More detailed information can be found in a whitepaper at Mentor website.

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