SOI Future or Flop?

SOI Future or Flop?
by Scotten Jones on 01-31-2014 at 8:00 am

 Silicon On Insulator (SOI) is a technology that has been in use by the semiconductor industry for a long time. Early technologies such as Silicon On Sapphire (SOS) were reported as early as the sixties. In the eighties technologies such as V groove dielectric isolation were used. In the nineties we saw wafer bonding become the most prevalent technique for SOI fabrication, although implanted oxygen was also in use. It wasn’t until the late nineties that IBM ushered in the modern era of SOI usage for high performance CMOS.

SOI has always offered certain performance advantages with radiation hardness, the ability to isolate both positive and negative voltages on the same substrate and reduced power consumption being a few key examples. Although this article is focused on state-of-the-art CMOS, SOI is also an important part of many emerging Micro Electro Mechanical System (MEMS) applications and some power IC applications as well. The issue with SOI has always been cost and it has always been a niche technology.

In the late nineties IBM introduced Partially Depleted SOI (PDSOI) for high performance CMOS. The introduction of a buried oxide layer under the MOSFET reduced parasitic source/drain (S/D) capacitance reducing power consumption. Planar MOSFETs have highly doped source and drain regions of one conductivity type separated by a lightly doped channel of opposite conductivity type. The surface of the channel is covered with an insulating layer and a gate electrode. The gate of a MOSFET really only has good control of the surface and in the sub surface regions there are S/D leakage paths. With partially depleted SOI, the device silicon layer on top of the insulator is still thick enough that the gate can’t fully deplete the channel in the off-state and leakage paths still exist. PDSOI also requires all of the processing of a standard bulk process plus a couple of SOI specific masks. This coupled with the high cost of SOI substrates yields a very expensive process. In spite of the cost issues, IBM utilized PDSOI from 130nm to 22nm for high performance processors. Concurrently IBM developed a high performance embedded DRAM technology (eDRAM) that took advantage of the buried oxide isolation in SOI making the process ideal for their high performance processors needs. In the early 2000s AMD was a development partner of IBM and they also adopted PDSOI for their processors for the 90nm through 45nm generation and at one point all three major game consoles utilized PDSOI based processors. Today IBM’s 22nm process is to the best of our knowledge the only leading edge logic process still running on PDSOI. In IBM’s case the processors are used for high margin server products and performance is far more important than cost. Other PDSOI users have concluded that any performance advantages are outweighed by the cost.

Fully Depleted MOSFETs

As MOSFET gate lengths have shrunk, S/D leakage has been increasing exponentially and a change in MOSFET architecture is now required with the 20nm node expected to be the end for the bulk – planer MOSFET. If instead of a partially depleted channel the channel of a MOSFET is full depleted in the off-state, S/D leakage is reduced by orders of magnitude. There are two main techniques currently in use for fully depleted MOSFETs, FinFETs and Fully Depleted SOI (FDSOI).

FinFETs utilize thin fins of silicon standing up perpendicular to the wafer surface in a 3D configuration for the MOSFET channel. The fin may have gates on both sides (a classic FinFET) or on both sides and the top (Trigate). With gates on both sides the fin thickness must be approximately one half the gate length to be fully depleted and with gates on both sides and the top the fin width must be less than approximately one times the gate length to be fully depleted. The Trigate configuration relaxes the fin thickness requirements making them easier to manufacture. FinFETs can also be fabricated on either bulk or SOI (more on that later). At 22nm Intel was the first in the industry to introduce FinFETs with their Trigate process. Intel announced at the time that the Trigate process adds 5% to the processing costs versus planar. One interesting observation here is that the FinFET process actually requires fewer masks and process steps than bulk. In an ideal FinFET, the channel would be undoped but in order to achieve multiple threshold voltages multiple gate work function metals would be required. Due to the difficulty of fabricating multiple work function metals, FinFETs today have doped channels and this requires masks and implants for Vt tuning, however the complexity of the Vt tuning scheme is reduced relative to bulk-planar MOSFETs due to the absence of Halos. If you just look at the processing steps for a FinFET versus a bulk-planar MOSFET the FinFET flow is simpler. I believe the added cost is due to yield issues from the fin formation on bulk process where controlling the fin height is very difficult.

The other option for fully depleted MOSFETs is planar FDSOI. In planar FDSOI the device silicon layer thickness on top of the buried oxide must be less than approximately one third the gate length. The challenges of making a sufficiently thin and uniform FDSOI device layer took many years to overcome and FDSOI has only recently become available. There is a very technologically interesting byproduct of such a thin device silicon layer over an insulator. It is possible to fabricate a buried back gate under the MOSFET channel. The back gate can be biased to tune the MOSFET performance and or threshold voltage. Modern System On a Chip (SOC) designs require three or even four threshold voltages. For a 20nm bulk-planar MOSFET technology each threshold voltage requires an NMOS and a PMOS threshold voltage mask and implant. Halo implants also strongly influence threshold voltage and each threshold voltage requires a S/D Ext/Halo mask and set of implants. S/D Ext/Halos require three to four implants each. Tailoring of deep S/D contact implants can also be required. The bottom line is a planar-bulk MOSFET can require 4 to 6 masks and 9 to 15 implants for each threshold voltage! Multiply that number by 3 or 4 threshold voltages and you can see what a huge process and cost driver threshold voltage is. Eliminating all of these masks and implants by biasing a back gate offsets the cost of the SOI starting substrate and yields a cost competitive technology with better performance. For the interested reader I have written a cost analysis comparing FDSOI to bulk at 22nm available here: http://www.icknowledge.com/news/presentations.html (in the spirit of full disclosure the work was funded by SOI producer Soitec).

FDSOI Versus FinFET
Now that we have reviewed the options for fully depleted MOSFETs let’s take a look at the relative merits of the two approaches.

I have spent a lot of time looking at performance of FinFETs versus FDSOI. I believe it is generally acknowledged that FinFETs offer the highest ultimate speed and drive current in the smallest area. FDSOI on the other hand offers lower power and the best performance per watt. This would suggest that for very high performance applications FinFETs would be the best technology. On the other hand if you are designing a SOC IC for a mobile application FDSOI would be a better choice.

There are a number of cost comparisons that have been published of FDSOI versus FinFETs on bulk showing FinFETs are significantly more expensive. Handel Jones of IBS for example has published a 20nm die cost comparison showing a 35% higher wafer cost for FinFETs versus FDSOI. When I look at the specific process steps for a bulk FinFET versus an FDSOI device I don’t see this at all. I can only assume that there are some unfavorable yield assumptions in the FinFFET portion of the analysis. I haven’t spoken to Handel Jones about this but one of my colleges asked him about this at ISS this year and my understanding is that Dr. Jones acknowledged that it was yield driven. I personally find it very hard to believe that after over two years of manufacturing experience on the process, Intel wouldn’t have over 90% wafer yield on their process by now and I therefore believe these higher cost estimates are wrong.

There have also been published analysis from IBM claiming that FinFETs on SOI are cheaper than FinFETs on bulk (although in the same presentation they also appear to acknowledge that after accounting for the more expensive SOI wafer the costs are roughly the same). Based on my own analysis and Intel’s published 5% cost difference at 22nm I believe FinFETs on bulk and FDSOI at the 22nm/20nm node have very similar cost.

I have also looked at 14nm costs for FDSOI, FinFETs on bulk and FinFETs on SOI. The following table summarizes some findings based on a detailed analysis of the processes.

[TABLE] align=”center” border=”1″
|-
| style=”width: 167px; height: 17px” |
| style=”width: 80px; height: 17px” | FDSOI
| style=”width: 90px; height: 17px” | FinFET on bulk
| style=”width: 86px; height: 17px” | FinFET on SOI
|-
| style=”width: 167px; height: 17px” | Mask layers
| style=”width: 80px; height: 17px” | 44
| style=”width: 90px; height: 17px” | 46
| style=”width: 86px; height: 17px” | 43
|-
| style=”width: 167px; height: 17px” | Multi patterning masks
| style=”width: 80px; height: 17px” | 8
| style=”width: 90px; height: 17px” | 13
| style=”width: 86px; height: 17px” | 11
|-
| style=”width: 167px; height: 17px” | Total masks
| style=”width: 80px; height: 17px” | 52
| style=”width: 90px; height: 17px” | 59
| style=”width: 86px; height: 17px” | 54
|-
| style=”width: 167px; height: 17px” | Substrate cost
| style=”width: 80px; height: 17px” | High
| style=”width: 90px; height: 17px” | Low
| style=”width: 86px; height: 17px” | High
|-

The FDSOI mask and cut mask count is based on a STMicro presentation that details the masks for their upcoming 14nm process. The Intel and IBM mask counts are based on my own analysis performed with other industry process experts I work with and include all mask layers required for the full process. In the case of IBM I have removed the eDRAM related masks to create a direct comparison. All three processes are also based on 10 metal layers and 3 threshold voltages. Looking at the mask counts and process details I don’t see a big cost advantage for any of the three processes and don’t believe cost will be the differentiating factor. If anything a straight forward process and materials analysis appears to favor FinFETs on bulk. If any SemiWiki readers believe they understand FinFET processing and disagree with these counts I would be happy to have a private conversation about it. I am also still working on a detailed cost comparison of the three processes but don’t anticipate that will change my conclusions.

What Leading Edge Logic Companies are Doing
To summarize this paper so far, FinFET appears to be the best solution where ultimate performance is the goal with power consumption being a secondary concern and FDSOI appears to be the best solution where power is the primary concern.

We will now examine what companies are actually doing at 14nm. The following table summarizes all of the companies pursuing 14nm logic with their announced process technology.

[TABLE] align=”center” border=”1″
|-
| style=”width: 201px; height: 17px” | Company
| style=”width: 201px; height: 17px” | 14nm technology
|-
| style=”width: 201px; height: 17px” | Global Foundries
| style=”width: 201px; height: 17px” | FinFET on bulk although will also make FDSOI under a manufacturing agreement with ST Micro
|-
| style=”width: 201px; height: 17px” | IBM
| style=”width: 201px; height: 17px” | FinFET on SOI
|-
| style=”width: 201px; height: 17px” | Intel
| style=”width: 201px; height: 17px” | FinFET on bulk
|-
| style=”width: 201px; height: 17px” | Samsung
| style=”width: 201px; height: 17px” | FinFET on bulk
|-
| style=”width: 201px; height: 17px” | ST Micro
| style=”width: 201px; height: 17px” | FDSOI
|-
| style=”width: 201px; height: 17px” | TSMC
| style=”width: 201px; height: 17px” | FinFET on bulk
|-
| style=”width: 201px; height: 17px” | UMC
| style=”width: 201px; height: 17px” | FinFET on bulk
|-

With many years or development and hundreds of million or even billions of dollars invested in process development I would consider the processes in this table to be pretty well locked in at this point.

Looking at this table, FinFET on bulk represents roughly 95% of the expected 14nm capacity with FinFET on SOI and FDSOI only representing about 5%.

Looking at IBM and taking into account their eDRAM on SOI technology, a FinFET on SOI strategy makes perfect sense. IBM needs the highest possible performance plus eDRAM and there is an argument that FinFET on SOI has some performance advantages over FinFET on bulk.

For Intel performance is also a big driver although in recent years they have become more focused on performance per watt than they were previously. FinFETs on bulk make a lot of sense for Intel.

Looking at the major foundries, TSMC, Global Foundries, Samsung and UMC their technology choice is not as easy to understand. The big business driver for the foundries these days is SOCs going into mobile devices where FDSOI would appear to be a better process. I have spent a lot of effort trying to understand this issue. I have discussed this with a lot of knowledgeable industry experts and as best as I can piece together it appears that FDSOI wasn’t ready back when these companies were making technology decisions. There is also a lingering concern about the SOI substrate cost and the availability of enough wafers to service an Intel, TSMC or Samsung.

The bottom line is FDSOI will be in use at ST Micro and some production volume at Global Foundries. IBM will utilize SOI for FinFETs. At 14nm with process development essentially complete, SOI is unlikely to be much more than 5% of production volumes.

10nm and 7nm Forecast

Another interesting question is could SOI increase market share at 10nm or 7nm. I believe 10nm development is pretty well along at this point and companies that have invested so much money and time into FinFETs are unlikely to change after one generation. There is a lot of published work from companies like TSMC on Ge PMOS fins for 10nm and they have even made an announcement that they plan to use Ge PMOS fins at 10nm. Possibly Global Foundries could ramp up FDSOI if they see a lot of demand but I think it is unlikely anyone else would switch.

At 7nm there are differing opinions of the viability of FDSOI. There appears to be a clear path to 10nm FDSOI but 7nm is more controversial. At IEDM in December 2013 there was an FDSOI paper and the authors appeared to be confident 7nm could be achieved (keep in mind that the device layer has to get thinner as the gate length scales down). Other FDSOI experts I have spoken to are less optimistic.

Conclusion
Based on what companies are doing today, the installed and planned capacity for the companies, the likelihood of changes at 10nm and the difficulties of scaling FDSOI to 7nm, I expect the leading edge logic market to look like this:

[TABLE] align=”center” border=”1″
|-
| style=”width: 90px; height: 17px” | Node
| style=”width: 90px; height: 17px” | FDSOI
| style=”width: 97px; height: 17px” | FinFET on bulk
| style=”width: 96px; height: 17px” | FinFET on SOI
|-
| style=”width: 90px; height: 17px” | 14nm
| style=”width: 90px; height: 17px” | 2.1%
| style=”width: 97px; height: 17px” | 96.2%
| style=”width: 96px; height: 17px” | 1.7%
|-
| style=”width: 90px; height: 17px” | 10nm
| style=”width: 90px; height: 17px” | 5.0%
| style=”width: 97px; height: 17px” | 93.5%
| style=”width: 96px; height: 17px” | 1.5%
|-
| style=”width: 90px; height: 17px” | 7nm
| style=”width: 90px; height: 17px” | 1.6%
| style=”width: 97px; height: 17px” | 96.9%
| style=”width: 96px; height: 17px” | 1.5%
|-

SOI clearly has its place in the mobile market and is also gaining a lot of traction in the RF front end of cell phones, but given the current technology and capacity commitments of the leading edge logic producers FDSOI appears likely to peak at only 6.5% of the leading edge logic market.

lang: en_US


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