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Bring Water to those in the World that need it

Bring Water to those in the World that need it
by Luke Miller on 08-03-2014 at 3:00 pm
Categories: FPGA

Dear Reader, I need your help with something.

Invention is the Mother of necessity. When I bought the Miller Farm, it came with a very shallow well. What that meant is priming the pump, alot. Me being an engineer weighed the options. The wife, with 5 kids to bath, wash clothes, cook, etc.. was a bit overwhelmed. Of course the worst day was like 97 degrees and no water. It’s the simple things eh?

I realized that overall the well was capable of producing about a 0.25 Gallon per minute. I just needed a way of capturing that water and storing it in a tank to get one day ahead on water.

0.25 Gallons/Min x 24 hrs = 360 Gallons of water per day, Potentially.

This lead to the invention of the Well Doctor.

Here is a nice video to explain the Well Dr.

I used a flow sensor which feeds a CPLD/FPGA board and uses an Algorithm to sense flow and when the flow drops, prime is not lost. It adapts and constantly changes as the water table does. What is does, is it controls the pump via a relay, which control’s the ON/OFF time based on the success of the last run. Very simple but has been working great for years.

What I would like to do is get this technology to others in the world that do not have the luxury of water. If a hole can be dug and it has water, then this device will get you a day a head. So I am asking you if you can help me find the right channels to see if we can make this happen. I have written the water charity org’s etc.. and no avail? Perhaps a kick starter?

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Open Source Verilog

Open Source Verilog
by Paul McLellan on 08-03-2014 at 8:01 am
Categories: EDA

Over the years there have been various open source EDA projects but none that has realized a full industrial strength design tool that has broad adoption and is strong enough to compete with similar products from the EDA industry.

Open source is clearly a great way to develop software. Lots of people can see all the source code and there is a sort of wisdom of crowds effect. As Eric Raymond famously said, “with enough eyeballs all bugs are shallow.” But there are two weak aspects to open source. Firstly, although it is a great development model it is not a great business model. It is hard to make money selling something that is also available for free. For sure, big companies will pay you something in support fees to make a problem go away and perhaps there are other for-fee services that can be built on top of the product. But there is a limit to how much can be charged. If a big EDA company open sourced all its software, nobody is going to make $50M deals since it is cheaper to set up a team of engineers for a couple of million and pull down the source and support yourself. The second problem is that open source works best when the programmers understand the problem they are solving, which usually means that the product being developed is one programmers will use themselves. Linux, gcc, Firefox, Apache (the web-server not the subsidiary of Ansys), mySQL and so on are the most successful open source projects, written by software engineers for software engineers. When a marketing person specifies the product details and then an engineering team implements them then this model doesn’t work so well. If remember reading a quote (but I can’t find it today) that “if you need a specification the project is already in trouble.”

Tachyon Design Automation has been in existence for years and sells a Verilog simulator called CVC (for compiled Verilog code, since it compiles Verilog straight into x86 code with lots of detailed optimization). It supports full IEEE 1364 (2005) Verilog. Although any simulator’s speed depends somewhat on exactly what is being simulated, it is often the fastest simulator on the market for a given workload. One customer found that they couldn’t get their nightly regressions to run in one night with one of the big 3 EDA companies Verilog simulators but it would with CVC. This is not a cheap but adequate simulator, it is fully competitive.

CVC was developed by Steve Meyer whose roots go back to Gateway (where Verilog was developed and where the roots of Cadence’s simulation technology originate), Chronologic (where Synopsys’s VCS was originally developed). Antrim integrated the technology in their AMS simulator, which is a very demanding environment.

Tachyon’s customer base is mostly small companies who are not big enough to get the attention of the big 3 EDA companies’ salesforces but they also have some larger companies that use it to give additional capacity and keep a check on their primary simulator. However, selling against the big EDA companies is difficult. The big accounts get their simulators as part of a much larger deal, and the small companies don’t consume enough licenses.

So Tachyon have decided to do something different. They are making the entire simulator open source. You can download it from their website. Big semiconductor companies are suddenly interested since they want access to the source. Not so that they can fix their own bugs, they will pay Tachyon to do that, but so that they can integrate their own technology in with the simulator to improve their own verification effectiveness.

Tachyon Design Automation’s website is here.


More articles by Paul McLellan…

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Enabling Higher Level Design Automation with Smart Tools

Enabling Higher Level Design Automation with Smart Tools
by Pawan Fangaria on 08-02-2014 at 10:00 pm
Categories: Concept Engineering, EDA

Although design houses have always strived for optimizing best design flows according to their design needs by customizing the flows using effective and efficient internal as well as external tools, this need has further grown in the context of design scenarios getting wider and wider from transistor, gate and RTL to system level. Today, it’s rare a single flow connects the system up to transistor in terms of design, verification or debugging; however comprehensive methodologies are must at all these levels to reflect the effect of any change at transistor, gate or interconnect level up to the system level, or let’s say IP level which is integrated into an SoC.

A couple of weeks ago I was talking about Concept Engineering’sS-engine[SUP]TM[/SUP] which could be easily integrated into any design automation tool for automatic schematic generation (and smart editing) that could enable transistor, gate or SoC/IP interface visualization at any level of abstraction in the design for efficient design and system exploration, analysis, debugging and integration. After learning that Verific Design Automation, Alameda, CA has integrated Concept Engineering’s Nlview[SUP]TM[/SUP]schematic generation and visualization engine with their netlist database (press release here), I looked a bit deeper into Nlview and this integration.

Nlview Widgets is pioneered by Concept Engineering which is used to automatically generate and visualize schematic diagrams at various levels in the design process including transistor (with electrical components), gate, RTL or complete block and system. The schematics thus created can be interactively controlled and modified by designers as per their need, with a capability to incrementally generate and further add parts of schematics.

Look at the part of schematic using operator signs with bus connectivity (which may come from any third party parser). The Verific parser (SystemVerilog, VHDL…) and VVDI-link(connectivity package provided with Nlview software package) give Nlview seamless access to the Verific netlist database.

In this schematic with busses, the rippers are automatically created. The Nlview performs automatic net bundling from the connectivity with single-bit level. The IO port buses and the bus pins of the muxes need to be indicated to Nlview.

In this schematic, signals are passing through hierarchical blocks. The Nlview provides features such as putting the blocks in different colors, folding and unfolding of hierarchy with +/- signs, incremental navigation and so on.

There are host of other features including timing annotations, incremental generation and viewing, and others. More examples of schematics can be seen here. The schematics are optimized by using robust, fast algorithms.

The Nlview Widgets are customized according to different GUI environments such as NlviewQT for Qt development environment, NlviewTK for Tcl/Tk based GUI environment and so on. Today, Concept provides NlviewQT, NlviewTK, NlviewJA (for Java platform), NlviewMFC (for MS Windows platform based on MFC library), NlviewWIN (for MS native Windows), NlviewWX (for wxWidgets cross-platform), NlviewP TK (for Perl with Tk) and NlviewCORE. The NlviewCORE is without GUI which can output graphic files like SVG, PostScript or PDF in batch mode. The provided core APIs and algorithms are same in all of them except the GUI interfaces.

By integrating Nlview schematic generation in EDA applications such as high level synthesis or logic synthesis, verification, physical design, test automation etc. designers or tool owners can enhance their tool’s capability in terms of wider and deeper navigation, performance, on-the-fly IP/block management and integration, incremental schematic generation and viewing, greater control and visibility over the synthesis process, easy and integrated debugging environment and so on, thus improving designers productivity.

The VVDI-Link in the connectivity package, aided by standard Verilog, VHDL or SystemVerilog parsers from Verific, enables automatic generation of schematic through Nlview for Verific which acts as front-end for several EDA and FPGA tools for simulation, emulation, verification, synthesis, analysis and test of RTL designs.

With 10s of thousands of installed EDA applications using Nlview Widgets, it’s clearly an industry standard for schematic generation and viewing that provides unparalleled flexibility, customizability, controllability, performance and reliability to the integrators.

More Articles by Pawan Fangaria…..

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FDSOI Target Applications Are…

FDSOI Target Applications Are…
by Eric Esteve on 08-01-2014 at 12:05 pm
Categories: FD-SOI

Not PC segment, not necessarily Application Processor for Mobile, despite the power efficiency advantage versus a bulk technology. After several weeks filled by very animated and controversial discussion about FD-SOI cost, thanks to Semiwiki bloggers and readers, it seems interesting to elevate the debate and try to figure out if FD-SOI could be a successful Silicon technology option, and why. By “option”, I mean that I don’t expect FD-SOI to completely replace the bulk technology (planar of FinFet), and solve the Moore’s law economic issue forever, but rather to offer a viable option to stay on a 28nm technology while benefiting from 20nm bulk performance, at a lower cost, as explained by Paul McLelan in this recent FD-SOI: 20nm performances at 28nm Cost blog. To be successful on the market, a technology should bring a technical advantage over the currently used solution, but that’s necessary, not sufficient. The technology should also be endorsed by at least one of the market leaders. It’s better, as the technology offer is now more credible, but still not enough to guarantee the market adoption. Damn! What else is missing? In fact, we enter into the non-rational area of industry psychology: risk aversion, fear in front of innovation. How to overcome this human behavior? Educate, evangelize, and even more important, convince by showing real cases (show me the Silicon) success!

Why did I mention the PC segment? Because I have read many comments during the past weeks that we can summarize by: “Intel did not select FD-SOI, thus FD-SOI is not a viable option”. Come on! Do you need me to list the so many examples of Intel market failures? Is Intel engineering culture is to design for power efficiency? No, the company culture is to design for higher and higher performance. It was a winning strategy in the 2000’s (remember that the main PC sales argument was the processor frequency). I am sorry, but it’s a completely failing strategy in the 2010’s when addressing the mobile market. So, yes, Intel did not select SOI technology, but who known if it was for scientific reason, or because of the company culture? As far as I am concerned, Intel has selected another technology option, more complicated, more expansive, and this is not a good reason to disqualify FD-SOI.

As you certainly know if you look at the semiconductor ranking, the #2 SC company is Samsung, with a much diversified offer than the #1, as the company build DRAM, Flash, Application Processor for mobile, and propose a foundry business. Samsung is the above mentioned market leader, and you can read this announcement “On May 14, ST and Samsung Electronics Co. Ltd. announced the signing of a comprehensive agreement on 28nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology for multi-source manufacturing collaboration. The licensing accord provides customers with advanced manufacturing solutions from Samsung’s state-of-the-art 300mm facilities and assures the industry of high-volume production for ST’s FD-SOI technology.”I found this wording in ST first half 2014 financial results document, at a location showing the company commitment to FD-SOI: it was the 3[SUP]rd[/SUP] paragraph of the “Recent Corporate Developments”, the first two dealing with ST executive nominations. This clearly shows how important is FD-SOI technology for ST future.

You may think that this is corporate communication only, but I remember, when working with TI ASIC, two events related to TI product port-folio. The first was in 1995, when TI decided to kill the 20 years old microcontroller product line, the second a couple of years later when the same decision was made about the ASIC product line, despite the prestigious ASIC customers like Sun or Siemens… That I mean here is how important is it for a product group when the management trust in it success. Not sufficient to guarantee the success, but necessary when it’s time to make decision about heavy investment, whether to expand fab or support market promotion campaign. This positioning is also key when a key account manager has to convince his customer to invest into an ASIC built in FD-SOI technology. That simply helps passing the risk aversion or fear in front of innovation barrier.

If you drag into this document, you will see this table, revenue by product line in Q2 2014 and 2013. DCG means Digital Convergence Group, it encompass ASIC, Consumer (mainly Set-Top-Box) and the legacy ST-Ericsson products. If you compare Q2 2014 and 2013, you clearly see what ST problem is: DCG revenue is been cut by 50%! For ST management, FD-SOI will be the solution to grow by 2X this Digital Convergence Group…

Thus I have listened to the analyst call hold on July 23[SUP]rd[/SUP], chasing for more information, especially about FD-SOI. And, by the way, many questions from analysts arise about FD-SOI. About FD-SOI adoption from ASIC customers: ST claims 18 FD-SOI ASIC design win, in the communication infrastructure and consumer segments, including two major design win (at major accounts?). Looks healthy, isn’t it?

One of this major design win is for a communication infrastructure ASIC in 14nm FD-SOI. This is the guarantee that FD-SOI technology roadmap is solid, and not holds at 28 nm. The total number of design wins is also a positive sign: ST is building an IP ecosystem around FD-SOI. We know that the company supports internal IP developments, but we also know that major IP vendors have been involved, making FD-SOI IP available for ST… and Samsung customers.

From Eric Esteve from IPNEST

More Articles by Eric Esteve…..

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eSilicon and the Ten Minute Quote

eSilicon and the Ten Minute Quote
by Paul McLellan on 08-01-2014 at 8:01 am
Categories: eSilicon, Semiconductor Services

One of the challenges in bringing a design into production is getting a quote that includes all the various stages of the process. The quote cycle typically takes a couple of weeks. It is also pretty wasteful. A typical design might be quoted by 3 manufacturers and so 2 out of 3 quotes are wasted expense because the design is lost to a competitor (and, of course, ultimately ends up as a cost on the designs that are won). When the quote is done manually there are high risks of errors: options that get forgotten, or options that are incompatible being ordered together.

eSilicon has had the goal of automating as much of the process of handling the fab operations and customers with designs in their manufacturing flow can access the complete status online. Internally they had an automated tool for handling quotes that made the process faster and less error prone. They started making this available to their customers, initially just for multi-project wafer (MPW) prototype shuttle runs. Then earlier this summer they made the entire quote system for prototypes and production available. At DAC they had a demonstration of the system in action which I blogged about then, but there was no video of the demonstration so there were probably lots of things that were not entirely clear.

Today, eSilicon ran a webinar in which “live on stage” they actually quoted a part. As in the DAC demo, the specification of the chip was not canned numbers but were being provided by a customer of eSilicon. To make it even clearer that this was live and not staged, a couple of times the audience were polled for a choice. It took about 10 minutes to enter all the data and then perhaps 30 seconds from completing it to have the quote.

There are several sections that you need to complete: the process, the die size, the package and so on.

Here is specifying the package. The quote system automatically only gives you choices that are compatible with the choices you have made so far. In the webinar the chip was bumped and so no wire-bond packaging options are offered since that is incompatible, for example.

Then finally, get the quote. It is actually a multi-page document with a fair bit of detail, but the cost of prototypes and the cost in volume production are probably the most important. Here is a bit of the quote. Using the system is almost as simple as shopping on Amazon except you are buying things that cost in the $millions.

Changing a few test options to get the price down a little was even quicker. For now, you have to enter the whole design a second time but later this year that obvious inconvenience will be fixed and you will be able to start one quote by starting from another and just making incremental changes.

For now the quote system covers only TSMC processes from 28nm up to 0.35um. Perhaps the most impressive thing about the quote system is that there is a complete TSMC cost-model under the hood, along with similar (but much simpler) cost models for wafer sort, final sort, packaging, assembly.

One thing to emphasize is that the quote is a legally binding document (well, once signed of course). It is not an “estimate” of what eSilicon will charge you. It is a price that eSilicon will stand behind, and indirectly TSMC and the other people in the supply chain too.

This is a game anyone can play. Go to the eSilicon website here. In the middle at the top of the screen it says “GDSII Quotes”. Sign up if you are not already a user, then you too can play with the system or, if you are at just the right point in your design process, use it for real.

UPDATE: the link to the webinar is here (registration)


More articles by Paul McLellan…

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It’s not a fiction, it’s about to turn into reality

It’s not a fiction, it’s about to turn into reality
by Pawan Fangaria on 08-01-2014 at 2:00 am
Categories: General

Often I used to wonder why a search engine company would invest so heavily and indulge into stuff like smartphones, home automation devices, servers and many other exotic, innovative things they are doing internally and externally. But when I connect the dots, I find that this company in on certain massive missions which, if accomplished on full scale, can completely alter the way we do things in various spheres of life across the world. Internet-of-things will become a misnomer; it will become internet-of-one-thing, or the other thing, into the cosmos of many things or everything. There are certain things owned by this company which will seamlessly seep in through most of the devices across the world. Is this company going to own the world? Of course governments will have much greater say for their countries; however, versatile and omnipresent services provided by this company will have the governments listen to what the company says. You must have guessed it right about which company I am talking 🙂

I have many things to say about Google, which acquired and then sold MotorolaMobility (obviously, the most important aspect of those deals was to acquire the huge quantity of Android patents and retain them), acquired Nest Labs(a home automation company), Waze(a community based traffic and navigation apps provider) and is about to acquire Twitch(a video game streaming company), and of course notable past acquisitions include Android, YouTube, Applied Semantics(maker of AdSense), Postini(an email security and service provider) andDoubleClick(display ad technology) among others. For now, I will restrict myself to the much talked about ‘driverless cars’, what it can bring to the society and how it connects into the larger scheme of Google to connect and control the world.

Before getting into the technology details, let me talk about how ‘driverless cars’ can change the transportation scenario, associated infrastructure and other feel good factors for the societies across the world.

These cars can become ubiquitous, at your fingertips to pick-or-drop you from/to your office, home, discotheque or anyplace you are in. People will not need to own cars, unless some have obsession about owning a car. The net advantage is less number of cars releasing most of the parking space occupied by stationary cars. Since a driver or your spouse doesn’t need to drive all the way to pick/drop you, there will be less traffic on the roads and that can eliminate all detours, the result is reduction in the miles driven, saving of fuel, less pollution. A significant reduction in opportunity cost will be in terms of less person hours spent on roads.

Because of no human involved in driving, it will be a perfect disciplined car movement without any personal biases and that can lead to almost accurate time to distance. This will make the best use of roads with best co-ordination with other cars and vehicles providing best safety and less road fatalities. Your percentage of time spent in daily routine travel can significantly reduce and become joyful or peaceful as you like.

All space in the car is yours, all passengers, no driver and therefore no reserved seat and steering system for the driver. People can interact face-to-face and enjoy car infotainment system. It’s one for all, children, young, adult, old whether they can drive or not. The car makers can use this advantage in most creative ways to engage their passengers.

It’s obvious, it can reduce the burden on traffic police personnel; they can focus more on planning of roads, estimating population and average number of cars and other vehicles in particular areas and so on.

Doesn’t it look like a dream? But it’s doable. Of course, there are risks involved, one major risk is about security, imagine a terrorist cracking the central control system and breaking the whole system of cars across the city. Other issues can be on commercial side – private car sales will drop drastically, existing drivers will have to find other jobs and so on. And many other issues will crop up. However, my guess is that solutions to these can be worked out after a pilot commercial run can be successful in a city. Now, let’s talk about the technologies that are making it possible, Google is magnificent in that aspect with its open innovation lab and continuously promoting great innovations.

You see the device on top of the car? It’s called lidar (light detection and ranging system) which performs the most important operation, sensing about the car’s surroundings and movements. It has laser powered sensors which throw laser beam at an object and measure its return time to calculate the distance. The 3D data about the surroundings of the car can be fed to a computer inside the car. The resolution can be so high that it can detect small objects and differentiate between an animal, a solid or a paper material. Along with lidars, there are other sensors, radars and cameras. The lidars can work for long range at highways in all weather conditions. The cameras are used to read traffic signals of different colors and road signs. There are several companies in lidar manufacturing business. The one which built a 64-laser unit lidar for Google’s prototype car is Velodyne Lidar Inc. Definitely cost of lidar is very high and has to go down significantly for that dream to come true. The number of laser units can be reduced as per need which can significantly reduce the cost. Several companies along with car makers are working on the cost aspect, that’s a positive sign 🙂

Let’s look at the other aspects of technology. Do you see the dots connecting somewhere with what Waze has in store along with GPS system enabled by Google maps? And Twitch for gaming inside the car?

Anyway, I would like to talk about the one; I am there wherever you go – Android. After Android in phone, tablet, notebook, wearable and even TV, it’s in your car now. That’s Google’s quest to make it universal and thus control the world, for good reason, of course. The Android Auto has all car-centric features which today need an Android smartphone connected to the car system, but I am sure Google can make the car system independent of phone going forward. Movies, shows, games, maps, Google Now, automatic voice message read outs etc. can be played on a big screen inside the car. What is more important is the connectivity among cars and with other vehicles. Will that unfold into a specialized internet-of-cars or internet-of-autos connected to rest of the world through other threads? More later after we ponder over these and throw more ideas, questions, opinions, issues involved… A technology always comes with opportunities as well as challenges!

More Articles by Pawan Fangaria…..

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How to Beat a New Entrant with Superior EDA tool

How to Beat a New Entrant with Superior EDA tool
by barun on 07-31-2014 at 8:00 pm
Categories: EDA

How to handle a new entrant with superior product quality is a point of worried to all EDA companies. Due to continuous research happenings and relatively lower investment requirement new and new EDA start-ups are coming in EDA domains regularly. In several situations, these start-ups offer product of superior quality in terms of run-time or performance metric achieved compared to the existing product available in the market. The immediate reaction of incumbent companies is to cut the price of the product to prevent a start-up to take away its existing or new customer. And the sales team, in good number of cases, asks for price lower that the start-up price to keep existing customer base intact. The argument follows is that as the existing product has lower quality than the new product, the price also should be lower.

But that is not the case, the existing company can even price the its product at higher price and even keep its customer base intact or acquire new customer – thanks to huge switching cost or adoption cost involved in EDA product. Let us see how a switching cost or adoption cost creates a great safety net to the incumbent company.

Scenario 1: Existing customer
Let us assume utility perceived by customer for the existing product ‘x’ is u[SUB]x[/SUB]. The utility perceived by customer for the new product ‘y’ is u[SUB]y[/SUB] and u[SUB]y[/SUB] > u[SUB]x[/SUB]. The price of product ‘x’ is p[SUB]x[/SUB] and price of product ‘y’ is p[SUB]y[/SUB]. The switching cost for customer from product ‘x’ to product ‘y’ is S[SUB]xy[/SUB].

So to change from product ‘x’ to product ‘y’ customer incurs total cost of p[SUB]y[/SUB] + S[SUB]xy[/SUB]. He will buy product ‘y’ only when the difference of utility perceived by him exceeds the additional cost will pay to migrate from product ‘x’ to product ‘y’ i.e.
p[SUB]y[/SUB] + S[SUB]xy[/SUB] – p[SUB]x[/SUB] < u[SUB]y[/SUB] – u[SUB]x
[/SUB]
So, p[SUB]x[/SUB] > p[SUB]y[/SUB] + S[SUB]xy[/SUB] – (u[SUB]y[/SUB] – u[SUB]x[/SUB])

And he will not migrate if p[SUB]x[/SUB] < p[SUB]y[/SUB] + S[SUB]xy[/SUB] – (u[SUB]y[/SUB] – u[SUB]x[/SUB])

And if S[SUB]xy[/SUB] > u[SUB]y[/SUB] – u[SUB]x[/SUB] p[SUB]x[/SUB] can be more than p[SUB]y[/SUB]

Hence the incumbent company can demand more money from its customers even its product has lower quality than the upcoming one.

Scenario 2: New customer
For using any EDA tool a customer needs to invest to evaluate the tool, learn the tools and integrate the tool in its flow. This is called adoption cost. Let us assume adoption cost for product ‘x’ is S[SUB]φx*[/SUB] and adoption cost for product ‘y’ is S[SUB]φy
[/SUB]
So customer will choose product ‘y’ over product ‘x’ if the difference in total cost paid by him is lower than the difference utility perceived by him i.e.

(p[SUB]y[/SUB] + S[SUB]φy[/SUB]) – (p[SUB]x[/SUB] + S[SUB]φx[/SUB]) < u[SUB]y[/SUB] – u[SUB]x[/SUB] i.e.

p[SUB]x[/SUB] > p[SUB]y[/SUB] + (S[SUB]φy[/SUB] – S[SUB]φx[/SUB]) – (u[SUB]y[/SUB] – u[SUB]x[/SUB])

The customer will choose ‘x’ over ‘y’ if p[SUB]x[/SUB] < p[SUB]y[/SUB] + (S[SUB]φy[/SUB] – S[SUB]φx[/SUB]) – (u[SUB]y[/SUB] – u[SUB]x[/SUB])

If (S[SUB]φy[/SUB] – S[SUB]φx[/SUB]) > (u[SUB]y[/SUB] – u[SUB]x[/SUB]) then p[SUB]x[/SUB] can be more than p[SUB]y[/SUB]

Hence in EDA industry switching cost and adoption cost has a big importance and company needs to focus on these two aspects in addition to the quality of the product. Let us now see how company can increase switching cost (from its product) and decrease adoption cost
Few of the ways to increase switching cost are

  • Offer substantial renewal discount to customers
  • Increase the compatibility of tool with other tools used in the flow
  • Provide regular training at low cost to the tool users
  • Create platform for user interactions where users can discuss the issues and solution of regarding usage of the product

Few ways to decrease adoption cost

  • Provide tools to the university at very low price so that huge pool of engineers trained in the tool
  • Make the tool compatible with the other common tools used in the flow
  • Create a easy user interface or readymade scripts
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IO Design Optimization Flow for Reliability in 28nm

IO Design Optimization Flow for Reliability in 28nm
by Daniel Payne on 07-31-2014 at 5:00 pm
Categories: EDA, MunEDA

User group meetings are a rich source of information for IC designers because they have actual designers talking about how they used EDA tools in their methodology to achieve a goal. Engineers at STMicroelectronicspresented at a MunEDAUser Group on the topic: I/O Design Optimization Flow For Reliability In Advanced CMOS Nodes. That presentation was then turned into a paperat the IRPS 2014 (International Reliability Physics Symposium) held in Hawaii just two months ago. I’ll provide my take on this 5 page paper in this blog. Reliability is pertinent to me because I’ve had two consumer devices fail in the past year – an iPad 3 and MacBook Pro. Maybe both devices would still be working if Apple did more reliability simulations on the components in their iPad and if memory makers did more reliability simulations on their DRAM chips.

There are three main wear-out mechanisms categorized by reliability engineers:

  • BTI – Bias Temperature Instability, where the Vt degrades over time.
  • HCI – Hot Carrier Injection, where an electron or hole gets enough energy to break an interface state, becoming trapped in the gate dielectric, changing switching.
  • TDDB – Time Dependent Dielectric Breakdown, where the silicon dioxide in the CMOS gate breaks down creating a conducting path through the oxide to the substrate.

The promise of the MunEDA flow for STMicroelectronics is to automatically analyze and size devices that meet reliability requirements on I/O circuits on a 28nm CMOS process.

Reliability modeling needs to occur across the entire Vgs and Vds design space. In STMicroelectronics’ FDSOI PDK, MunEDA uses Eldo UDRM simulation results, including BTI, HCI and TDDB effects.

A high age rate is shown in Red, while a low age rate is depicted with the Blue color. Age rate means the rate of defect nucleation that causes device degradation, like: gate leakage, oxide breakdown, or hard breakdown. Equations were shown for the Mean Time To Failure (TTF), failure rate (FR) and Failure in Time (FIT).

The EDA tool flow for reliability simulation uses a SPICE circuit simulator (ELDO in this case for STMicroelectronics), along with aging model parameters, a user-defined reliability model, and a comparison of aged simulation versus fresh simulation.

Designers generate an aging report with useful information like: Vth shift, mobility degradation and FIT numbers. Moving from theory into actual practice, an I/O buffer circuit was selected for analysis and automated sizing using both a 28nm bulk and UTBB FDSOI process.

The tool flow for automated transistor sizing including aging and reliability constraints uses the WiCkeD tool from MunEDA:

What makes this flow different is that MOS widths and lengths are changed not only within Reliability Design Rules (RDR), but also taking into account reliability SPICE simulations during the optimization, thus keeping the growth in layout area to a minimum. There are multiple circuit simulations performed to determine the stress per device, and then aged performances are simulated to create reliability constraints for sizing.


Restricted design parameter space Pi to fulfill all the performances f(p) under reliable constraints c(p)

Once optimization is complete, the designers could choose a trade off between different sizing strategies for: Area, Performance, Reliability.

Silicon Results

A 28mm test chip was built to validate and compare actual results versus predicted results. A ring oscillator circuit was used for dynamic stress with maximum operating frequencies by connecting five bidirectional I/O cells together.

The frequency of the ring oscillator was simulated and compared versus silicon as a function of the stress time, showing close correlation:

Another comparison of reliability simulations shows good accuracy of the WiCkeD tools versus silicon:

Summary

You can now use a tool flow that optimizes MOS device sizes taking into account reliability factors. The WiCkeD tools from MunEDA were shown to predict aging and reliability effects that matched silicon. The steps used in this flow look easy enough to learn, and result in a more robust circuit that meets your reliability requirements. The complete five page paper can be read online.

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Making IP Reuse and SoC Integration Easier

Making IP Reuse and SoC Integration Easier
by Daniel Payne on 07-31-2014 at 2:00 pm
Categories: EDA

The last graphics chip that I worked on at Intel was functionally simulated with only a tiny display size of 16×16 pixels, because that size allowed a complete regression test to be simulated overnight. Our team designed three major IP blocks: Display Processor, Graphics Processor and Bus Interface Unit. We wanted to also integrate an 80186 core, but our IP team in Japan couldn’t meet the schedule, so we had to be less ambitious and rely upon an external CPU. Needless to say, when silicon came back the only display size that worked properly was 16×16 pixels.

Today we have SoCs that contain hundreds of IP blocks and cores that can come from other departments, other divisions or even bought as commercial IP. So the challenge still remains the same – how do I know that I’ve done enough functional verification, integrated all the IP properly, and uncovered enough corner-case bugs?

Assertions are one technology that promise to meet those challenges, and an assertion is a logic statement that defines the intended behavior of signals in a design. You can either write an assertion manually based upon your own understanding, or have a tool automate the creation of some assertions to assist your verification efforts. Atrentahas an EDA tool called BugScope that can automatically create assertions for an RTL design by reading in your functional stimulus and RTL source:

Methodology for Assertion Reuse in SoC – MARS

Users of BugScope can run a few different apps that provide assertion synthesis.


BugScope Assertion Synthesis Applications

One app has the acronym MARS – Methodology for Assertion Reuse in SoC. With MARS an engineer can verify that integrating each new IP block at the SoC level is correct by:

[LIST=1]

  • Verifying that the IP is configured properly at the SoC level
  • Any design issues are flagged at the SoC level
  • Measuring coverage that may have been missed at the IP level

    So assertion synthesis complements the traditional functional simulation practice in the goal to verify that an SoC is both functionally correct and ready for tape out. With assertion synthesis you can actually measure the progress towards your verification goals. Your digital design flow with assertion synthesis added looks like:


    Assertion Synthesis Flow

    Design engineers create RTL source code and then add test stimulus as inputs to the assertion synthesis tool.

    In MARS, once the properties are generated, they represent the known good state space of the design. BugScope then synthesizes assertions which create an executable specification for use in SoC integration. Note that no property classification was required at all. In fact, the entire MARS flow is fully automated.

    During IP development, output from assertion synthesis are properties that will always be true for that stimulus. If you see lots of new coverage properties when you scan through them, it may mean that your existing stimulus has some holes that verification runs have not covered. Some of these properties may also indicate that you’ve found a new design bug.

    IP designers review the properties for obvious bugs and coverage holes – not full blown classification since that’s difficult to do and time consuming. They would do this in combination with the Progressive App, which provides continuous, instant verification status.

    Once the IP team is ready to hand RTL to the SoC team, they generate assertions. You then bind these assertions to your favorite HDL simulator, emulator or even a formal verification tool. In simulation and emulation, these act like an executable specification. Once again, when you simulate or emulate and an assertion is triggered, you have just found either a specification error, an IP-level coverage hole, or a new bug to fix.

    With all of this feedback a verification engineer can then write new stimulus to fill any coverage holes, provide debug info to hardware and software engineers to fix specification errors, and ultimately debug info to fix corner-case bugs.

    Live Webinar

    Learn more about automated assertion-based verification methodologies for IP-SoC integration at the next live webinar on Thursday, August 7th where Larry Vivolo will be presenting. There’s a brief registration process, and during the one hour webinar you can ask questions at the end to see how this methodology might help out on the verification quality of your present or next IC design.