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November 30, 2014June 14, 2019

Solution for PI, TI & SI Issues in 3D-ICs

Solution for PI, TI & SI Issues in 3D-ICs
by Pawan Fangaria on 11-30-2014 at 7:00 pm
Categories: Ansys, Inc., EDA

As we move towards packing more and more functionalities and increasing densities of SoCs, the power, thermal and signal integrity issues keep on rising. 3D-IC is a great concept to stack multiple dies on top of each other vertically. While it brings lot of avenues to package dies with multiple functions together, it has challenges as well to handle power distribution, tackle inter-die thermal issues and maintain signal integrity. Other than that 3D-ICs bring a typical issue of accommodating heterogeneous dies with designs at different technology nodes. As technologies and designs have progressed to newer ventures, EDA tools have always kept pace with them to provide best automation in getting volume production.

Today, ANSYS has a great suite of tools which can very accurately analyze power, noise and reliability for any chip taking into account its package and system level interactions as well. These tools are capable of handling all kinds of issues including inter-die effects that arise in 3D-ICs.

RedHawk can perform multi-die (each die can have design at different process node) power integrity analysis with or without shared power/ground nets. It can do concurrent analysis when detailed data for each die is available; in case physical data is not available for any particular dies then also it allows early design analysis by using power models (CPM) for those dies.

In 3D-IC, there is a tendency of heat getting trapped between dies which can lead to electro migration (EM) effect and that can cause opens and shorts getting build up in the design. The allowable current density of wires also gets affected. The thermal analysis using Chip Thermal Model (CTM), package model, and system level heat transfer coefficients enables generation of temperature profiles on 3D-IC components including chip metal layers, package, and bump/micro-bump/TSV for accurate thermal-aware EM methodology. Also, with higher current densities, the ESD analysis across dies must be performed.

ANSYS offers solution with proven tools to model wide-IO jitter for an interposer or 3D-IC design, extract channel parasitic and analyze the impact of SSN channel design on power and signal integrity of the design. Parasitic of a single TSV in a uniform array or hundreds of TSVs in an irregular array can be accurately extracted. The package and die can be taken into consideration to co-optimize decap as well.

ANSYS provides excellent modeling capabilities that are Spice-accurate and take into account the operating conditions, parasitic and temperature effects. CPM (Chip Power Model) is a compact model for full-chip power delivery network that contains switching current profile as well as parasitics of on-chip non-linear devices including decaps, loading capacitance and power/ground coupling capacitance. It accurately models the electrical response of the chip for a wide range of frequency, from DC to multi-GHz, thus enabling the analysis and optimization of system-level power integrity designs.

Generated by RedHawk and Totem, CTM (Chip Thermal Model) is a comprehensive chip-level thermal model based on chip’s operating conditions, its layout and specialized temperature-dependent power libraries. It captures the power and current inside a chip as a function of temperature, location, electrical activity, interconnect, layer-by-layer metal density and thermal conductivity of materials on silicon and package for accurate simulation. Sentinel-TI uses CTM to perform accurate closed-loop chip-package-system thermal analysis.

Similarly, CSM (Chip Signal Model) is used for SSO (Simultaneous Switching Output) simulation; it takes into account the power and ground rails on the die and hence the output characterization is power/ground noise dependent. TSVs (Through Silicon Via) have to be extracted with all parametric values and modeled for accurate power/signal integrity and reliability analyses. ANSYS provides capability to extract 1000s of TSVs in a large array and create accurate 3D EM models to capture frequency dependency and crosstalk. Sentinel-TI can be used to generate comprehensive finite element simulation models for chip package that can be used to simulate the effects of thermal and mechanical stresses on the chip package.

Look for more details on ANSYS solution and offerings from other EDA vendors as well as designers and manufacturers for 3D-IC design solutions in the upcoming 3D ASIP conference to be held on Dec 10 – 12, 2014 in Burlingame, CA.

Norman Chang, VP Design Solutions at ANSYS will be presenting in Preconference Symposium as well as in a special session dedicated to “Design Analysis and Modeling – Signal Integrity, Thermal and Power Considerations”. Attend these presentations as per the schedule below –

Preconference Symposium
Dec 10, 2014, 8:30AM – 12:30PM – 2.5/3D-IC Design Tools and Flows

Session 5: Design Analysis and Modeling – Signal Integrity, Thermal and Power Considerations
Dec 11, 2014, 3:30PM – 5:30PM – Performing 3D-IC Design Trade-off with Fast Power/Thermal/Signal Integrity Analyses for Early Design Stages

IC Place and Route for AMS Designs

High-capacity IC place and route (P&R) tools can cost $200K and more to own from the big three vendors (Cadence, Synopsys, Mentor), but what about IC designs that are primarily Big Analog and Little Digital? In the EDA world we often have multiple choices for tools, and there are affordable alternatives to place and route out there. To delve a bit into this space I watched an archived webinar titled, Tanner EDA’s New HiPer Place and Route Overview and Demo.Jeff Miller was the presenter, and we’ve met in person before several times at past DAC shows.

Place and route is just one piece of the bigger tool flow now offered by Tanner EDA, Aldecand Incentia for AMS designs as shown below:

This combination of EDA companies kind of reminds me of the alliance created by Viewlogic back in the 1990’s called the IC Power Team.

The P&R product name is called HiPer Place and Route, an option to the L-Edit layout editor. Typical designs for AMS P&R are around 50K gates and using mature process nodes (350 nm to 90 nm). File formats are de-facto standards like LEF and GDS for layout, Liberty for the cell timing data, and Verilog or VHDL as RTL input. An actual demo flow was presented:

Synthesis (DesignCraft by Incentia)
Placement (HiPer P&R)
Clock tree synthesis (HiPer P&R)
Clock routing (HiPer P&R)
Signal routing (HiPer P&R)
SDF extraction (HiPer PX)
Timing Verification (TimeCraft by Incentia)
DFT (TestCraft by Incentia)
ECOs
Physical Verification

An 8 bit ADC (Analog Digital Converter) was the demo circuit, written in Verilog. Scripts were used for logic synthesis in the DesignCraft tool. For placement a rectangular region was defined and then the IOs were added, 10 rows were defined, LEF files read in, and the Verilog netlist imported. Actual placement took just a few seconds:

Clock buffering was skipped for this small design, filler cells were added for power and ground, power rails were added to the sides, and then routing was run using 3 layers:

Connectivity checks were run to confirm that no shorts or opens were detected, an then an SDF file was created from extracted interconnect for timing delays. TimeCraft was run using scripts and the output was a report on worst-case timing paths, since the timing requirements were all met there was no iteration required. The demo was simple, short and convincing.

Q&A

Q: What is the smallest geometry process that customers have used this IC design flow on?
We’ve had customer designs done at the 65 nm process node with our tool flow.

Q: What is the largest design that you’ve run this on?
Almost 200K gates have been used with this tool flow, although we see 50K as the more typical design size.

Q: How do I get an evaluation of this P&R tool?
Contact salesw@tanner.com to get started.

Summary

EDA companies like Tanner EDA, Aldec and Incentia have partnered to create a complete AMS design and verification flow. The new P&R tool has a capacity up to 200K gates, and works well for the Big A, Little D style of AMS designs. It was refreshing to see an EDA vendor actually run their tool live, instead of canned, because it produced results so quickly for the demo design. Give Tanner a call if you are doing AMS designs down to the 65 nm process node. View the complete archived webinar here, after a brief registration process.

November 29, 2014June 14, 2019

Filling the Gap between Design Planning & Implementation

Filling the Gap between Design Planning & Implementation
by Pawan Fangaria on 11-29-2014 at 7:00 pm
Categories: Dassault Systemes, EDA

As every other person is talking about IoT today, Michael Munsey of Dassault Systemes looks at this trend in the context of critical success factors and Dassault’s strategy towards providing semiconductor solution that integrates the design chain and continues to keep the semiconductor eco-system healthy and profitable. I looked at one of his presentations to his top customers where he draws the inference of changing world from 1 device for 1000’s users in 1960s to 100’s of devices per single user in near future, what will drive such devices, what are the gaps and how those gaps can be filled. Let’s see in a brief what this means.

A device for IoT will be a new class of device which will have sensors, actuators and SoC containing ultra low power processor, wireless link and power management units, all in the same package. This device will be intelligent enough to sense, analyze, anticipate and act, and will be always on.

Clearly, all of this cannot be done by one single vendor in a captive way. In order to bring excellence in all parts of the product, there needs to be design creators to bring fastest, smallest and lowest power IPs and design integrators to provide robust integration platforms for SoC implementation to bring out high quality products at right cost and right time. So, what is the gap we are talking about?

The gap comes at the time of integration of all pieces together. How do we know the final product will come in perfect order as we desired while all components come from diverse sources with lot of heterogeneity involved between them? To fill that gap, from a system’s perspective, a seamless handoff between RTL design along with IP reuse and chip implementation is needed and that can be filled by functional virtual prototyping. A functional virtual prototype between RTL and chip implementation can rightly estimate the power, performance and area before the final implementation can proceed, thus eliminating rework, shortening design cycle and meeting time-to-market. How can Dassault contribute in filling this gap faster and more precisely which can lead to a profitable business?

If you look at Dassault’s semiconductor strategy (From Productivity to Profitability) in one of my previous article, there are couple of steps between Product Engineering and Design Engineering which ensure requirement specification based management and New Product Introduction (NPI) based on what customer needs, and then IP management, protection, integration, design and validation. So, here during virtual prototyping, SoC deliverable based project management, requirement tracking and planning can be done. Dassault provides Validated IP Catalog management which can trace a best suited IP for a particular requirement and readily present its properties, thus aiding in faster and appropriate IP integration into SoC. During chip implementation, Dassault provides its versatile Design Data Management support.

Also, Dassault’s SRDV (Semiconductor Requirement Driven Verification) solution provides capability to track SoC verification and validation results back to SoC’s requirements. Read more on this in the article – Dassault’s Simulation Life Cycle Management.

It looks like Dassault is on the right toes to support the IoT bandwagon and fetch profitable rewards from there.

Verification plans overcome hope-based coverage

Verification plans overcome hope-based coverage
by Don Dingee on 11-29-2014 at 7:00 am
Categories: Aldec, EDA

Coverage is an important yet elusive metric for design verification. It often seems 90% of coverage comes with 10% of the effort, and getting the final 10% covered takes the remaining 90% of a project. Usually, it takes another tool or methodology to get at the 10% the first tool missed. With 100% closure difficult, most teams inspect what hasn’t been covered Continue reading “Verification plans overcome hope-based coverage”

November 28, 2014June 14, 2019

IC Design at ZMDI

IC Design at ZMDI
by Daniel Payne on 11-28-2014 at 7:00 pm
Categories: EDA, Perforce

As a blogger I have the privilege of meeting many IC designers from around the world, mostly through contact on LinkedIn or from connecting at trade shows. Through a contact at DACI met up with Achim Graupner, a manager of methodology and design automation from ZMDI, then asked him for an interview to understand how his group does IC design in Germany. Achim has been with ZMDI since 2004 and his background includes design engineering plus being a research assistant at the Technische Universitat Dresden.

Q&A

Q: What kind of business are you in?

Zentrum Mikroelektronik Dresden AG (ZMDI) began in 1961 and is headquartered in Dresden Germany. ZMDI is a fabless global developer of analog and mixed-signal semiconductors solutions for automotive, industrial, medical, mobile sensing, information technology and consumer applications.

Q: What are the electronic products that you offer?

ZMDI designs and develops semi-conductor products in the areas of sensing which include multi-market, mobile sensing and automotive sensing as well as products in power management, battery management, industrial ASSPs and automotive ASIC. These solutions enable our customers to create the most energy-efficient products .

Q: Where are your products designed?

We have 6 sites: Dresden (DE, headquarters), Limerick (IR), Munich (DE), Stuttgart (DE), Varna (BG) and Sofia (BG).

Q: How large are the design teams?

In total 170 engineers are working in design, layout, verification and applications, while the team size is between 5 and 30 with an average of 10.

Q: At a high level, what is your design methodology?

Our scope are mixed-signal products for whose realization we are using a top-down design approach. We follow an IC project centric approach with all IP being designed as part of the IC project. Also we do reuse IP from previous projects as well as we do integrate IP from 3rd party.

Q: When did you first start using Methodics tools?

We did our first evaluation in 2008, and we have used Methodics tools since 2010 for revision control. Methodics also has other tools for IP lifecycle management.

Q: Why did you chose Methodics tools?

We’ve been using Subversionin version control for a long time (say 2006) and we were looking for a Virtuoso integration.

Q: Did the Methodics tools replace a similar tool, and if so, why?

No replacement, we introduced Methodics VersICas just an add-on to Subversion.

Q: What were the benefits of using Methodics tools in terms of time savings, cost savings or reduced re-spins?

As the team size is growing there is no alternative but to use tools for revision control. Especially the verification engineers never would see stable data to setup the verification environment as design data is constantly modified by other designers. Methodics VersIC greatly improves the usability of Subversion, especially to an analog designer who prefers to work with a GUI. The use of Methodics tools has a significant role in the successful implementation of our “1[SUP]st[/SUP] Time Right in Time” strategy.

The main benefit I see is in the improved usability of revision control for Virtuoso-users (analog designer, analog layout).

Q: Are there any improvements that would make Methodics tools even more useful to your team?

One challenge for us is maintaining performance over NFS.We use NFS for storage and the combination of NFS and Subversion causes performance issues. Using local disks is not an alternative as we work with a compute cluster on separate machines for interactive work and batch jobs like simulation.The Methodics workspace management solution helps a lot by reducing the amount of data in user workspaces. However, any additional performance improvements would be beneficial.
Related – Speeding up IP and Data Management

Q: How responsive has Methodics been to work with in terms of support and training?

We started working with Methodics some 6 years ago and have found them to be very responsive and pretty keen as well. SInce introducing Methodics tools at ZMDI we’ve worked with them to evolve our data and configuration management methodology significantly. In general, bugs have been fixed in a timely manner and they’ve been open to making changes based on our methodology discussions.
Summary
Engineers at ZMDI design a range of AMS products across multiple geographies, developing and keeping all of their semiconductor IP managed with Methodics, Subversion and Cadence tools.

November 28, 2014June 14, 2019

Predicting Component Temperature Early in Design

Predicting Component Temperature Early in Design
by Pawan Fangaria on 11-28-2014 at 7:00 am
Categories: EDA, Siemens EDA

In today’s electronics with multiple functions working together, heat generation is on the rise; sometimes it becomes intolerable. In fact components running at different temperatures can cause timing issues, and very high temperatures can lead to operational issues such as latch-up. An electronic system can contain chips, SoCs, PCBs and even fans and heat sinks as cooling systems. In order to see a system working reliably for its lifetime, it’s important to assess the materials, packages, mechanical design of the system, cooling systems and airflow arrangement and so on and estimate the amount of heat it can sustain without damaging the system. And this study and optimization of thermal design of the system has to be done in initial stages of the design, not later. It requires appropriate modeling of component temperatures and then designing the system for it to work under different conditions. So, how do we do this?

The first point is to consider the 3D component model where appropriate packages of the ICs are considered from their thermal conductivity properties. Adding heat sink may not be required if proper selection works well in the simulation. Mentor’sFloTHERM 3D includes material properties in its simulation which can predict case temperature for different package styles. The process to determine the most appropriate component thermal model (CTM) is iterative through continuous refinement.

How to compare the models in the first place to reduce the number of iterations and converge faster in simulation? A 2-resistor CTM is capable of predicting both case and junction temperatures without requiring any more mesh than a simple conducting block, thus having lowest computational burden, but exhibiting worst-case error of the order of ~30% which can vary according to size and type of package. Such models can be used for initial assessment of size of hit sink, number of fins, fin thickness and height needed to reduce the air-side thermal resistance of the heat sink, but not for determining the base thickness needed to adequately spread the heat.

There is JEDEC standard approach for packages with single heat flow path such as LEDs and TO-style packages (used in analog, linear ICs and power semiconductor devices). These packages use RC-laddermodels that include thermal resistors as well as thermal capacitors and can be used for transient simulations. They provide excellent results when the application environment is close to that of the test cold plate environment, for example, when the package is soldered to a MCPCB (Metal-Core PCB). Power LEDs are often mounted on MCPCBs attached to heat sink. Mentor’s T3Ster (transient thermal tester) is used to measure packaged ICs to create such models that can be used directly as a network assembly for 3D thermal simulation in FloTHERM.

DELPHI models are further up in terms of accuracy and can be used for detailed thermal design work of all but the most thermally critical packages such as stacked or 3D ICs where additional information such as temperature distribution on the die surface is needed.

Mentor’s FloTHERM PACK has JEDEC package wizard to generate a representative thermal model of the package based on the package information such as style, body size, and number of leads. The model can be updated when more information becomes available, thus making available 2-resistor, DELPHI, and detailed models for easy refining of the CTM as the design is elaborated.

In detailed model, the temperature variation is predicted throughout the package and dies. In order to predict the temperature distribution on the die, the active power variation over the die’s active surface areas has to be accounted. An SoC can have several power maps according to the circuit functions distributed over it. The leakage power which is a function of local temperature gets exacerbated by the active power. Power analysis tools are used to compute power maps.

The detailed models are validated with experiments and effective thermal resistances and capacitances are calibrated using transient thermal testing techniques. T3Ster is used to measure the response of an actual package, and then the simulation model can be adjusted to fit the experimental response, thus increasing the accuracy level of temperature. The thermal conductivity of the thermal interface material (TIM) can be accurately measured as a function of temperature by using T3Ster DynTIM tool to help choose the most suitable TIM for a particular application.

Read a whitepaperat Mentor website for more details which also provides an example where FloTHERM was used to optimize component placement for a high-speed switch in telecom network.

Xilinx Boards Make a Great Christmas Gift!

Xilinx Boards Make a Great Christmas Gift!
by Luke Miller on 11-27-2014 at 7:00 pm
Categories: FPGA, Xilinx

Ok, first thing first, Happy Thanksgiving! For the Miller’s as I get older, it is new traditions as some old ones have passed on. Memories are great and new ones to make. So you know the great debate right?

These poor people working Thanksgiving to sell some tablet or smart phone to save a few bucks. Those that must work, my condolences to you and I promise I will not see you on Gray Thursday or Black Friday. May I make a recommendation for your gift giving list this year? Instead of getting the kids a box that plays video games, why not get them a box that allows them to design games and anything else they can imagine!

I know, it does not sound exciting nor exotic, and could even scare off a child with the aspect of an ‘educational’ gift. But if your child has any bent or inclination of things electrical or computer, a Xilinx FPGA and or Xilinx CPLD board would be a perfect gift. Now I also understand as a parent that you may not have the knowledge of even what an FPGA is or why a kid would want, or even how to use one. Let me explain a bit.

Remember the good old days, Radio Shack used to have those 101 Electronic Lab projects.

They had Lights, buzzers, solar cells, 7 Segment display, some radio circuitry and such. Now if you will, can you imagine literally 1000’s of these Radio Shack Labs into one circuit board. The possibilities are unlimited and will challenge even the smartest of children. I will give a list of recommended boards for kids at the end of this blog and you may find many used ones on Ebay for a fraction of the cost. Some things your child could learn all the yearlong?

· Digital Clock/Timer
· Sonar Range Finder
· Audio Recorder/Sound Effects
· Remote Control
· Internet Control
· Motion detection
· LCD/Video Display
· Alarm System
· Robots/Servo Control…

It will also create some real quality child parent time. It can be quite fun and funny, especially when electricity is involved. Once you get the Xilinx framework up and running it is a piece of cake to change in and out functions. You do not need to be a college graduate to play with Xilinx, all you need is some curiosity and a bit of gumption. Now I will not be getting my wife a Xilinx FPGA board, she’s an Altera woman. I know, we are supposed to be equally yoked! Can you imagine giving the wife an Altera FPGA, couch sleep is certain. So below is a list of a few affordable Christmas Xilinx boards to get your child into the best hobby and maybe career in the world. For the first board listed below, I made a GPS driven Nixie Tube Speedo for my 1953 Pickup Truck.

Basys™2 Spartan-3E FPGA Board
Basys™3 Artix-7 FPGA Board
CoolRunner-II CPLD Starter Board
ZYBO Zynq™-7000 Development Board

There are a ton of video’s, papers, code , groups and resources on the web… Your Child will Love a Xilinx Board for Christmas! What do I want for Christmas? I love neon signs, so dear Xilinx, would you please send me a real Xilinx neon sign? I’ve been good 😉

November 27, 2014

Rock for CASA, December 6th

Rock for CASA, December 6th
by Paul McLellan on 11-27-2014 at 7:00 am
Categories: Events

It is the holiday season so time to get together with your friends and colleagues in EDA, IP and semiconductor at the third annual event raising money for Court Appointed Special Advocates (CASA) (www.casaofsantacruz.org). This is the third event that Heart of Technology has worked with CASA. CASA has local organizations and in this case we are working with their Santa Cruz organization.

The event is on Saturday December 6th from noon to 5pm at Doc Auto in Santa Cruz, which is at 908 Ocean Street. There will be a big tent so that the event can take place rain or shine. As always there will be live music, food, drink, silent auctions and raffle drawings. It promises to be a fun afternoon. Cost is just $10 or donate a $10 gift card.

Of and if you are wondering why the event is taking place at an auto shop, there is an EDA connection. Doc Auto is owned by Ken Potts family. He worked for me at Compass way back when and currently is at Cadence.

Santa Cruz is economically very different from San Jose. The statewide median household income is $59,540. The median income for a household in San Jose was $77,000, which is well above median for a Santa Cruz household in the city was $50,605. Many households are having a difficult making it and families are suffering. CASA is about taking care of families going through difficult times. This is especially true around the holidays.

A little more about CASA: Children with a CASA Advocate are…

More stable while in foster care;
Receive more of the physical and emotional resources they need to heal;
Better able to succeed in school;
Less likely to return to the system.
Children with a CASA Advocate are more likely to grow into healthy adults who can break the cycle of abuse and neglect.

This holidays the focus for the event will be teenagers. Often the teenagers are left out. CASA will use proceeds to purchase gift cards for example. These gift cards are very useful by teenagers who want to fit in.

I will be there, hope to see you too.

Court Appointed Special Advocates of Santa Cruz County
As many as 600 local children each year live in the Santa Cruz County dependency system because of parental abuse or neglect. Each day they face uncertainty and trauma, their lives a sea of ever-changing professionals who –although well-meaning- are nonetheless strangers; police, social workers, foster parents, therapists, judges, lawyers and many others. This is where CASA steps in. For more than 200 of these children each year, one person is consistently there; a caring person whose focus is solely on them, a person whose reassuring presence does not change; the child’s volunteer CASA Advocate. Read more.

‘Tis the season for 4K UHD and HEVC

‘Tis the season for 4K UHD and HEVC
by Don Dingee on 11-26-2014 at 4:00 pm
Categories: Foundries, STMicroelectronics

4K UHD TVs were all dressed up at CES 2014 with no content to show. The good news for the 2014 holiday season is the industry has converged on one set of standards for display, interfacing, and encoding, so consumers should not be left marooned in an instant replay of the 3DTV hype-crash cycle. It may be a bit longer before everyone can see 4K, but there has been significant progress. Continue reading “‘Tis the season for 4K UHD and HEVC”

November 26, 2014June 14, 2019

Transistor-Level IC Design is Alive and Thriving

Transistor-Level IC Design is Alive and Thriving
by Daniel Payne on 11-26-2014 at 7:00 am
Categories: EDA, MunEDA

There’s much talk in EDA about High Level Synthesis (HLS), Transaction Level Modeling (TLM) and the Universal Verification Methodology (UVM), however there’s a lower-level of abstraction, the transistor-level, where high-speed digital cell libraries are created, analog circuits are crafted, and AMS designers tweak transistor sizes and choose circuit topologies in order to meet stringent specifications. At the transistor level the IC designers have many challenges, like:

Will my circuit be robust and work across all PVT conditions?
How does process variation effect the yield of my design?
Is my design optimized?
How do I port from 90 nm to 65 nm?
Does this analog topology work with FinFET processes?

One EDA company founded in 2001 has a focus on tools used for interactive, manual, semi- and fully automatic analysis, sizing, design centering and yield optimization of analog and mixed-signal circuits. Their annual user group meetingwas last week in Munich, and I attended to learn first-hand. The company is called MunEDA, pronounced moo-nee-dah.

An Example MOS Op Amp Circuit

The user group meeting started on Monday when Pierluigi Daglio from STMicroelectronics gave an overview of previous years, dating back to 2006. I first met Pierluigi back in 2010 when he was on a panel that I moderated at DACon the topic – Hot and SPICEy: Users Review Different Flavors of SPICE and FastSPICE.

Pierluigi Daglio, STMicroelectronics

Over the next two days we had 29 presentations, complete with Q&A to learn more about getting the best results out of transistor-level designs. Here’s a quick list of presentation titles:

ICScape – Accelerate Design Closure
MunEDA – Statistical Verification and Analysis Tools
SMIC – Process related yield debug and optimization of analog IP with MunEDA WiCKeD
Lantiq – Sign-off flow for RF design with WiCkeD in a 65nm Technology
Novatek – S&H Sample & Hold (ADC) Mismatch Analysis and Sizing using WiCkeD
IPGEN – New layout generation techniques for variation sensitive analog circuits
MunEDA – Reliability & Robustness Based Design Using WiCkeD
STMicroelectronics – I/O Design Optimization Flow for Reliability In Advanced CMOS Nodes
Infineon – Reliability Aware Design of Relaxation Oscillator in Advanced CMOS Technology Nodes with WiCkeD
STMicroelectronics – IOs circuit optimization activities to enhance productivity, circuit robustness and improve existing reliability flow
Sapienza University Rome– Digital standard cell noise margin optimization, also considering aging effects with MunEDA WiCkeD and
Synopsys MOSRA tools (MANON)
Infineon – Safeguarding Hold time Margin for Internal Scan Chain in Multibit-Register Standard cells
Altera – Distributed Memory Design (MLAB) – design optimization and worst case analysis on memory cells, data paths and write pulse
generators with WiCkeD
MunEDA – Advances in Circuit Migration
HLMC – 55nm to 40nm Bandgap porting with SPT & High gain Amp optimization with MunEDA WiCkeD
Fraunhofer – Silicon Proof of the Intelligent Analog IP Design Flow using WiCkeD
MunEDA – Full-Custom Low Power Design Methodology with MunEDA WiCkeD
MunEDA – Ultra High Sigma (6+ Sigma) Analysis – High Sigma is not enough
STMicroelectronics – Corner Verification and Design Optimization in Smart Power & Non-Volatile Memory Technologies
University Frankfurt – FEATS – explorative automated topology synthesis with WiCkeD
Fraunhofer – Advanced measures for OpAmp optimization with WiCkeD
STMicroelectronics – Design validation and development of RF macrocells
ARP Microsystems – High-Voltage Automotive Analog IP Development for SOC using WiCkeD tools
Altera – Full-custom and Semi-custom Clock Trees Optimization using MunEDA WiCkeD – Clock Skew Matching, Clock Insertion Delay
and Duty-Cycle
STMicroelectronics – SMAC – Smart components and Smart Systems integration

Foundry partners included: STMicroelectronics, SMIC and HLMC. I had heard about the first two foundries, but HLMC located in Shanghai was new to me, and they offer 90 nm, 65 nm and 45 nm processes into markets like: standard CMOS, AMS, RF CMOS and NOR Flash.

EDA partners were: ICScape, IPGen. We’ve blogged about ICScape on SemiWiki last year, and then IPGen is a small startup with IC layout generation technology plus services.

Reimund Wittman, CTO, IPGEN

Each of the presentations were made using PowerPoint, and then attendees had a hard-copy handout which will be followed up with an online version with video archives for registered users. We had plenty of time to network and socialize during coffee breaks, lunch and a fabulous dinner on Monday night at the Agustiner Brewery.

Agustiner Brewery

The most creative presentation had to be from the University Frankfurt, where they had an analog synthesis framework that included expert knowledge to produce a wide variety of circuit topologies. They connected their framework to the circuit sizing optimization in the MunEDA WiCkeD tool.

Markus Meissner, University Frankfurt

On the fast digital side was a paper from Altera about how they optimized the transistor sizes for clock trees used inside of their latest FPGA designs.

B.Y. Ng, Altera

Overall I learned that transistor-level IC design is alive and thriving, thanks to the University curriculum on AMS design techniques, commercial practice of circuit design, demand from foundries for libraries, and finally EDA tools that enable analysis and optimization.