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January 29, 2015

Apple’s Implications for Semiconductor

Apple’s Implications for Semiconductor
by Robert Maire on 01-29-2015 at 11:00 am
Categories: Foundries

Apple’s iPhone 6 alone represents at least 50K wafer starts/month plus the iPad (A8X). What could the Iphone 6S/7 & A9 mean? What about the iWatch? Apple is the technology and volume driver of the semiconductor industry so lets take a look at the broader implications.

If we do the math the A8 is 89mm2 and 8.47 X 10.5mm. Using a die calculator that means that roughly 675 die can be squeezed onto a 12 inch wafer. If we assume a 75% yield we get 500 good die per wafer (I like to use round numbers). If we take 74.5 million iPhones over three months that’s about 25 million a month (or 34K an hour…but who’s counting?) Divided by 500 per wafer and you get 50K wafer starts a month, give or take, depending on yield etc… That sucks up a significant chunk of a fab and doesn’t leave a lot of room for other customers.

The A9 could consume more than 100k wafer starts…
If we stretch and presume that Apple forces Samsung into eating the yield loss and goes whole hog at 14nm the wafer starts could get excessively high. We could assume a similar die size A8 though we would bet that the A9 will be larger with more functionality (SoC integration).

If we presume the same roughly 675 potential die on a wafer then apply a guesstimate of 20% yields we would get 135 good die per wafer, if the die size were larger we might only get 100 good die per wafer. If we assume that Samsung can get its act together on 14nm FinFET and manages to get 40% yields then that would be 270 good die at a similar die size.

If we assume that Apple continues to run at 25M phones a month we could see 100K wafer starts a month of capacity dedicated to the A9 (unless yields get better faster). This again, brings us back to our recent newsletter questioning whether the A9 will be 14nm FinFET or not.

The iPad Air 2 – A8X is no slouch either..
The A8x in the iPad Air 2 has 3 cores and 8 GPUs compared to the A8 which is dual core with 4 GPUs. The A8 is small at 89mm2 versus the 128mm2 A8x. The larger die size is due to doubling the number of GPUs and adding a third core. If we guess that each wafer could produce up to 450 A8x parts , using a yield of 75% is about 340 good die per wafer. Apple just sold a bit over 21M iPads in the quarter (7M per month). If we presume that 4M of those will be equipped with the A8X then that’s at least another 12K wafer starts/month.

The iWatch “S1” SOC….
Though not likely to be a big seller at first, we think the iWatch will be a constant climber unlike the DOA Google Glass. Likely to start off slow then ride the coattails of the iPhone and iPad so probably not a lot of wafer starts for the iWatch. We have already heard more buzz about the second generation iWatch even before the first generation is out. My guess would be the first gen will be an early adopter/ learning tool type of device, followed by a more realistic and refined gen2.

Korea, Austin and maybe Malta?
Looking at the number of wafer starts that Apple will be driving, combined with increasing sales then multiplied by crappy yields, we are talking about Apple dominating a number of fabs. This could keep Samsung’s logic fabs in both Korea and Austin very busy as well as GloFo (if they get past the delay).

Then add in memory and support chips…
All we have talked about so far are the main SOC’s for Apple. You have to add in all the memory, both NAND and DRAM as well as all the other many support chips which are not insignificant in terms of fab capacity. Apple has gone to 2GB of DRAM for the iPAD Air 2 after disappointing people with on 1GB on the iPhone 6. Upgrading DRAM on the next iPhone is likely and average NAND installed continues to grow. All in all, we are talking about a lot of fab capacity being driven by Apple and its huge success.

Longer term looks good despite near term slow down….
Despite the fact that the industry is hitting a bit of a soft spot on 14nm foundry and logic roll out, the long term demand for square inches of silicon remains quite good. We see no reason for Apple to slow even when looking at the currency forex headwinds. International sales were 65% and that was with an overly strong dollar. The iPad Pro and the iWatch will be a nice chaser to the amazing Q4 sales of iPhones which blew past all expectations. Luckily the mobile and IOT markets are growing much, much faster than the Wintel Duopoly is fading. Intel is also lucky to have the “cloud” to sell processors to.

Apple driving the bus…..
Apple is firmly in command at the drivers seat of the tech industry bus. Semiconductors, software, servers, IOT, the cloud, financial, media even Google and android are all along for a great ride on our way to over 100M devices a quarter and beyond. Its no longer the VW Microbus that Steve Jobs sold to fund the start of Apple but somewhere he is smiling at his vastly upgraded new wheels.

Robert Maire
Semiconductor Advisors LLC

January 29, 2015January 13, 2022

NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers

NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers
by Paul McLellan on 01-29-2015 at 7:00 am
Categories: IoT, IP, Sonics

At the end of last year, I moderated a Sonics webinar to introduce the concept of a network-on-chip or NoC. It was called NoC 101 and the replay is still available here.

Well it is a new year and time for chapter 2. I will be moderating a webinar next Wednesday February 4th at 10am pacific time. Once again the webinar itself will be delivered by Drew Wingard who is the CTO of Sonics. It is entitled NoC 102: Using SonicsGN to Address Low Power Requirements From IoT to Servers.

The performance and power requirements are very different for IoT devices such as wearables, and big server SoC. But it turns out that the same underlying technology, the NoC, can be used in both cases to integrate the large numbers of IP blocks that might be involved, handle the power domains and often the powering up and down of individual blocks of IP.

Modern mobile devices are increasingly pushed to provide greater functionality at lower power. Improved architectures provide the most effective approach to minimizing power by dividing the SoC into a multitude of power and clock domains, ensuring that each domain operates at the lowest power level to satisfy the application requirements. The on-chip network increasingly plays a critical role in both supporting larger numbers of domains and enabling rapid, safe power-state transitions. The arrival of ultra low power devices (and ultra low power processes) is only going to make this more challenging.

Furthermore SoCs utilizing multicore processors often require very high bandwidth communication capabilities between processors, between processors and accelerators, and between these components and a main memory store. The design of these complex devices presents many challenges for the SoC designer. One of those challenges is power management. Power consumption is important for all categories of Multicore SoCs, from battery operated devices where power savings can lead to smaller batteries and/or longer battery life, to line powered devices where power savings are important for cooling reasons as well as packaging and component costs. Even in high performance data centers, electricity and cooling costs can significantly exceed equipment costs.

The Network-on-Chip (NoC) providing on-chip communication plays an important role in the power management strategy of a multicore SoC. This webinar will address many of the techniques used to manage power consumption. These include fine-grain and course-grain clock gating techniques as well as voltage scaling and power switching with auto-wakeup capabilities. Building these techniques into the NoC simplifies the task of implementing an efficient power management strategy at the SoC level.

You can register for the webinar here.

Related Blog

January 28, 2015

Translating Intel

Translating Intel
by Scotten Jones on 01-28-2015 at 10:00 pm
Categories: Foundries

Some of Intel’s technology posts make some pretty specific statements and I have seen a number of posts where people seem to have misinterpreted what Intel was actually saying.

Multi Patterning
I have seen a lot of confusion on this one with some people saying Intel didn’t use multi patterning at 22nm and others saying Intel used multi patterning at 14nm for the first time. Lets start with where I think the root of this problem began.

Continue reading “Translating Intel”

January 28, 2015

Qualcomm Earnings Call

Qualcomm Earnings Call
by Paul McLellan on 01-28-2015 at 9:35 pm
Categories: Mobile

Qualcomm had their earnings call today. There has been a lot of discussion about their business going forward and they lowered guidance. They didn’t say explicitly why but in the usual Kabuik theater of these things this is what they did say:While our outlook for the first half of the fiscal year is ahead of our prior expectations, our QCT forecast for the second half of the fiscal year has been reduced due to a number of factors. First, we are currently seeing a shift in share among OEMs at the premium tier, which has reduced the near term addressable opportunity for our Snapdragon processors and has skewed our product mix towards more modem chipsets in this tier. Second, we now expect that our Snapdragon 810 processor will not be in the upcoming design cycle of a large customer’s flagship device, impacting our outlook for both volume and content in that device.
Translation. Apple’s iPhone 6 is doing much better than expected but Qualcomm only supply the modem and Apple designs their own application processors. So that reduces their revenue possibilities. Also, Samsung look like they will use their own Exynos processor rather than Snapdragon 810. Since Samsung is far and away the volume leader (twice Apple) this is a big loss (although they have a big range of phones at different price points and this chip would not have been in all of them). He continued: And thirdly, although we had a very strong competitive position exiting fiscal 2014, we are seeing heightened competition in China at the mid and high tiers. We are continuing to gain share year-over-year with OEMs based in China, but not at the pace we had previously expected. This is in part due to some product challenges with one of our chips in meeting some of the more demanding design points of those tiers. This has provided an opening to competitors who are being very aggressive in order to establish a position in the marketplace, resulting in more pricing pressure than previously expected. Translation: actually just a guess. there is some truth to the overheating problems that are part of the reason Samsung switched away. It looks like some other Chinese manufacturers are holding back, or not ramping, or perhaps switching to Taiwanese MediaTek. They are in the Xiaomi Pro Note which should ship in high volume in China based on past experience. But in the Q&A they pretty much denied it: On the 810, let me be very clear. The device is working the way that we expected it work and we have design traction that reflects that. If you look at the number of designs, it’s over 60. It’s essentially won all the premium designs across multiple ecosystems in China, Windows Mobile, as well as Android. So we’re quite pleased with how that is performing. There is a concern. As you mentioned it’s related to one OEM, and I don’t think you should extend that to imply that something has changed fundamentally between us and that OEM. They talked a bit about the problems with the NDRC (Chinese antitrust regulator). Qualcomm invented CDMA pretty much single handedly and have always had an aggressive royalty and patent license program. I negotiated a deal with them in the 1990s and we ended up walking before they got desperate a year later and we eventually got a chip license. NDRC seems to think Qualcomm are abusing their monopoly position on technology and demanding excessive licensing. But who is to say? NDRC has already said they expect the case to be settled soon. Qualcomm also said on the call that many of their Chinese licensees are under-reporting and so they have increased their auditing. SeekingAlpha transcript is here. It is pretty long I have to warn you.

January 28, 2015

Tabula Closes its Doors

Tabula Closes its Doors
by Paul McLellan on 01-28-2015 at 3:55 pm
Categories: FPGA

I heard a rumor at lunchtime that Tabula was closing its doors. A friend of mine talked to a couple of employees and it is true. They have to be given 2 months notice apparently so the doors don’t actually close until March 24th. I thought they had raised $150M but Wikipedia (not always reliable of course) says $215M. They were one of Intel’s first foundry customers (at 22nm) and Intel capital provided some of that money. It was founded in 2003 by Steve Teig who had been CTO of Cadence. I saw a presentation about the technology at DAC organized by CEDA a couple of years ago.

Tabula had a unique Spacetime 3D FPGA technology but it seemed very hard to master. I heard a couple of years ago that they had needed to do a complete redesign or maybe even two. But the real weakness, I suspect, was the complexity of the software required to program it. The technology is supposed to give a two process node advantage over traditional FPGA approaches.

As the Tabula website puts it:A Spacetime device reconfigures on the fly at multi-GHz rates executing each portion of a design in an automatically defined sequence of steps. Manufactured using a standard CMOS process, Spacetime uses this ultra-rapid reconfiguration to make Time a third dimension. This results in a 3D device with multiple layers or “folds” in which computation and signal transmission can occur. Each fold performs a portion of the desired function and stores the result in place. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function. By rapidly reconfiguring to execute different portions of each function, a 3D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an FPGA, with its inherently 2D architecture.

Obviously taking a standard synthesis flow and making it dynamically continuously reprogram itself at very high speeds sounds like it would be very complex. They have software products to do this, primarily a synthesis tool called Stylus Compiler.

I suspect that the real problem was the red queen problem, that it takes all the running you can do to stay in the same place. By the time they got things working at 22nm they need to be on the node soon, they needed an IP portfolio, I’ve heard the tools were buggy at least a couple of years ago.

RIP Tabula.

January 28, 2015

Opto-Electronics to Take Care of Data Explosion

Opto-Electronics to Take Care of Data Explosion
by Pawan Fangaria on 01-28-2015 at 11:30 am
Categories: Foundries, General, Intel Foundry, Silicon Photonics

As we come nearer to an intelligent IoT world, one of the major concerns we talk every day is about data explosion, its storage, and access and so on. In the beginning of the year, I had blogged about some facts that indicated successful emergence of IoT in very near future. My faith gets further strengthened when I envision the semiconductor world going through another revolution with opto-electronic chips. In the near future, we can see Intel’s photonics technology on top of silicon that can enable high-speed, efficient and reliable data centers without power, heating or space problems in storing and handling Big Data.A LASER (Light Amplification through Simulated Emission of Radiation) is based on Raman Effect, invented by Sir C. V. Raman, an Indian physicist who received Nobel Prize for this discovery in 1930. LASER has been successful in glass fiber. In glass fiber, after travelling several kilometres, the laser beam acquires enough energy to cause a significant amplification of the data signal. Intel’s silicon photonicstechnology is actually a LASER in silicon. The Raman Effect is more than 10000 times stronger in silicon than in glass fiber. In silicon, the distance required is only in centimetres. Also, silicon is most cost effective and requires existing fabrication techniques. Since silicon cannot emit laser light, a waveguide (conduit for light in silicon) is etched into a silicon wafer.The silicon waveguide encountered another problem called ‘two-photon absorption’. In this, two photons arrive at an atom at the same time and the combined energy is enough to free an electron from an atom. At high power densities, the rate of creation of free electrons exceeds the rate of their re-combination with the crystal lattice. The free electrons then start absorbing the light passing through the silicon waveguide, thus diminishing the power of signals. To overcome this problem, the scientists at Intel Photonics Technology Lab inserted a diode-like PIN device in the wave guide that removed the free electrons to produce continuous amplification. Raman Effect was created to amplify the light as it bounced between two mirrors coated on the ends of the waveguide, thus producing a continuous laser beam at a new wavelength. This formed the breakthrough silicon laser. Look for more details in a whitepaper at Intel Photonics Lab website.Silicon laser alone was not enough, other components such as high-speed silicon modulators and silicon photo-detectors were developed. A chip can have multiple hybrid silicon lasers at different wavelengths and each modulated at say 50 Gbits/s. A silicon multiplexer can then combine all signals into a single optical fiber. At the other end of the fiber, another chip can have detectors to convert the optical signal from each laser back into electronic signal. At IDF 2013, Dr. Mario Paniccia, Director of Intel Photonics Technology Lab demonstrated a transceiver based on photonics technology, operating at 100 Gbits/s. Justin Rattner, CTO of Intel at that time, said that Intel has fully automated test technology for such photonic wafers that combines electrical, optical or RF test. It uses microscopic lenses to read optical signals.Fujitsuworked with Intel to demonstrate Optical PCI Express (OPCIe) server, which was enabled by Intel’s silicon photonics technology. It solves power and heat density problems which occur in Rack-based servers due to space and power constraints. Signals over optical fibers can go much longer compared to copper signals. Look for details about this prototype at Intel website here.Looking at these working devices, it’s certain that silicon chips will have another revolution to add optics into them. I am calling these as opto-electronic chips that can enable very high-speed, low latency connections and high storage in the cloud as demanded by the upcoming semiconductor market in the near future. I can envision this technology in main stream chip production sooner than later. Does it ask for another Nobel Prize for Intel scientists? In my view it could, provided it fulfils the larger need of high-speed computing, storage and access without too many issues as seen in copper wires. The cost must be affordable because silicon is always low cost compared to other materials for such use. Comments welcome!

January 28, 2015

Altera Back to TSMC at 10nm? Xilinx Staying There

Altera Back to TSMC at 10nm? Xilinx Staying There
by Paul McLellan on 01-28-2015 at 7:00 am
Categories: FinFET, FPGA, Xilinx

Xilinx announced their quarterly results last week. They slightly missed their number due mainly to a decline in wireless sales. Of course Xilinx parts don’t go in the smartphones since the cost and power are too high, but they are very heavily used in basestation, backhaul etc especially in China. Xilinx’s business in China has been historically limited by a slower buildout to a shortage of parts (not the Xilinx parts but power amplifiers). That problem seems to have gone away and their China business is on track and the weakness is in the rest of the world.

As always here at semiwiki it is interesting to use the FPGA market to get insight into the foundry roadmaps.

As Moshe said on the call:We also achieved several important milestones for our 20-nanometer portfolio. Our Kintex UltraScale devices became the industry’s first 20-nanometer FPGAs to move into volume production. Based on customer feedback, we continue to believe that we have an estimated one-year lead over the competition. This technology leadership is complemented by our Virtex UltraScale family, which is the industry’s ASIC class 20-nanometer high-end product offering. It’s a very high-end of this family, we began shipping the industry’s largest FPGA which delivers over 4x of the capacity of any competitive devices.

With regards to 16nm, they are a couple of months behind schedule. The problem is on the design end at Xilinx themselves and doesn’t appear to be due to any changes on the TSMC side. Moshe said that they should tape out in May:Okay. So there are no issues with TSMC, they have had numerous tape outs already, they are giving us full support. The design whenever you encounter a new generation of product tends to unearth problems that you did not anticipate and as a result the closing of all of these issues is taking a little longer plus the challenges related to design for FinFET transistors are more significant. So it’s not a TSMC challenge or issue at all, it’s just our ability to finish the design with their support. After if you look at our business typically what sort of happens is tape it out, you get it back after a few months, you go through a lengthy evaluation cycle and then you move it into production at which point in time it takes two to three years until it reaches high volume production.

Meanwhile Altera also had an earnings call. As you probably know they use TSMC for 20nm and above but switched to Intel 14nm (which is what TSMC calls 16nm for Chinese reasons). They are seeing a lot of the same slight weakness in end-user markets. John Daane, the CEO, said that they were also a couple of months late taping out in 14nm:Let me start with 14-nanometer. Our original schedule was to tape-out in first calendar quarter, we’re running a couple of months late to that and are actively working to pull that in but worst case, we will sample this fall so we are still definitely in this year.

He also reckons that in the Intel process which has tighter pitches than TSMC that they will get a 25% area savings which is less than the original thought of 35%. But the bombshell was about 10nm:Question: You talked about 14-nanometer, have you guys made any decision on your foundry choice for 10-nanometer?
We have not made that decision. We have told both, Intel and TSMC, who are working with on the technology that will likely make a decision before the end of the first calendar quarter.

So Altera could go back to TSMC for 10nm. Of course this might all be a negotiating strategy for better wafer prices but switching to Intel for just one process generation would be unusual.

Seeking Alpha transcripts: Xilinxand Altera

There is a Semiwiki forum discussion on this here.

January 28, 2015

Qualcomm versus Samsung?

Qualcomm versus Samsung?
by Daniel Nenni on 01-28-2015 at 3:00 am
Categories: Foundries, Mobile

There is an interesting reality show playing in the media featuring Qualcomm and Samsung with supporting actors TSMC, LG, Xaomi, and Apple. As I’m sure we all have read, Samsung is losing massive amounts of money on mobile which was once a very profitable business unit. Let’s take a look at the current landscape and some of the recent headlines to try and make sense of this thing. Sound like fun?

According to IDC the worldwide smartphone market hit close to 1.3 billion units in 2014. According to the world population clock there are more than 7.2 billion people on planet Earth with a net gain of one person every 16 seconds. Let’s also put the average smartphone replacement cycle at every two years. Smartphones are now an integral part of our quality of life so the market for the SoCs that power smartphones will continue to grow rapidly for many years to come, absolutely.

[TABLE] cellspacing=”3″
|-
| 1. China
| 1,361,512,535
| 6. Pakistan
| 199,085,847
|-
| 2. India
| 1,251,695,584
| 7. Nigeria
| 181,562,056
|-
| 3. United States
| 321,362,789
| 8. Bangladesh
| 168,957,745
|-
| 4. Indonesia
| 255,993,674
| 9. Russia
| 142,423,773
|-
| 5. Brazil
| 204,259,812
| 10. Japan
| 126,919,659
|-

Samsung still holds the number one position in the smartphone market but for how much longer? Samsung mobile posted negative numbers in 2014 and this year looks even more challenging. Apple is number two and gaining market share on the success of the iPhone6 and 6+. Xiaomi is now number three thanks to the China market and is rapidly expanding into India and other densely populated countries excluding the United States. Lenovo (including Motorola Mobility) is a strong number four and LG is fifth.

In regards to the SoCs inside these phones, QCOM, MediaTek, and Apple control the market with 80-90% market share depending on whom you believe. In 2014 the majority of these SoCs were 28nm from both TSMC (QCOM and MDTK) and Samsung (Apple iPhone5). At the end of last year Apple started shipping TSMC 20nm (iPhone6) and in 2015 SoCs will be a mix of 28nm, 20nm, and 14nm.

Having worked with Samsung in the past I can tell you they are a fierce competitor that knows no bounds so I find it highly unlikely that they will abandon the mobile market. I also find it highly unlikely that they will participate in a market that they cannot win so what is Samsung to do?

[LIST=1]

Pressure Qualcomm by rumoring that the Snapdragon 810 (TSMC 20nm) has heating problems? I spoke with friends inside QCOM when the story first broke and was told it would be proven false.While Samsung blamed the delay of the Galaxy S6 on QCOM, LG and Xiaomi released phones using the identical SoC with no reported problems.

As I mentioned before QCOM will use Samsung’s 14nm process but now I must ask: Is there more to this story? Will the QCOM 14nm SoCs be made available to all smartphone vendors or just Samsung? QCOM will also use TSMC’s 16nm FF+ so maybe this is the real reason for the split?

Have QCOM take over Exynos and develop the chips for Samsung? This would be my recommendation.

Bottom line: I see the foundry business as playing a key role in the competitive battle amongst the mobile vendors and the SoC makers may be forced to choose sides.

January 27, 2015March 22, 2022

DNA Sequencing Eyes SoCs for Stability and Scale

DNA Sequencing Eyes SoCs for Stability and Scale
by Majeed Ahmad on 01-27-2015 at 9:00 pm
Categories: Cliosoft, EDA

DNA sequencing — which provides vital information on genetics study, forensics, diagnostics and therapies — has been an exclusive territory of high-end research labs with millions of dollars to spend because of the expensive chemical and optical equipment needed for research. That is changing, thanks to complex integrated circuits, a.k.a. systems-on-chip (SoC), which are overcoming cost and technical hurdles to bring the price of human DNA sequencing to US$ 1,000 or less with the eventual goal of reaching US$ 100.

Although DNA sequencing technology based on semiconductor products is still in an embryonic stage, single-chip solutions clearly seem its best hope. Take DNA Electronics (DNAe), for instance. The London-based (UK) firm has embedded the whole diagnostic process on a single chip to sidestep the need for measuring optical signals or using lasers and microscopes. The lab-on-a-chip — as the company founder Christofer Toumazou likes to call it — is a fusion of semiconductors and sensors that uses very small amounts of chemicals to conduct tests on the spot.

DNAe’s lab-on-a-chip that can be inserted into a USB stick

Toumazou claims that this single-chip device — built around the company’s Genalysis platform — can be inserted into a USB stick and that it will provide results that are viewable on a computer within 20 minutes. “Genalysis can perform both PCR (for speed) and sequencing (for content) on the same chip in the same analysis, to arrive at a fast, accurate and informative diagnosis.”

According to the European Patent Office data, by 2016, the DNA sequencing market is expected to be worth US$ 6.6 billion and will grow by 17.5 percent annually. But this era of personalized medicine will require highly complex SoCs and ultra high-tech semiconductor tools in order to turn the chemical information of the DNA into a change in the electrical signal.

How it Works

DNA sequencing determines the order of nucleotides (building blocks of DNA) in a DNA strand, which provides scientists valuable information and serves as the basis for diagnosis of diseases, detection of genetic predispositions to diseases, etc.

In all living organisms, a hydrogen ion is released when DNA strands are extended by a nucleotide, the individual chemical bases of the DNA (known by their abbreviated letters of A, C, T or G). The game-changing technology of DNA sequencing requires signals that are sensitive enough to detect tiny amounts of DNA (nanomolar concentrations). When a signal current is passed through the nanopore (a very small hole created in synthetic materials like silicon), it causes a spike in the current unique to each chemical base (A, C, T or G) within the DNA molecule.

The human DNA set or genome is already mapped, and the order of genetic mutations is known; so a pre-set sequence of nucleotides can be designed that matches genetically mutated ones. Once the target matches, it releases many hydrogen ions, which in turn is detected by the chip. The DNA sequencing is a matrix of hundreds of tiny wells, each well containing a fragment of the subject DNA.

The crossroads of biology and physics is going to be a challenge for the DNA chip developers in their bid to sequence single DNA molecules. But they are steadily overcoming these challenges related to signal accuracy and stability through innovative design and manufacturing techniques and a variety of SoC tools. That’s partly because there is an increased use of semiconductor technology in non-traditional markets like biotechnology.

For instance, Genia Technologies — acquired by Swiss drug giant Roche in June 2014 — is developing a nanopore sequencing technique that is based on a mix of SoCs and NanoTag chemistry. Genia’s NanoTag sequencing technique, developed in collaboration with Columbia University and Harvard University, uses a DNA replication enzyme to sequence a template strand with single-base precision as base-specific engineered tags cleaved by the enzyme are captured by the nanopore.

Schematic of a single molecule DNA sequencing by a nanopore with phosphate-tagged nucleotides

Genia’s SoC-based solution bypasses specialized, expensive optical sensors while detecting changes in electrical current through chips that aim to be as inexpensive as the ones found in mobile phones, PCs and other consumer electronic products.

The GENIUS system of GenapSys marks a shift from optics to electronics

SoC tools to the rescue

GenapSys Inc., the Redwood City, California, based chipmaker that provides DNA sequencing solutions, has been, like Genia Technologies and DNAe, using SoC-centric data management solutions such as ClioSoft’s SOS for handling analog, digital and firmware parts of its GENIUS sequencing chip. ClioSoft’s SOS data and IP management platform is a hardware-centric system that streamlines design flows and helps design teams collaborate more efficiently to ensure project timelines are met.

Like many SoC device makers, GenapSys doesn’t do all of its development at a single site, but it hosts all the data on a single server. “A lot of ClioSoft technology is tightly integrated into Cadence’s Virtuoso custom IC flow, so it’s not necessary to spend a lot of time interfacing directly with ClioSoft tools,” said Hamid Rategh, VP of engineering at GenapSys. “Like many SoC designs, the GENIUS sequencing chips of GenapSys use Virtuoso’s analog design environment.”

ClioSoft SOS is closely coupled up with EDA tools and syncs-up analog, digital and firmware parts of an SoC

Rategh added that ClioSoft links the whole work area, and that makes a big difference to the amount of disk space required. “You would think this would be less of a problem, with disks continuing to get cheaper, but management overhead for backups is still an issue.”

The GenapSys example shows that tools like Cadence Virtuoso coupled with ClioSoft’s SOS design management platform can bring necessary impetus to the DNA sequencing SoCs in their bid to bring stability and scaling to semiconductor-based solutions and eventually to bring down the costs of next-generation DNA sequencing technology to affordable levels.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

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January 27, 2015

Xilinx ships the VU440 and its 4M logic cells

Xilinx ships the VU440 and its 4M logic cells
by Don Dingee on 01-27-2015 at 8:00 pm
Categories: FPGA, Xilinx

Xilinx has delivered not only “the biggest FPGA on the planet”, but what it claims is currently the world’s largest integrated circuit: the Virtex UltraScale VU440, with 19 billion transistors fabbed in TSMC 20nm. The list of first customers to receive parts says a lot about the state of SoC design today, and the vital role FPGA-based prototyping and hardware-aware synthesis plays.

Fabs love massive FPGAs to prove out sophisticated process nodes. Around the periphery, there is certainly some magic with high-speed SERDES transceivers and other interfaces. The interior is where scale lives. Laying down a sea of equally sized logic cells in an interconnect fabric is ideal territory for fabs to show their process can maintain planar consistency across space and environmental variables.

The VU440 has 4,432,680 of those logic cells, along with 88.6Mb of block RAM, 1404 single-ended HP and 52 single-ended HR I/Os, three 100G Ethernet ports, and 48 GTH 16.3 Gbs transceivers among other features. Its package is a marvel unto itself: a 55x55mm flip chip BGA with 2892 pins, with 3D techniques including stacked silicon and 600,000 micro bumps. Getting that all in a part, and getting that part reliably attached to any board, is just plain amazing.

What does one do with something this big? Xilinx cites some top-of-pyramid applications: digital array radar, LTE-A wireless, 8K Ultra HD broadcast video, and 1Tb/sec optical transport networks. Performance is welcome, however not all of these applications need this many logic cells. Currently, six smaller UltraScale parts with similar features fill those requirements just fine. Single board computing vendors, who used to be the prove-out platform for large FPGAs, are probably going to be content at smaller capacities and lower price points.

Where capacity still can outstrip FPGA state-of-the-art is SoC design. 4M logic cells translates to roughly 50M ASIC gates. This fits a lot of things. In an introductory video, Xilinx shows just such an example: a Xilinx AFX board with a single VU440 holding a cluster of 10 ARM Cortex-A9 cores. It is filled to the brim: 94% of CLBs, and 77% of LUTs are used. The ten CPU cores are running at 50 MHz. While a demo system, it illustrates the potential.

Among other improvements, Xilinx spent a lot of time completely revising the clocking scheme in UltraScale, making it more ASIC-like with respect to how slice boundaries are dealt with. They also improved routing the routing architecture and logic cell packing. Even with these improvements and the massive resources of the VU440, current SoC designs are often far bigger than 50M gates, and RTL has to be partitioned across multiple FPGAs.

Synopsys was among the first to receive VU440 parts, and is working on an even bigger version of the HAPS prototyping platform. As we explored in a recent post on prototyping the Imagination PowerVR Series6XT, having a big enough gate pile to hold logical partitions of a design is the start. Synopsys ProtoCompiler performs hardware-aware synthesis, using constraints defining FPGA and board-level resources such as interconnect and multiplexing. When they get their arms around the UltraScale architecture, and leverage the VU440 capability fully in synthesis, designers will have incredible capability.

Of course, there is still the old school of “manual” tool-assisted partitioning. Some designs are cleanly separable. Capability of Xilinx Vivado Design Suite for tasks like partitioning continues to improve. Some designers like the control, and the challenge. Another FPGA-based prototyping system vendor, The Dini Group, also has VU440 parts in house. In an homage to just how far we have come in being able to cut large and unruly ASIC designs into manageable pieces, they have proudly dubbed their newest prototyping engine as “Godzilla’s Butcher on Steroids.”

For more information on the VU440, and to launch the full video, see the Xilinx press release:

Xilinx Delivers the Industry’s First 4M Logic Cell Device, Offering >50M Equivalent ASIC Gates and 4X More Capacity than Competitive Alternatives

Scalability, as the name implies, is central to the Xilinx UltraScale strategy. The shipment of the VU440 is a stunning accomplishment, one likely to be unmatched for a while. We seem to have arrived at a point where the practice of FPGA-based prototyping is ready for prime time. The costs of committing to silicon without complete hardware and software co-verification, and rapid changes leading to retesting, are too big to risk. The capacity of the VU440 applied to FPGA-based prototyping should bring in more developers.