The maiden voyage of NASA’s Orion spacecraft brought a raft of articles about how the flight computer inside is “no smarter than your phone,” running on wheezing IBM PowerPC 750FX processors. NASA’s deputy manager for Orion avionics, Matt Lemke, admits the configuration is already obsolete – at least in commercial terms. Continue reading “Synthesizing rad-tolerant RTL for FPGAs”
Whenever a market matures, either it gets plagued by substitutes or it looks for complementary products or technologies which can fuel its maturation curve into further growth opportunities. While PCs and Notebooks got substituted by smartphones, there is no other device in foresight to substitute smartphones. The reason is smartphones have inherited many functions from other devices including communication, computing and consumer applications. Communication and computing being two powerful functions ‘on the go’ have provided huge boost to smartphones in the hands of consumer which has attracted other applications to get into smartphones. Now smartphones are ready to further displace other devices such as remote controls for TVs, ACs, and Cars and so on. People are tired of having so many remote control devices; they would prefer to use just their smartphones from anywhere they like!
Guess, what will drive smartphones to take control of their own destiny – it’s IoT. IoT will enable smartphones to control all other devices in consumer, home, personal, security, automotive, healthcare and other spaces.
IC Insights is correctly predicting cellphones to be the largest driver for IC sales; and wireless and IoT to exhibit the fastest growth for next five years.
In its reportfor 2013-2018, IC Insights predicts strongest IC sales growth in subsystems for IoT and wireless networks; while IoT is expected to grow at CAGR of 22.3%, wireless ICs can grow at CAGR of 19.7%. Similarly, the systems sales associated with IoT are expected to rise at the fastest CAGR of 21.1% (in another graph). And cellphone ICs will continue to top the IC sales share at $70.7B.
This foresighted trend is being reflected in the strategies of leading semiconductor companies. Last week, I was studying about Samsung’s plans after major fall in their profit from phone business. Samsung is putting major emphasis on IoT which will stitch together most of their other businesses and generate benefits across their product lines – Smartphones, TVs, computers, watches, cameras, fridges, washers and dryers and so on.
Lee Jae Yong of Samsung has established collaboration with Intelto develop and strengthen its own operating system, Tizen; joined Thread Group, led by Google’s Nest Labsto build home automation; and signed global patent licensing agreement with Ciscoto strengthen connected devices systems. They acquired SmartThings who specializes in developing mobile applications that remotely control household devices.
Samsung has massive plans to setup chip manufacturing for wearable and connected devices. They have already setup a large Innovation Museum (in a five storied, glass walled building) that signifies smart living and inspiring. There are booths to demonstrate connected life in hotels, shopping malls, offices, living rooms in homes, airplanes and so on. And everything is controlled through your Smartphone; for example, you can check-in into the hotel by pressing a key on your Smartphone without waiting in the queue, warm your oven or clean your room before coming home, check all security and condition of your home even after leaving from there, all from your Smartphone.
Samsung is not alone; Qualcommhas low power wi-fi platform that connects major home appliances to the network; IntelQuark plans SoCs that are smaller and low power than atom to support IoT; Applehas HomeKit and HealthKit; Google Nest provides thermostats and smoke detectors that can be managed through smartphones. GEforays into industrial internet with portfolio including equipments, internet-linked sensors and software to monitor and control performance. Cisco provides network convergence system that enables fabric suitable for IoT.
Next era will be for IoT enabled smartphones; IoT will drive Smartphone market into a new growth trajectory and retain the fortunes of these phone and wireless companies as well as those which enable smart things to be done through IoT and smartphones. Comments welcome!
The Internet of Things (IoT) is apparently the next big thing, but it tends to appear in different ways to different people. To some it’s all about connectivity of the web of devices and to other it’s synonymous with sensors and wearable devices. And the scope of IoT is expanding by the day—to smart lighting, smart thermostats, smart homes, and smart buildings. Even cameras and cars are increasingly being seen under the IoT fold.
To understand the larger concept, and get clarity on the IoT bandwagon, it’d be worthwhile to take a brief history detour. Where are the technology origins? What was it initially aimed for? How the concept evolved over the years?
The vision thing
The Internet of Things was not a new idea. In 1988, Mark Weiser, a technologist at the Computer Science Lab of Xerox Palo Alto Research Center (PARC), put forward the notion of ubiquitous computing as information technology’s next wave after mainframe and personal computers. In this new world, what he called “calm technology” would reside around us, interacting with users in natural ways to anticipate their needs.
Weiser coined the term “ubiquitous computing” to describe a future in which personal computers would be replaced with invisible computers embedded in everyday objects. He believed that this would lead to an era of computing in which technology, rather than panicking people, would help them focus on what was really important.
Weiser’s work—based on research on human-computer interaction and PARC’s earlier work on computing—initially sparked efforts in areas such as mobile tablets and software agents. Subsequently, these efforts morphed into pursuing intelligent buildings packed with wireless sensor networks and displays, where information follows wherever people go. Weiser’s vision was shared by many in the PC industry.
The first practical manifestation of ubiquitous computing emerged in the early 1990s when John Doerr, the legendary venture capitalist at Kleiner Perkins Caufield & Byer, started the pen-computing frenzy by funding Go Corp. By 1991, the pen-based computing wave had become the “next big thing” in technology world. Yet, despite this pen-based computing rush, only a single product became commercially available from GRiD Systems, a small computer outfit on the east of the San Francisco Bay.
But then Apple Computer’s chief executive officer, John Scully, fanned the flames of pen-based computing in a speech about a handheld computer he called the personal digital assistant or PDA. “Palmtop computing devices will be as ubiquitous as calculators by the end of this decade,” he told his audience. Scully echoed Weiser’s vision touting that computing would eventually go a step farther in the journey that started from mainframe to minicomputer to personal computer. In May 1992, Apple CEO announced the Newton, an amazingly ambitious handheld computer. Scully set the computer world on fire with his prediction that PDAs such as Apple’s Newton would soon contribute a trillion-dollar market. He professed that this gadget would launch the “mother of all markets.”
Newton failed to connect with the rest of the computing world, and five years after its launch, the newly arrived chief executive Steve Jobs abandoned the product to focus on Apple’s core Macintosh lineup. But the Newton debacle proved a kind of start-over that led to a new generation of PDAs that would focus on more practical features. A plethora of such products sprang up—offering some sort of interactive capability—and among them was Palm Pilot, a simple, no-frills compact device which hit the market in February 1996. Palm Pilot became one of the fastest-selling high-tech toys of the decade. The elegant little computer became an American icon; one million Palm Pilots were sold in the first eighteen months.
The rise of the machines
Next up, the cellular-centric machine-to-machine (M2M) communications industry emerged in 1995 when Siemens set up a dedicated department inside its mobile phones business unit to develop and launch a GSM data module called M1. It was based on the Siemens mobile phone S6 for M2M industrial applications and enabled machines to communicate over wireless networks.
Among these network-centric innovations, the most prominent early contributions came from mobile phone companies who had been using their 2G and 3G networks to connect everything from juke boxes to ice machines since the late 1990s. The use of the mobile technology as a payment gateway had started in Helsinki in 1997 when a company owned by Coca-Cola installed two mobile-optimized vending machines. These machines accepted payment via text messages.
The companies like General Motors and Hughes Electronics were also among the early implementers of the M2M technology.
What’s in the name?
PDAs and M2M continued their slow and modest journey toward gaining interactivity and getting assimilated into the network. Meanwhile, a British technologist Kevin Ashton became interested in incorporating radio frequency identification (RFID) chips into products with smaller form factors while he was working as an assistant brand manager at Procter & Gamble in 1997.
After a couple of years’ of work, he proposed using RFID chips to help manage P&G’s supply chain problems. He argued in an article that having humans input data was incredibly clumsy and inefficient. On the other hand, semiconductor chips and sensors were becoming smaller, cheaper and less power hungry, so they could be incorporated into just about anything.
Ashton suggested that getting information from objects themselves could revolutionize the supply chain. The “Internet of Things” was born. The use of an RFID chip within a miniature device connected wirelessly was akin to a simple SIM card, and it expanded the reach of the Internet of Things to healthcare, automobile, energy, and more.
Vision becomes reality
In 2000, LG Electronics announced plans to launch the first Internet refrigerator. Later, in 2005, the notion of theInternet of Things got official recognition from the communications world when the International Telecommunications Union (ITU) published its first report on this emerging industry discipline.
The report acknowledged, “A new dimension has been added to the world of information and communication technologies (ICTs): from anytime, anyplace connectivity for anyone, we will now have connectivity for anything. Connections will multiply and create an entirely new dynamic network of networks—an Internet of Things.”
In the 1990s, the concept of remotely monitoring and controlling distributed assets and devices a.k.a. the Internet of Things was mostly reserved for large and expensive investments like power plants and dams. Fast forward to 2013, connected products are expanding to e-books, cars, home appliances, smart grids, manufacturing, fast food, security, healthcare, and more. By 2020, billions of things—from clothes to cars and from body sensors to tracking tags—are forecast to be part of the Internet of Things bandwagon.
Image credit: Xerox PARC and Slideshare.net
The content of this article is based on the excerpts from The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future. The article was originally written for The Smartrphone World.
Last week was ASML’s investor day. I wasn’t there and they haven’t yet got the material posted on their website, so this is all second hand information. As you know, if you have read any of my comments on EUV, I have been dubious about whether EUV would ever work for production.
The three big problems seem to be:
I have heard other issues too, such as line-edge-roughness, but these seem more like the regular HVM ramp issues that greadually get fixed just by running a lot of wafers.
ASML announced that TSMC has ordered two more EUV scanners. They already have two and they will be upgraded with the new light sources. These are apparently on course to achieving 120W of output early next year and so can support 1000 wafers per day throughput (currently it is 80W and around 500 wafers per day). They claim 1500 in 2016 but schedules for anything to do with EUV have been notoriously unreliable.
They said that TSMC will be using these for 10nm production. I don’t think TSMC is going to try and introduce EUV at the same time as a new process node (nor 450mm if that ever happens). The initial PDKs for 10nm are already out and they involve multiple patterning. So I presume TSMC will actually introduce EUV for 16nm (probably not for production), do the HVM ramp for 10nm and then brings EUV in as an option there. Intel, by the way, have said they will not use EUV at 10nm.
In fact ASML’s CEO Peter Wennink conirmed this:We are working with a customer[presumably TSMC] towards a mid-node insertion of EUV at the 10nm logic node expected in late 2016. Other customers are preparing for initial learning in a manufacturing environment.
The next big problem has been mask contamination. The masks for EUV are reflective mirrors (actually not even all that reflective, ordinary mirrors absorb EUV just like almost anything). Without a pellicle, a thin covering for the mask, any contamination on the mask is in the focal plane and will print (see the above diagram). So masks need to be cleaned but there are a limited number of times a mask can be cleaned before the pattern starts to degrade. Intel has already said that they don’t see how to use EUV for volume manufacturing without a pellicle.
The challenge with a pellicle is that any material absorbs EUV with pSi being the best material by far. ASML said that they will manufacture pellicles too, so presumably striking that problem off the list.
I don’t know if progress has been made on the mask defect issue. The masks (and the mirrors in the optical path) are actually built up with multiple layers of Mo/Si. One of the challenges is that defects on the base layer can be too small to see with optical inspection (plus the size makes it equivalent to searching for a golfball in the whole of California). However, when the multi-layer mirror is build up the defect gets magnified to the point that it will print. There has been some work done on aligning the pattern on the mask so the defects are under the pattern, so irrelevant, but I’ve not seen anything about it recently. Anyway, I think mask inspection and mitigation are still an open issue.
Like you I cannot believe 2015 is upon us. 15 years ago I remember the Y2K panic. I remember watching the news and noticed the liberal media (they were liberal back then too) just waiting for the first fail somewhere. Ended up like Geraldo at the opening of Al Capone’s Vault. Remember that one? As I persist on with this word salad may I be the first to wish you a Merry Christmas?
I just witnessed again, Uncle Billy giving the 8 grand to Mr. Potter (It’s a Wonderful Life), drives me nuts every time. I better write something techy here, I’m losing you. Happy New Year as well!
In 2014, Xilinx quietly solidified its global lead for the next decade by finalizing what I would call a morph from a fabless FPGA company, to a fabless SoC + EDA company. Did you catch that morph? It has been an ongoing execution since Moshe became CEO of Xilinx in 2008. Moshe took the helm of a great company with the challenge of making Xilinx even greater. Having an EDA background (which Moshe had coming from Cadence) did not hurt.
Not by chance but by Xilinx strategy they acquired AutoESL (which developed a tool called Autopilot; the 1[SUP]st[/SUP] ‘C to gates’ tool that worked great in my opinion). Xilinx rolled AutoPilot into Vivado calling it Vivado HLS. I keep banging this drum but here is where an FPGA could ‘really’ be programmed using C/C++. The figure below is not marketing propaganda but reality. Xilinx had the foresight that a programming model beyond RTL would be needed.
While all this is going on Xilinx ISE circa 1995 (plus many updates along the years) was not going to get a face lift but a morph as well (or burial of sorts). It started by throwing the ISE Place and Router (P&R) away and designing a new one from scratch just like grandma did. There was just no way simulated annealing was going to yield reliable P&R times nor efficient FPGA usage with 4M+ Logic Cells in view. Vivado was born using analytic place and route which yields this fantastic before and after as shown below.
Speaking of another birth, the Millers are expecting another in March 2015, of the male kind. For earned value I have already taken credit for the birth in the FYI 2014. For those of you counting this will be Child number 8, Lord willing.
2015 will be the year of ‘16’, nanometer that is. But more than that, Xilinx recently announced ‘SDAccel’:
· First Architecturally Optimizing Compiler for OpenCL, C, and C++
· First Complete CPU/GPU Like Development Experience on FPGAs
· First Complete CPU/GPU Like Run-time Experience on FPGAs
This video does a great job on explaining what SDAccel is all about.
Xilinx brought to the world the first ARM SoC FPGA named Zynq. Software engineers once alienated from FPGAs found themselves where hardware engineers lived, except from a different view. This is the grand unification of Xilinx FPGAs into all systems, and I mean all. SDAccel is not just another ‘tool’ in the ‘tool box’ but the very fabric that will allow Xilinx FPGAs to live in data centers, IoT, Military Systems and where CPUs/GPUs are embedded but no longer are affordable options. The table below from theLinley Group does a great job highlighting the Xilinx SDAccel significant advantages. Like I said in July, RIP CPU.
The C/C++, OpenCL programming model for FPGAs is here to stay and Xilinx has the edge not only in silicon but with tools as well. Wait ’til you see 2015 from Xilinx…. I cannot wait!
eSilicon engages with customers in many different ways, from providing a full menu of design services down to simply manufacturing parts. Increasingly, they have been automating a lot of this on their website. It started with automatic quotes for MPW shuttles and more recently they have a full production quote system for parts that will be manufactured by TSMC. Presumably more foundries will come.
See Getting a Quote Without Talking to a Salesman
eSilicon also provide IP, primarily memories and specialized I/Os. They have two development groups in Vietnam (in Ho Chi Minh City and Da Nang) where most of this work is done. They have now started to put their IP portfolio online too, allowing customers to serve themselves. This first version of what they have named IP Marketplace is available now, allows you to try IP before you buy it, and the second version which should be available in March next year, will also allow the actual procurement to be done online too.
The current version allows you to find out power, performance and area (PPA) for any item of IP. This can be displayed graphically, in a table, or downloaded to Excel. The system supports all eSilicon developed IP (in the future 3rd party IP will also be available) including memory compilers, standard and specialty I/Os and across multiple foundries, currently TSMC, GlobalFoundries, Dongbu and LFoundry at a range of different process nodes. You only need to pay for the IP when the chip tapes out.
The marketplace makes it easy to compare PPA across different potential process nodes at different foundries, and also try different configurations of memories at different operating points (PVT). See the diagram above. You can download a complete chip memory subsystem for free, giving you the full capability to “try before you buy” and without needing to have eSilicon personnel in the loop slowing the process down. But it is not just the specification data that is free to download, you can get all the front-end views to actually do the design (or do an even more detailed analysis). You purchase the layout (GDS II) only when you are ready to tapeout and, of course, only for the IP blocks that you actually ended up using.
If you are using TSMC, you can now get all the IP you need and get a legally binding prototype and production quote, all online. All you have to do is actually design the chip!
eSilicon’s IP Marketplace page is here, where you can find out more, login or create a new account.
As I wait for my plane to Taiwan I’m wondering what the New Year has in store for the fabless semiconductor ecosystem. Good things I hope but to make sure let’s take another look at one of my trusted economic bellwethers (TSMC) which I’m guessing will break the $25B revenue mark this year. That is more than a 25% growth rate year over year. What an amazing road this company has paved for us!
Here are some interesting snippets from the TSMC 14th Annual Supply Chain Management Forum held in Hschinsu last week:
“TSMC’s success comes from collaborating with our customers and suppliers through our Grand Alliance so that we magnify each others’ innovations and stand together as a most powerful competitive force in the semiconductor industry,” said TSMC Co-Chief Executive Officer Dr. Mark Liu. “Our supplier partners are a critical part of this alliance, and we look forward to reaping the rewards of many years of strong growth together.”
The Outstanding Contribution Award went to Applied Materials for EPI/PVD Equipment and Local Service. From what I heard this is in direct response to the success of the 16FF+ process but more on that later.
One of the things I have enjoyed over the years is the candid nature of Morris Chang’s comments. Even on the quarterly conference calls which are usually scripted. So far I have experienced the same from heir apparent Mark Lui. Take a look at Mark’s resume on the TSMC website:
Dr. Mark Liu is currently President and Co-Chief Executive Officer at Taiwan Semiconductor Manufacturing Company (TSMC). Prior to this, he was Co-Chief Operating Officer from March 2012 to November 2013. Before that, he was Senior Vice President of Operations from 2009 to 2012. From 2006 to 2009, he was a Senior Vice President responsible for the Advanced Technology Business at TSMC. From 1999 to 2000, he was the President of Worldwide Semiconductor Manufacturing Company.
Prior to joining TSMC, from 1987 to 1993, he was with AT&T Bell Laboratory, Holmdel, NJ, as a research manager for the High Speed Electronics Research Laboratory, working on optical fiber communication systems. From 1983 to 1987, he was a process integration manager of CMOS technology development at Intel Corporation, Santa Clara, CA, developing silicon process technologies for Intel microprocessor.
Ph.D., Electrical Engineering and Computer Science, University of California, Berkeley
Some people say filling the shoes of Morris Chang will be difficult but I do not see a problem here. I would hold Mark’s credentials up against any other CEO in the semiconductor industry, absolutely.
Also Read: Intel is NOT Quitting Mobile!
We know that the best technology or product, even if it exhibits best in class and unmatched features, is almost of no use if lacking an ecosystem. If you think about a processor core, you will expect to find compatible communication bus and memories (inside the SoC) and operating system, compiler, debugger, etc. When dealing with a disruptive ASIC technology like FD-SOI, you will expect to have multiple sources for raw SOI wafers, at least double sourcing capability for processing these wafers and, last but not least, a solid IP ecosystem. If you can’t decree the creation of this IP ecosystem, you (the foundry or ASIC vendor) can certainly invest resource to internally develop the foundation IP (standard cell library or memory compiler). Your involvement in supporting or initiating the development of complexes IP by the best in class IP vendors will make the difference too.
Taking a look at this FD-SOI roadmap, extracted from the presentation made by Patrick Blouet from ST during IP-SoC “Which IP from FDSOI Ecosystem”, give you an idea of the additional features and related IP to be added to the current offer at 28nm FDSOI. Today the status is that you can design a complete digital SoC (for example an Application Processor), including high performance CPU and GPU (from ARM or Imagination Technologies), internal memories for cache, DDR4 memory controller (from Cadence) and the various IP to support interface protocols like USB, HDMI, MIPI and probably more.
The 28nm roadmap feature path gives you some interesting indication too. If RF IP can be available on the same IC to support WiFi, Smart BT or WigBee as well as some advanced mixed-signal function, you are close to build a dedicated IoT chip supporting smart watch or metering application. Then the designer could take full advantage of the power efficiency inherent to FD-SOI technology, and release to the IoT market an application offering strong differentiators in term of cost (monochip solution) and power consumption, thanks to FDSOI. On the below picture, ST claims for a power consumption improvement better than 3X between 40LP and 28 FDSOI.
This example of a SoC integrating RF and mixed-signal illustrate an IoT application, but a building a complete IP ecosystem will require to port many existing functions to FDSOI. At SOC level, migrating an existing design from bulk to planar FD represents an effort comparable to half-node migration, for example from 45nm to 40nm. In other words, it brings very worthwhile benefits at reasonable efforts. A typical approach could be:
During the presentation at IP-SoC, Patrick Blouet has unveiled THINGS2DO, the program supporting the FDSOI ecosystem creation:
The partners rank from Silicon suppliers, tools providers, IP & Design Houses, System integrators and research organizations. Developing IP supporting FD-SOI is a business driven decision, and we know that the more IP will be available, the higher will be the number of FD-SOI ASIC design-win. “Somebody“ has to initiate this virtuous cycle, and ST has decided to do it with THINGS2DO initiative. This decision is certainly the best THING to do at the moment, like giving a kick to start a motor, the market following when the business will become attractive enough. Because Samsung and Global Foundries are also in the loop, we have no doubt that this IP ecosystem will grow…
From Eric Esteve from IPNEST
Synopsys announced their earnings a couple of days ago. This is actually also the end of their fiscal year. They had quarterly earnings of $539M meaning that they did just over $2B for the year. Their guidance for fiscal 2015 is revenue between $2.185B to $2.225B. They said that about 80% of that revenue is already in backlog.
But it is some of the color that I think is more interesting if you are looking at the whole industry and not just trying to decide if Synopsys stock is going up or down. For example, Aart said that they have 170 active FinFET designs and tapeouts all the way down to 10nm. Designs in more mature nodes such as 20nm, 28nm and 40/45nm are increasing in complexity since many designs don’t need the absolute most advanced node and the cost of these older nodes seems to be lower.
Aart went on to put Synopsys strategy down explicitly. The headline is to continue to invest in EDA but also broaden the product portfolio to address a more diversified set of customers.
Priority number 1: Maintain clear technical, business and support leadership in core EDA. This will mostly be through organic growth, rather than acquisitions. Synopsys introduced several major developments this year such as verification compiler and IC Compiler II, and there are more to come in 2015.
Priority number 2: Drive continued growth in IP and Systems, leveraging the confluence of increased outsourcing of IP, growing technical complexity, and the essential customer need for trust and reliance on its partner suppliers. Synopsys is already the #2 supplier in IP (ARM is #1) and the trend towards design being a combination of IP assembly and software has them in a good spot.
Priority number 3: Expand our presence in the software-quality, test and security space by building on the excellent technology from Coverity. This is a two-pronged strategy, firstly selling software quality products into the software groups associated with chip designs, where obviously Synopsys is already engaged. But also sell into:the large untapped software-applications market that reaches from financial to health, energy, retail, social media to virtually any company doing sophisticated software and having quality, security and testing issues.
Core EDA is relatively slow growing (“single digit”), despite the huge investment required to create leading edge tools that keep up with the process node transitions. Like the queen in Alice Through The Looking Glass, it takes all the running you can do to stay in the same place. Or as Aart put it in the Q&A:So, one hand same old, same old. On the other hand, same old has always meant very rapid progress.
IP is growing faster (“double digit”) and getting increasingly profitable. In Q4 Synopsys closed a multi-year agreement for 16, 14 and 10nm IP outsourcing with AMD and hired 150 of their engineers into their IP team. They already have some 10nm IP wins.
The Coverity space is a huge new market. About half of Coverity’s business is in embedded software but the other half are in pure application software markets. Coverity should be breakeven by middle of 2015 with revenues of over $100M in 2016.
This was Brian Beattie’s last call as CFO since he has been promoted to run all the adminstrative operations of Synopsys, including IT, HR and strategy. Trac Pham is the new CFO.
In the Q&A Synopsys was asked about their largest customer since they hadn’t said it was over 10% as they usually do. Everyone knows the customer has to be Intel although nobody is allowed to say that word. And it was just over 10% as usual.
IEDM (technically the International Electron Devices Meeting although I’ve never heard anyone use the full name) is in a couple of weeks time, in San Francisco. It is December 15-17th at the Hilton Union Square (which is not actually at Union Square but nearby at 333 O’Farrell Street).
For the last few years on the Tuesday evening Coventor have sponsored an event (with appetizers and drinks). Last year it was all about collaboration. This year the topic is variation, Survivor, Variation in the 3D Era. It is at the Hotel Nikko from 5.30pm to 8.30pm on Tuesday December 16th in the Carmel Room. Hotel Nikko is 222 Mason Street just around the corner from the Hilton.
The format is a panel session moderated by our very own superstar Dan Nenni, who will be just back from Taiwan surrounded by his fan-club of hot Chinese babes and senior foundry executives. Or not.
I talked to David Fried today to get a little more background. The panel consists of:
The slogan of the session is taken from Survivor, but instead of being Outwit, Outplay, Outlast it is Reduce, Contain, Understand. Or as the Coventor flyer says:It’s a jungle out there. The era of 3D semiconductors, 3D NAND Flash, FinFETS and unprecedented process complexity introduces new pitfalls for the cunning engineer to overcome. Find out how the best and the brightest are outwitting the competition with creative ways to navigate the treacherous landscape of advanced IC design and manufacturing. They know the key to survival in dealing with process variation is to … Reduce It. Contain It. Understand it.
There are two people from each segment. Lam Research and TEL America need to reduce variation. In the meantime Oracle and GlobalFoundries need to contain it. And Coventor and PDF Solutions to understand it. Or something like that, in reality, everyone needs to worry about all aspects of variation.
Even before double patterning, variation was becoming an issue, since it made the traditional approach of worst-casing timing ineffective. The worst case barely moved even though the typical case was much improved, so if the investment in new process technology was going to be worthwhile, a new approach was needed with increasing accuracy replacing the brute force approach of just assuming the worst. But now we have double patterning which means that for those layers there is even more variation since the two exposures are not (usually) self-aligned meaning that, for example, the sidewall capacitances of interconnect can vary a lot depending on how perfectly aligned the two exposures are. But also in a predictable way, if some capacitances are up then others are down.
Anyway, we will see what these experts have to say about it all in a couple of weeks. There is no requirement to register, you won’t get a name-badge, but if you want to go then tell Coventor (so they know how much beer and food they need). Just send an email to rsvp-to-coventor@coventor.com saying you will be there.
I will be. See you there!
