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FD-SOI Foundry

FD-SOI Foundry
by Paul McLellan on 03-16-2015 at 7:00 am
Categories: FD-SOI, Foundries, STMicroelectronics

At the end of last month during ISSCC there was a forum organized by the SOI Consortium. It took place in San Francisco at the Palace Hotel (which, if you have never been there, is famous for converting its old entryway for carriages into an amazing dining room, and for a bar with a huge painting by Maxfield Parrish of the Pied Piper valued at over $5M, up a little from its original price of $6K). There were presentations on:

  • FD-SOI advantages for applications and ecosystem, Philippe Magarshack, STMicroelectronics
  • 28FD-SOI: Cost effective low power solution for long lived 28nm by Kelvin Low, Samsung
  • Synopsys FD-SOI IP Solutions, Mike McAweeney, Synopsys
  • FD-SOI: Ecosystem and IP Design, Amir Bar-Niv, Cadence
  • FD-SOI Promises for 100Gb/s and Beyond Optical Transceiver, Naim Ben-Hamida, Ciena
  • 28nm FD-SOI Design/IP Infrastructure, by Shirley Jin, Verisilicon
  • Driving Profitable Innovation and Rapidly Growing Ecosystems with a Semiconductor Start-up Incubator,Mike Noonen, Silicon Catalyst
  • RFSOI: Redefining mobility and more in the front-end, Mark Ireland, IBM
  • Towards a Highly-Integrated Front-End Module in RF-SOI using Electrical-Balance Duplexers, Barend Van Liempd, imec
  • RF SOI: from Material to ICs – an Innovative Characterization Approach, Mostafa Emam, Incize
  • ST H9SOI_FEM: 0.13µm RF-SOI Technology for Front End Module Integration, Laura Formenti, STMicroelectronics
  • SOI: An Enabler for RF Innovation and Wireless Market Disruption, Peter Rabbeni, GlobalFoundries

There was also a panel discussion moderated by our own Dan Nenni.

See also RF on SOI at GF


When FD-SOI was first being talked about it was perceived as a purely STMicroelectronics initiative. The whole world was going FinFET except for ST. But since then there have been a regular stream of announcements as the ecosystem expanded. GlobalFoundries announced that they had licensed FD-SOI in 2013 (but have not really said anything since). Samsung announced that they had licensed FD-SOI in June last year just before DAC. In January at the Tokyo forum Sony announced a chip they had built on FD-SOI. At Embedded World Freescale (soon to be merged with NXP) announced they were designing chips in FD-SOI. And on Dan’s panel Cisco discussed their own experiences. Ciena also presented their experiences at the San Francisco forum.


Since Samsung are a foundry, Kelvin Low’s presentation was one of the more important. If FD-SOI is going to be relevant then it needs to have availability from multiple sources. Samsung are clearly looking at 28FD-SOI as an extender for planar 28nm:

  • lower power
  • similar manufacturing cost (FEOL is simpler, which offsets higher substrate cost; BEOL is identical)
  • cheaper cost per transistor than FinFET
  • higher performance
  • easy port of designs from planar

These attributes make it a great basis for internet of things (IoT) applications which do require low power but don’t need the complexity of 14/16nm FinFET.

Kelvin said that the process had passed wafer level reliability (WLR) qualification in September last year. Samsung themselves are providing the foundation libraries and basic IP support. IP vendors are providing higher level IP (much of it at the RTL level of course) and design partners are providing ASIC design services.


All the presentations from the forum are here (or will be, some are not yet received).

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Apple Leaks Chip Sources?

Apple Leaks Chip Sources?
by Daniel Nenni on 03-15-2015 at 10:00 pm
Categories: Foundries, GlobalFoundries, Intel Foundry, TSMC

Take a look at the figure below and tell me this information did not come from inside Apple. The question is: Was it voluntary or involuntary? Inquiring minds want to know! There are some minor surprises which I will get to in a minute but the actual source information is spot on to what I have heard the past few quarters. This spicy little piece of information comes from the SemiWiki Semiconductor Process Technology Forum by the way. SemiWiki has always been about crowdsourcing and you will not find a better semiconductor crowd than on SemiWiki.com, absolutely.


In the fabless semiconductor industry there is always a lively debate on who will supply chips to whom. For Apple at 20nm it was TSMC versus Samsung. The Taiwan Press said TSMC and the Korean Press said Samsung. Even after it was clear that TSMC had won the A8 business the Korean press still said Samsung was supplying 20-30% of the chips. The Apple A9 has been all over the map. My prediction was that Samsung would get the A9 since their 14nm LP was ahead of TSMC by 3-6 months and TSMC would get the A9x which jibes with the figure above. I also believe that TSMC has the A10. Samsung having the A10x with 10nm is news to me. It was my understanding that Apple was still evaluating 10nm processes. The 10nm PDKs just came out so I would not bet on this one yet.

The other surprises for me are with the specific process nodes. The A9x should not be using TSMC 16nm, it should be TSMC 16FF+, and the A10 should not be 16nm FF+, it should be a new and improved Apple “tuned” version of 16nm. One interesting note, GlobalFoundries is mentioned as a second source for 14nm but not 10nm and obviously Intel Custom Foundry is nowhere to be seen but more on that later.

Notice that the figure says iPad & MAC for the A9x and A10x? Not really a surprise. In fact, I say it’s about time! Sign me up for six of those as long as they are iOS compatible. I really, really, really am sick of Microsoft Windows!

For the Apple iWatch I agree completely. The S1 is a scaled down version of the A7 which is Samsung 28nm. Given that, it is easy to assume the S2 is a scaled down version of the A8 which is TSMC 20nm.

The baseband processors for the next two versions of the iPhones (iPhone 6s and iPhone 7?) are a bit of a surprise as well. Not the vendors so much (QCOMM and Intel) but the fact that Apple does not have them integrated into the A9 and A10 SoCs. To me this is a total technology fail on their part. And it is not only cost but also power and packaging. As THE leading SoC design company Apple should be publicly shamed for this unless I’m missing something here. Why would Apple not integrate the baseband processor like Qualcomn, MediaTek, and other SoC companies already have?

The takeaway I have from this figure is that Apple is intentionally splitting orders amongst the foundries, not necessarily based on technology, but for business reasons. Clearly Apple wants multiple wafer sources and they will do whatever it takes to make that happen.

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Will the IC Market Growth Rate Stagnate in 2015?

Will the IC Market Growth Rate Stagnate in 2015?
by Pawan Fangaria on 03-15-2015 at 7:00 pm
Categories: Foundries, Semiconductor Services

In my last blog here, I talked about last 30+ years of semiconductor IC market. While we have seen this market growing at CAGR of ~9% over last 30+ years, the CAGR of current decade is expected to be at just ~4%. Although the base size of the overall semiconductor IC market is quite healthy, expected to be at ~$378B by 2019, we cannot hope for high growth rate from here. My belief about this proposition becomes stronger when I see a detailed report about the growth of major product categories in IC market, published by IC Insights here.


This report shows that IC market growth in 2015 will be a tad below at 7% compared to 8% in 2014. And only 11 product categories out of 33 will show growth rate higher than the 7% average of total IC market. This is less of a worry than what is being revealed when I look at the relative growth of individual product categories between 2014 and 2015.

True, there is growth seen in automotive ICs, 32-bit MCUs that support driver information system and semi-autonomous driving system, and NAND Flash that support mobile systems. However, look at their growth rate figures in 2015 compared to 2014; they are just about 1 to 3%. Whereas there are others that are staying above average 7% growth rate of total IC market, but their growth rates in 2015 have declined significantly compared to 2014. DRAM growth has declined from 33% to 14%, Power Management Analog growth has declined from 16% to 8%, and Amplifiers/Comparators growth has declined from 11% to 7%.

If we look at the line below 7%, we see similar situation. Tablet MPU growth has declined from 9% to just 3%, Industrial Special Purpose Logic growth has declined from 10% to 5%. We do not see growth of any category rising except 16-bit MCU and Wired Communication.

An interesting inference from the data at the end of the table, where product categories with de-growth are projected, is that they are improving; improving in the sense that their de-growth numbers have reduced although they are still in negative. Only Wired Communication – Application Specific Analog has dramatically recovered from -30% to 2%.

Looking at these figures, I think we are going to see ~5% CAGR in future, 5-10% in good times, 0-5% or even negative in bad times. It may be open to debate as we have not seen the IoT market yet. Automotive market is supposed to be the leading one in terms of percentage growth; the initial numbers of automotive ICs in 2014 and 2015 are here to see!

Can we say the IoT market will bring high growth rate of more than 10% CAGR? I do not think so. IoT itself will grow at a rate of ~22%, but that may take a decade to become a critical mass in itself to become a deciding factor. The semiconductor market with the reference of IoT can be better discussed after this decade. Comments welcome!

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Lake Tahoe: The Center of ESD Innovation

Lake Tahoe: The Center of ESD Innovation
by glforte on 03-15-2015 at 1:00 pm
Categories: EDA, Siemens EDA

Almost anyone that is active in IC design will be “in touch” with Electrostatic Discharge (ESD) at some time (pun intended). Preventing ESD related IC failures remains something like black magic—at least it’s easy to get that feeling when you are trying to debug ESD failures. I/O and ESD layouts that resulted in excellent robustness in one IC product might suddenly create havoc in a slight product variation. Designers have been hired and fired over ESD.

Have you run into an ESD related problem recently? What did you do: check with a colleague, the internet, online forums, or your old university courses notes on semiconductors?

Worry no more! Every year the world’s experts on Electrostatic Discharge gather in a highly interactive conference called the International ESD Workshop (IEW). This year it’s at the majestic Granlibakken Conference Center and Lodge in beautiful Lake Tahoe, California from May 3 – 7, 2015. This setting provides the perfect opportunity for participants to meet in a relaxed, invigorating atmosphere and engage in discussions about the latest research and issues of interest within the EOS/ESD community.

The IEW facilitates interactions among industry leaders through invited seminars, technical sessions, special interest groups (SIGs), discussion groups (DGs), and invited speakers. This year the focus is on Power Management for EOS/ESD, and EDA EOS/ESD Tools Best Practices and Experiences, but many other topics are included as well.

Scheduled poster sessions form the core of the technical program. These are preceded by a brief introduction by the authors in a plenary “teaser” session. The teasers encourage participants to select the posters of greatest interest. Meet and chat with the authors, while you expand your knowledge and network in the subsequent poster discussion session. This format provides an ideal forum for learning and exchanging new ideas. Topics covered in the poster sessions include IC EOS/ESD design, verification, test, multichip and system level ESD.

The discussion groups, held in the evenings, are a unique part of our interactive workshop. While each EOS/ESD topic discussion is facilitated by an expert on the subject, the main discussion will take place among the DG participants. The discussion groups will address topics such as 3D-IC, ESD Compact (SPICE) Models, ESD FOS (From Outside to Surface), Latch-up Testing and other interesting topics. The IEW also provides a similar forum for Special Interest Groups (SIGs), on selected subjects that may extend beyond the IEW time frame. Some SIGs have been successfully meeting for several years.

A number of stimulating state-of-the-art EOS/ESD seminars and invited talks are also scheduled. Come and listen to presentations discussing power management, EDA best practices and other exciting topics. As a break to EOS/ESD discussions, and to provide an opportunity to enjoy the spectacular surroundings, an afternoon is reserved for recreation with fellow attendees. This is a great way to become better acquainted with your EOS/ESD colleagues.

Come and meet experts, share your views, ask questions, and extend your network with EOS/ ESD experts from industry and academia. Above all, learn how to efficiently deal with today’s EOS/ESD challenges and prepare for tomorrow in an informal and interactive atmosphere. We sincerely hope that you will join us in Lake Tahoe for the 2015 IEW to ensure that ESD is no longer black magic. http://www.esda.org/iew.htm

Matthew Hogan (Mentor Graphics), IEW 2015 General Chair
Bart Keppens (SOFICS), IEW 2015 Publicity Chair

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Shifting Chip Design Left!

Shifting Chip Design Left!
by Daniel Nenni on 03-15-2015 at 7:00 am
Categories: EDA, Synopsys

In the traditional sense “Shift Left” is the process of making things simpler in an effort to make things faster. Shift Left was the theme of theDVCon keynote last week delivered by Synopsys co-founder and co-CEO Aart de Geus which is right on topic when it comes to modern semiconductor design and manufacturing, absolutely.

KEYNOTE: Smart Design from Silicon to Software

In our current semiconductor design community, the word “change” is, to say the least, an understatement. From a dizzying array of emerging “smart” niche end-products to major market trend shifts to ecosystem reconfigurations at every level, the world around us is morphing at an unprecedented pace. The challenge for IC designers to keep pace has never been greater. The good news is that we’re up for it! In his presentation, Aart will address the business and technology trends that are stretching designers’ concerns beyond the traditional sand boxes of design and verification.

First you should know that more than 1,200 semiconductor professionals participated in this event which is an all-time high. I was there, it was packed, I ran out of business cards yet again. Synopsys put out a nice lunch with great speakers from Freescale and Xilinx but Aart stole the show of course and he stayed afterwards for questions which is nice.

The premise of Aart’s keynote is that design schedules are not really changing but more work is being done within the same schedules. The big change I have seen is what I call the “Apple Effect”. In order to get a bite of the billions of dollars of Apple semiconductor ecosystem business you must synchronize your product schedules to the yearly iPhone release date which is just in time for the holiday shopping season.

The entire fabless semiconductor ecosystem pretty much accommodates Apple now including chip companies, foundries, IP providers, and even EDA companies. I welcome this added discipline (no more slipping product schedules) but the added pressure is seriously stressing the ecosystem. What does not kill us makes us stronger, right?

The point of Aart’s keynote that resonated strongest with me, along with IP re-use, was the requirement of eliminating point tools to shift your design schedule left: “In order to shift left you must have predictability through a highly connected design flow”.This is something I have heard since the beginning of big EDA but it has yet to come true. That is of course before multi-patterning, FinFETs, full coloring, and who knows what other design horrors 10nm and 7nm will bring us. Well, I have a pretty good idea but that is another discussion all together. The bottom line is that synthesis must be aware of the entire “design coherent system” if you want to Shift Left in the coming process nodes.

Coincidentally, one of the most viewed wikis on SemiWiki is the EDA Mergers and Acquisitions wiki. It is a VERY long list now and as you will see Synopsys is actually many different point tool technologies (400 million lines of code according to Aart) integrated into a seamless synthesis driven flow. It will be interesting to see what new point tool companies will be at DAC this year. They certainly are a dying breed and that makes me wonder what the future has in store for EDA. Certainly not what I had predicted in my first blog ever: EDA is Dead.

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Arteris Flexes Networking Muscle in TI’s Multi-standard IoT Chip

Arteris Flexes Networking Muscle in TI’s Multi-standard IoT Chip
by Majeed Ahmad on 03-14-2015 at 7:00 am
Categories: Arteris, IP

Arteris Inc., a network-on-chip (NoC) interconnect IP solution provider, has joined hands with Texas Instruments Inc. to create an ultra-low-power chip that helps Internet of Things (IoT) devices go battery-less with energy harvesting and support coin cell-powered IoT operation for multiple years.

Another low-power MCU parable with energy efficient ARM cores? Well, yes. However, what’s new in this MCU tale is the fact that TI’s new chip supports multiple wireless standards. Another prominent highlight is how TI has implemented Arteris’ FlexNoC interconnect fabric in its SimpleLink ultra-low power wireless MCU portfolio to facilitate the communications part of the IoT device.

TI’s wireless MCU platform for IoT applications

The FlexNoC fabric serves as the system-on-chip (SoC) backbone in these low-power MCUs and helps implement IoT wireless communications standards such as Bluetooth low energy, ZigBee, 6LoWPAN and sub-1GHz. TI claims it’s the first SoC product that supports multiple wireless connectivity standards using a single-chip and identical RF design. And the fact that a single die can be used in multiple IoT products allows TI to explore a unique SoC derivatives strategy.

The Dallas, Texas–based chipmaker’s SimpleLink ultra-low-power wireless platform comprises of CC2620 (ZigBee RF4CE), CC2630 (6LoWPAN or ZigBee), CC2640 (Bluetooth low energy), CC2650 (2.4GHz technologies), and CC1310 (sub-1GHz operation) IoT chips.

TI’s CC26xx family of low-power RF devices has integrated an ARM Cortex-M3 MCU, Flash/RAM, analog-to-digital converter (ADC), peripherals, sensor controller and built-in robust security on a single chip. There is a speculation that one of the first CC26xx chips is going into an Oral-B toothbrush for kids.

About FlexNoC Part
TI has used FlexNoC power disconnect and firewall features to fuse-off select digital I/O controllers and that has enabled various combinations of ZigBee/IEEE 802.15.4, ZigBee RF4CE, Bluetooth low energy, 6LoWPAN, and the proprietary SimpliciTI wireless protocols. As a result, TI was able to produce an entire IoT product lineup with a minimal number of digital logic components.

Moreover, TI brought down the power consumption by employing the inherent low latency performance of zero-latency cycle paths, which were enabled by fully combinatorial logic in FlexNoC interconnect IP. The FlexNoC fabric has also allowed TI to effectively use firmware in meeting the most stringent power and timing requirements.

FlexNoC safely disconnects power to parts of SoC and clock tree

TI’s IoT chips are an important design win for Arteris that claims that the number one benefit of using the FlexNoC interconnect technology is power management. TI’s General Manager for Wireless Connectivity Solutions Oyvind Birkenes acknowledges the role of FlexNoC’s power management features in creating what he calls the lowest-power IoT communication devices in the world. “FlexNoC allowed us to create a small set of digital logic SoC dies that serve as the brains of more than one hundred different products, each customized for its particular market.”

The implementation of FlexNoC technology inside TI’s wireless MCUs is crucial for Arteris for two reasons. First, IoT is a high-growth market, and an IP socket in a strategic market like IoT is a significant testimonial for Arteris’ network-on-chip technology. Second, it negates the common perception within IC design circles that the NoC interconnect IP products are only used in highly complex SoC designs.

RF and Power Conundrums
According to TI, its SimpleLink family of ultra-low-power MCUs for IoT devices boasts energy footprint that is small enough for a coin cell battery to power a light switch in smart home for 10 years. TI’s wireless MCUs even promise support for battery-less operation of energy harvesting-based sensor nodes.

So how were Arteris and TI engineers able to pull off this power management feat? Power management success stories in the wireless domain are typically traced back to the RF part. It’s usually the drain caused by transmit and receive currents inside wireless chips that puts constraints on the battery.

However, a closer look reveals that RF devices like radio transceivers usually don’t contribute much to power consumption within a wireless chip. In fact, it’s small sensors and wireless protocol stacks within an SoC device that mostly add up to power drain. To counter that, for a start, TI’s CC26xx family of IoT chips use two energy efficient MCUs: an ARM Cortex-M3 and a sensor controller.

The ARM Cortex-M3 is the main system CPU inside the CC26xx device that consumes less than 3mA while running at the maximum speed of 48MHz. Next up, sensor controller—which comprises of a 16-bit CPU coupled with peripherals like ADC, analog comparators, SPI/I2C and capacitive touch—facilitates interface with external analog or digital sensors autonomously while the rest of the SoC device sleeps.

Ultra-low-power footprint despite support for major wireless protocols

And that’s only part of the story. TI’s complete chip can stay in standby mode at only 1uA using memory retention and real-time clock (RTC) techniques. According to EEMBC’s ULPBench, it enables the CC26xx platform to offer half the power of other MCUs. Here, TI has put to work many of the FlexNoC power management features to safely disconnect power to individual IP blocks as well as to parts of the on-chip fabric and clock tree.

The designers of portable wireless products can keep the standby currents between the transmissions to minimum and save enough juice in the battery for the active use. For that purpose, in the CC26xx family of IoT chips, TI uses an ultra-low leakage SRAM that can be fully retained while having the RTC running. Meanwhile, CPU is retained in standby mode, which consumes as little power as 1uA. Moreover, in shutdown, the CC26xx can wake up on external I/O events while drawing as little as 150nA.

Take heart-rate monitor, for instance, which needs to run the ADC 10 times per second to capture the heart rate accurately. An ultra-low power CC26xx MCU can let the sensor controller perform all the ADC measurements and wake up the ARM Cortex-M3 every 10[SUP]th[/SUP] ADC sample for optional processing and group RF transmission of this data.

Image credit: Texas Instruments Inc.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

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RF on SOI at GF

RF on SOI at GF
by Paul McLellan on 03-13-2015 at 7:00 am
Categories: FD-SOI, Foundries, GlobalFoundries

Unless you have been living under a rock for the last decade, you can’t help but notice the increased importance of RF: bluetooth, WiFi, 3G, LTE, NFC, RFID and more. There is a lot of digital design associated with these standards, especially the highest bandwidth ones, but they also all contain a radio, often called a modem. Some, like LTE, have to have enough power to reach a cell-phone tower several miles away, others, like NFC, only need to work over short distances. At the FD-SOI and RF-SOI Forum in San Francisco at the end of last month, Peter Rabbeni of GlobalFoundries presented on SOI: An Enabler for RF Innovation and Wireless Market Disruption. Some RF can be done using standard CMOS but a lot requires more esoteric technologies such as SiGe (silicon-germanium), GaAs (Gallium-Arsenide). Or SOI. In fact RF on SOI is growing at a CAGR of over 20% and that is before the Internet of Things (IoT) really takes off with its almost universal requirement for wireless connectivity. Currently SOI has about 65-70% market share of RF switches. SOI brings some advantages that other approaches lack, primarily due to the isolation that comes from the high-resistance substrate, and the fact that it is basically a mainstream process that can be manufactured in a standard CMOS fab at comparatively low cost. Since standard logic can also be built on the same wafer, it is easy to integrate the control with the RF on a single die and even integrate the power amplifier on the same die. Further, due to the isolation, it is possible to stack devices to handle higher voltages. One of the challenges in radios is being able to create tunable filters. This is a pre-requisite for being able to use a single radio for multiple frequency bands. This is something enabled by SoI as is shown by some cutting-edge work done by ST and University of Twente. GlobalFoundries has various technologies suitable for RF, one of the most important being the 130nm RF SOI process which is manufactured in Singapore. This process is targeted to the RF front-end market for RF switches, integrated PA and high-voltage devices. There are a number of customers designing in the standard process today and there are also customer-specific SoI processes such as is used for the Peregrine Global1 product. In addition to GF’s own RF business, IBM has a large RF business that is manufactured in their Burlington VT fab. They are an industry leader in this business. It is complementary to the GF portfolio and the two roadmaps will be integrated once the acquisition of IBM’s semiconductor business by GlobalFoundries is completed. IBM also has a large share of the SiGe market for very high performance. GF has some SiGe business but nowhere near as extensive. Again, the two businesses will be integrated post-acquisition. The presentation should soon appear here.

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CDC Verification: A Must for IP and SoCs

CDC Verification: A Must for IP and SoCs
by Pawan Fangaria on 03-12-2015 at 1:00 pm
Categories: EDA

In the modern SoC era, verification is no longer a post-design activity. The verification strategy must be planned much earlier in the design cycle; otherwise the verification closure can become a never ending problem. Moreover, verification which appears to be complete may actually be incomplete because of undetected issues which can resurface during tape-out or even in the field after fabrication. The most difficult issues to detect and verify are cited to be related to CDC (Clock Domain Crossings). These issues appear when signals in a circuit cross asynchronous clock boundaries without being synchronized. A single CDC issue, if not resolved, can render the whole chip useless. This problem gets enlarged as the number of clocks increases in the design space. In today’s SoC, there can be hundreds of asynchronous clocks driving different IP blocks and complex functions spread across the design.


Example of a Typical SoC Block Diagram

Today, a typical SoC can have billions of gates, multiple power / voltage domains driven by different clocks, while the design can operate in different modes of operations with particular portions of the design being active at different times. Such a design would need a verification methodology defined according to the design implementation and an intelligent solution for complete identification and verification of all CDC issues.

Traditional tools such as RTL simulators or static timing analyzers cannot precisely detect CDC issues. They often end up either under-reporting the real issues or over-reporting false violations, thus wasting a verification engineer’s time. A comprehensive approach is needed that can pin-point the real issues at lower levels and re-use the information at higher levels, thus optimizing the overall verification flow and improving the quality of verification.

Atrenta’sSpyGlass CDC uses a protocol independent analysis technology and provides a comprehensive methodology for CDC verification. Using this software a state-of-the-art structural analysis can be done which uses a suite of rule-sets to verify all kinds of structural CDC issues and avoid any kind of meta-stability. The protocol independent analysis identifies and filters out false negatives upfront, thus saving verification time. It can identify synchronizers such as FIFO and handshake protocols that are properly designed in a generic way. It can also identify signals which can synchronize crossings between clock domains and check if the crossings are functionally correct. The SpyGlass CDC solution also includes functional analysis that complements the structural analysis and ensures proper working of the circuit without any data loss, incoherency, or glitch. The functional checks are done either by using formal verification or simulation.

With these powerful CDC verification capabilities integrated into the SpyGlass Platform, designers have ultimate flexibility to do the verification in multiple ways – flat, hierarchical bottom-up or hierarchical top-down. This flexibility allows designers to handle different situations while designing an SoC which can vary in complexity and size from a few million to more than a billion gates. Again, all IP blocks may not be ready before integration; some of them may be coming from third parties without their functional views. The SoC designer can take appropriate action for the level of verification required for such IP and its interfaces within the SoC. Let’s take a look at the scenarios.

For small SoCs or smaller blocks of IP, the verification can be done in flat mode where the entire SoC is verified in a single run without missing any CDC bugs. The advantage in this case is ease of setup, as all clock modes and design constraints are available at the chip level.

Hierarchical bottom-up CDC verificationis highly scalable and can handle billion gate designs. However, in this case, blocks need to be setup and verified gradually as they are built. The SoC designer works with only CDC-clean blocks, verifies CDC at inter-block interfaces, and then creates an abstracted smart model for this block. In this approach, the verification quality can be ensured by maintaining completeness at each block and its higher level integration, along with coherency of constraints between each block and its top level. Use of these smart models can reduce the verification time and memory footprint by up to 10X.

In hierarchical top-down CDC verification, the constraints are created and driven from the top. This creates the possibility of having the SoC constraints refined early in the design cycle and the ownership of satisfying those constraints goes to the IP or block owners. The verification closure happens gradually as, and when, the blocks become ready. In the case of any third party IP for which the functional view may not be present, the SoC integrator needs to decide whether that IP should be fully verified or partially verified at the boundary.

The SpyGlass CDC verification flow also provides a closed loop between RTL and netlist level verification. At the RTL, substantial structural and functional analysis is done to find all CDC issues. In the netlist, insertion of clock gating, power optimization logic, and other changes may introduce new CDC issues. Therefore, it is mandatory to perform complete structural analysis again at the netlist level. The functional verification is done as required depending upon the fixes implemented during structural analysis. Depending upon the design hierarchy and complexity, it’s important that the verification methodology is defined upfront and that CDC verification be done for the complete SoC in the most optimal manner.

Read a detailed methodology description for CDC verification of billion gate SoCs in a whitepaper here at the Atrenta website. You will need to complete a short registration process in order to download these whitepapers. To get more insight into SpyGlass CDC verification methodology, you can attend an upcoming webinar with the following schedule:

Topic –Signoff Quality CDC Solution for Billion+ Gate Designs
Date/Time – March 19, 2015 4:00pm CET (8:00am PDT) and 10:00am PDT
Registration link –http://www.atrenta.com/events/?series=webinar-series-2015

The SpyGlass CDC verification flow is also tailored for FPGA designs. Atrenta provides a SpyGlass-FPGA-Kit that can be used in a XilinxFPGA-based design to make it Lint and CDC clean. Look for more details in another whitepaper “SpyGlass Lint/CDC Analysis for Xilinx FPGA” here.

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Getting a Grip on the Internet of Things

Getting a Grip on the Internet of Things
by Paul McLellan on 03-12-2015 at 7:00 am
Categories: FPGA, QuickLogic

QuickLogic’s CTO Tim Saxe gave a keynote Getting a Grip on the Internet of Things at the IoT Summit last week.

He started by relating how things have changed over the last 3 years when he talks to customers.

  • Three years ago it was sensor hubs in smartphones and the power budget was 3mW (so one day between re-charging, something we are all well-trained to do).
  • Two years ago it was sensor-hubs with a power budget of 500uW, almost an order of magnitude lower (one month between charges).
  • Then IoT came along and we dropped almost another order of magnitude with enterprise wearables wanting 80uW power budgets, which will last of 6 months or is low enough to make the various energy harvesting approaches workable (so battery life becomes effectively infinite).


In the past systems were primarily built around software. If the processor wasn’t fast enough then up the frequency, if that can’t be done then add more cores, if that can’t be done then add a big FPGA to accelerate some algorithms. This approach is very power hungry and IoT turns everything upside down with the extremely limited power budgets.

Let’s look at what 80uW allows you:

  • accelerometer takes 14uW
  • BlueTooth Smart takes 12uW
  • power management takes 20uW
  • which leaves 34uW for processing

A representative microprocessor takes about 100uA/MHz so you can afford around ⅓MIPS.

BTW a pet peeve of mine. If your processor runs 333K instructions per second then it is ⅓MIPS, not ⅓MIP. The S in MIPS is not making it plural, it is the “second” of “per second”. End of pet peeve.

A basic pedometer takes about ⅓MIPS but anything with more sophistication needs more. Dedicated hardware is too complex to build high-level decision-making on top of. But pure software is too energy intensive. What is required is to move the few energy intensive parts to hardware and everywhere else keep the flexibility of software to get both accuracy and low-power.

Accuracy turns out to be a nebulous concept because more accurate measurements take more power. In fact like the three most important factors in real estate all being location, Tim repeated this three times. But in practice more power means more data lost when the battery needs replenishing, meaning that the power-hungry very accurate pedometer may be outclassed by a less accurate but less power-hungry approach.

A solution to a lot of complicated issues like natural language processing is to use machine learning. This isn’t always appropriate: machine learning is going to kill a lot of pilots and destroy a lot of money before it learns how to fly a plane. But for non-critical applications it is often a superb way to build an application that soon outclasses even the best hand-constructed models.

So Tim wrapped up by going back to reiterate that the IoT requires a change in how we should think about designs. The two big takeaways are:
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  • embrace uncertainty, overall accuracy is more important than point accuracy, and machine learning is a great way to get to answers that are hard to explain in advance
  • when power is critical, putting some functionality into hardware is vital

    Video of Tim’s keynote is available (21 minutes):

    • Posted on

    Cadence’s New Implementation System Promises Better TAT and PPA

    Cadence’s New Implementation System Promises Better TAT and PPA
    by Tom Simon on 03-12-2015 at 1:00 am
    Categories: Cadence, EDA

    On Tuesday Cadence made a big announcement about their new physical implementation offering, Innovus, during the keynote address at the CDNLive event in Silicon Valley. Cadence CEO Lip-Bu Tan alluded to it during his kick off talk, and next up Anirudh Devgan, Senior Vice President, Digital & Signoff Group, filled in more of the details. I was fortunate enough to have a briefing with Anirudh and Cadence Marketing Director Rahul Deokar on Innovus before the public announcement.

    Before I go into the details, I’d like to talk about my experiences with new EDA products. Over the years I have held sales and marketing positions at Cadence and Mentor as well as at smaller companies. In these roles I talked to a lot of customers, and certain themes came up over and over again. The cost of moving to new tools is high; there are risks and the results of moving need to justify the time and effort required. Thus management and engineers will only switch if the benefits are significant, or address a new and otherwise unmanageable design issue.

    Usually new tools offer either a turnaround time (TAT) advantage or an improved quality of result, such as performance, power and area (PPA), but not both. Lastly new products were often announced before challenging real world designs had been thrown at them. Now let’s talk about Innovus.

    Innovus adds a new placer technology called GigaPlace. This rounds out their updated implementation technology by complementing GigaOpt, Tempus and NanoRoute. Placement is crucial for optimal design results. During his keynote presentation even Anirudh telegraphed that they concurred placement was a weak spot for them previously. He has had 2 years to improve on the technology he inherited when he took over the implementation flow.

    In Innovus they are capitalizing on the technology from their Azuro acquisition by incorporating Clock Concurrent Optimization (CCOpt) in the flow. Azuro technology was always strong, but when it was being sold standalone the integration hurdles made for a difficult sale. I know I was there. But with this technology fully integrated with the rest of the P&R flow, using it is much easier. Plus Cadence has polished the useful skew technology that Azuro was starting to roll out at the time of the acquisition. For the clocks, they are using a hybrid approach with H-trees at the higher levels to maintain symmetry, but break out into classic CTS based clocks at lower levels. The portions that are H-tree based help reduce variation induced clock timing issues.

    The other big integration for Innovus is with Tempus, the Cadence sign off solution. Faster sign off is an obvious win with direct database integration. But Anirudh also talked about sign off based ECO’s. These are made more efficient because they can be done without tool iterations.

    Touting what Cadence calls massively parallel computing, Innovus is said to be able to work on much larger data sets and do so much more quickly. One way to gain from this is to take advantage of larger gate counts in blocks. Cadence is saying it works well with 5-10M or more instance block sizes. This reduces the number of blocks, removing channel routing areas and reducing congestion. These larger blocks will run faster in Innovus too. See the table they provided below for their numbers.

    From the chart it seems that there is a bigger win at 28nm than at 16nm, but this is understandable in that 16nm designs have many more constraints, and variation effects grow with additional masks and patterning requirements.

    But what about quality of results? Cadence provided the above chart to show improvement in PPA. One of the most interesting aspects of improved TAT and PPA is that designers might have time to improve their designs beyond specs, if they can reach initial design targets faster and then have more iterations available in the time remaining before tape out. One example Cadence cited shows this being done by one of their beta customers.

    Speaking of beta customers, it seems Cadence has been working with many of their customers on this technology. They are able to point to numerous design examples and have customer endorsements from the likes of ARM, Freescale, Juniper, Renesas, Spreadtrum and Maxlinear. An impressive list indeed.

    Anirudh spoke about how chip companies are no longer easily divided along the lines of Analog or Digital. Today’s SOC’s are predominantly mixed signal. This means that a winning flow will easily allow analog and digital content to be integrated and optimized together. Leveraging Cadence’s strength in analog design, they have added hooks to integrate Virtuoso and Innovus together in the flow. This includes a common database and adds a GUI that uses Tcl for scripting.

    Cadence appears to have addressed the main objection to moving to a new tool – will the change provide sufficient benefit to warrant the cost of moving? They seem have their ducks in a row regarding having enough miles under their belt before rolling out a new major update. ARM in particular talked very positively about their results with Innovus on their high end Cortex-A72 core implementation. And Cadence went to lengths to assure me that even for older nodes, all the technology and PDK information will still work. This means that now not only will this be useful for cutting edge designs, but it will also be helpful on a lot of IoT and mobile based designs that must have the lowest possible power and are implemented on nodes ranging from 180nm down to 40nm.

    For more information go to theCadence Innovus page.