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January 28, 2015

Tabula Closes its Doors

Tabula Closes its Doors
by Paul McLellan on 01-28-2015 at 3:55 pm
Categories: FPGA

I heard a rumor at lunchtime that Tabula was closing its doors. A friend of mine talked to a couple of employees and it is true. They have to be given 2 months notice apparently so the doors don’t actually close until March 24th. I thought they had raised $150M but Wikipedia (not always reliable of course) says $215M. They were one of Intel’s first foundry customers (at 22nm) and Intel capital provided some of that money. It was founded in 2003 by Steve Teig who had been CTO of Cadence. I saw a presentation about the technology at DAC organized by CEDA a couple of years ago.

Tabula had a unique Spacetime 3D FPGA technology but it seemed very hard to master. I heard a couple of years ago that they had needed to do a complete redesign or maybe even two. But the real weakness, I suspect, was the complexity of the software required to program it. The technology is supposed to give a two process node advantage over traditional FPGA approaches.

As the Tabula website puts it:A Spacetime device reconfigures on the fly at multi-GHz rates executing each portion of a design in an automatically defined sequence of steps. Manufactured using a standard CMOS process, Spacetime uses this ultra-rapid reconfiguration to make Time a third dimension. This results in a 3D device with multiple layers or “folds” in which computation and signal transmission can occur. Each fold performs a portion of the desired function and stores the result in place. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function. By rapidly reconfiguring to execute different portions of each function, a 3D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an FPGA, with its inherently 2D architecture.

Obviously taking a standard synthesis flow and making it dynamically continuously reprogram itself at very high speeds sounds like it would be very complex. They have software products to do this, primarily a synthesis tool called Stylus Compiler.

I suspect that the real problem was the red queen problem, that it takes all the running you can do to stay in the same place. By the time they got things working at 22nm they need to be on the node soon, they needed an IP portfolio, I’ve heard the tools were buggy at least a couple of years ago.

RIP Tabula.

January 28, 2015

Opto-Electronics to Take Care of Data Explosion

Opto-Electronics to Take Care of Data Explosion
by Pawan Fangaria on 01-28-2015 at 11:30 am
Categories: Foundries, General, Intel Foundry, Silicon Photonics

As we come nearer to an intelligent IoT world, one of the major concerns we talk every day is about data explosion, its storage, and access and so on. In the beginning of the year, I had blogged about some facts that indicated successful emergence of IoT in very near future. My faith gets further strengthened when I envision the semiconductor world going through another revolution with opto-electronic chips. In the near future, we can see Intel’s photonics technology on top of silicon that can enable high-speed, efficient and reliable data centers without power, heating or space problems in storing and handling Big Data.A LASER (Light Amplification through Simulated Emission of Radiation) is based on Raman Effect, invented by Sir C. V. Raman, an Indian physicist who received Nobel Prize for this discovery in 1930. LASER has been successful in glass fiber. In glass fiber, after travelling several kilometres, the laser beam acquires enough energy to cause a significant amplification of the data signal. Intel’s silicon photonicstechnology is actually a LASER in silicon. The Raman Effect is more than 10000 times stronger in silicon than in glass fiber. In silicon, the distance required is only in centimetres. Also, silicon is most cost effective and requires existing fabrication techniques. Since silicon cannot emit laser light, a waveguide (conduit for light in silicon) is etched into a silicon wafer.The silicon waveguide encountered another problem called ‘two-photon absorption’. In this, two photons arrive at an atom at the same time and the combined energy is enough to free an electron from an atom. At high power densities, the rate of creation of free electrons exceeds the rate of their re-combination with the crystal lattice. The free electrons then start absorbing the light passing through the silicon waveguide, thus diminishing the power of signals. To overcome this problem, the scientists at Intel Photonics Technology Lab inserted a diode-like PIN device in the wave guide that removed the free electrons to produce continuous amplification. Raman Effect was created to amplify the light as it bounced between two mirrors coated on the ends of the waveguide, thus producing a continuous laser beam at a new wavelength. This formed the breakthrough silicon laser. Look for more details in a whitepaper at Intel Photonics Lab website.Silicon laser alone was not enough, other components such as high-speed silicon modulators and silicon photo-detectors were developed. A chip can have multiple hybrid silicon lasers at different wavelengths and each modulated at say 50 Gbits/s. A silicon multiplexer can then combine all signals into a single optical fiber. At the other end of the fiber, another chip can have detectors to convert the optical signal from each laser back into electronic signal. At IDF 2013, Dr. Mario Paniccia, Director of Intel Photonics Technology Lab demonstrated a transceiver based on photonics technology, operating at 100 Gbits/s. Justin Rattner, CTO of Intel at that time, said that Intel has fully automated test technology for such photonic wafers that combines electrical, optical or RF test. It uses microscopic lenses to read optical signals.Fujitsuworked with Intel to demonstrate Optical PCI Express (OPCIe) server, which was enabled by Intel’s silicon photonics technology. It solves power and heat density problems which occur in Rack-based servers due to space and power constraints. Signals over optical fibers can go much longer compared to copper signals. Look for details about this prototype at Intel website here.Looking at these working devices, it’s certain that silicon chips will have another revolution to add optics into them. I am calling these as opto-electronic chips that can enable very high-speed, low latency connections and high storage in the cloud as demanded by the upcoming semiconductor market in the near future. I can envision this technology in main stream chip production sooner than later. Does it ask for another Nobel Prize for Intel scientists? In my view it could, provided it fulfils the larger need of high-speed computing, storage and access without too many issues as seen in copper wires. The cost must be affordable because silicon is always low cost compared to other materials for such use. Comments welcome!

January 28, 2015

Altera Back to TSMC at 10nm? Xilinx Staying There

Altera Back to TSMC at 10nm? Xilinx Staying There
by Paul McLellan on 01-28-2015 at 7:00 am
Categories: FinFET, FPGA, Xilinx

Xilinx announced their quarterly results last week. They slightly missed their number due mainly to a decline in wireless sales. Of course Xilinx parts don’t go in the smartphones since the cost and power are too high, but they are very heavily used in basestation, backhaul etc especially in China. Xilinx’s business in China has been historically limited by a slower buildout to a shortage of parts (not the Xilinx parts but power amplifiers). That problem seems to have gone away and their China business is on track and the weakness is in the rest of the world.

As always here at semiwiki it is interesting to use the FPGA market to get insight into the foundry roadmaps.

As Moshe said on the call:We also achieved several important milestones for our 20-nanometer portfolio. Our Kintex UltraScale devices became the industry’s first 20-nanometer FPGAs to move into volume production. Based on customer feedback, we continue to believe that we have an estimated one-year lead over the competition. This technology leadership is complemented by our Virtex UltraScale family, which is the industry’s ASIC class 20-nanometer high-end product offering. It’s a very high-end of this family, we began shipping the industry’s largest FPGA which delivers over 4x of the capacity of any competitive devices.

With regards to 16nm, they are a couple of months behind schedule. The problem is on the design end at Xilinx themselves and doesn’t appear to be due to any changes on the TSMC side. Moshe said that they should tape out in May:Okay. So there are no issues with TSMC, they have had numerous tape outs already, they are giving us full support. The design whenever you encounter a new generation of product tends to unearth problems that you did not anticipate and as a result the closing of all of these issues is taking a little longer plus the challenges related to design for FinFET transistors are more significant. So it’s not a TSMC challenge or issue at all, it’s just our ability to finish the design with their support. After if you look at our business typically what sort of happens is tape it out, you get it back after a few months, you go through a lengthy evaluation cycle and then you move it into production at which point in time it takes two to three years until it reaches high volume production.

Meanwhile Altera also had an earnings call. As you probably know they use TSMC for 20nm and above but switched to Intel 14nm (which is what TSMC calls 16nm for Chinese reasons). They are seeing a lot of the same slight weakness in end-user markets. John Daane, the CEO, said that they were also a couple of months late taping out in 14nm:Let me start with 14-nanometer. Our original schedule was to tape-out in first calendar quarter, we’re running a couple of months late to that and are actively working to pull that in but worst case, we will sample this fall so we are still definitely in this year.

He also reckons that in the Intel process which has tighter pitches than TSMC that they will get a 25% area savings which is less than the original thought of 35%. But the bombshell was about 10nm:Question: You talked about 14-nanometer, have you guys made any decision on your foundry choice for 10-nanometer?
We have not made that decision. We have told both, Intel and TSMC, who are working with on the technology that will likely make a decision before the end of the first calendar quarter.

So Altera could go back to TSMC for 10nm. Of course this might all be a negotiating strategy for better wafer prices but switching to Intel for just one process generation would be unusual.

Seeking Alpha transcripts: Xilinxand Altera

There is a Semiwiki forum discussion on this here.

January 28, 2015

Qualcomm versus Samsung?

Qualcomm versus Samsung?
by Daniel Nenni on 01-28-2015 at 3:00 am
Categories: Foundries, Mobile

There is an interesting reality show playing in the media featuring Qualcomm and Samsung with supporting actors TSMC, LG, Xaomi, and Apple. As I’m sure we all have read, Samsung is losing massive amounts of money on mobile which was once a very profitable business unit. Let’s take a look at the current landscape and some of the recent headlines to try and make sense of this thing. Sound like fun?

According to IDC the worldwide smartphone market hit close to 1.3 billion units in 2014. According to the world population clock there are more than 7.2 billion people on planet Earth with a net gain of one person every 16 seconds. Let’s also put the average smartphone replacement cycle at every two years. Smartphones are now an integral part of our quality of life so the market for the SoCs that power smartphones will continue to grow rapidly for many years to come, absolutely.

[TABLE] cellspacing=”3″
|-
| 1. China
| 1,361,512,535
| 6. Pakistan
| 199,085,847
|-
| 2. India
| 1,251,695,584
| 7. Nigeria
| 181,562,056
|-
| 3. United States
| 321,362,789
| 8. Bangladesh
| 168,957,745
|-
| 4. Indonesia
| 255,993,674
| 9. Russia
| 142,423,773
|-
| 5. Brazil
| 204,259,812
| 10. Japan
| 126,919,659
|-

Samsung still holds the number one position in the smartphone market but for how much longer? Samsung mobile posted negative numbers in 2014 and this year looks even more challenging. Apple is number two and gaining market share on the success of the iPhone6 and 6+. Xiaomi is now number three thanks to the China market and is rapidly expanding into India and other densely populated countries excluding the United States. Lenovo (including Motorola Mobility) is a strong number four and LG is fifth.

In regards to the SoCs inside these phones, QCOM, MediaTek, and Apple control the market with 80-90% market share depending on whom you believe. In 2014 the majority of these SoCs were 28nm from both TSMC (QCOM and MDTK) and Samsung (Apple iPhone5). At the end of last year Apple started shipping TSMC 20nm (iPhone6) and in 2015 SoCs will be a mix of 28nm, 20nm, and 14nm.

Having worked with Samsung in the past I can tell you they are a fierce competitor that knows no bounds so I find it highly unlikely that they will abandon the mobile market. I also find it highly unlikely that they will participate in a market that they cannot win so what is Samsung to do?

[LIST=1]

Pressure Qualcomm by rumoring that the Snapdragon 810 (TSMC 20nm) has heating problems? I spoke with friends inside QCOM when the story first broke and was told it would be proven false.While Samsung blamed the delay of the Galaxy S6 on QCOM, LG and Xiaomi released phones using the identical SoC with no reported problems.

As I mentioned before QCOM will use Samsung’s 14nm process but now I must ask: Is there more to this story? Will the QCOM 14nm SoCs be made available to all smartphone vendors or just Samsung? QCOM will also use TSMC’s 16nm FF+ so maybe this is the real reason for the split?

Have QCOM take over Exynos and develop the chips for Samsung? This would be my recommendation.

Bottom line: I see the foundry business as playing a key role in the competitive battle amongst the mobile vendors and the SoC makers may be forced to choose sides.

January 27, 2015March 22, 2022

DNA Sequencing Eyes SoCs for Stability and Scale

DNA Sequencing Eyes SoCs for Stability and Scale
by Majeed Ahmad on 01-27-2015 at 9:00 pm
Categories: Cliosoft, EDA

DNA sequencing — which provides vital information on genetics study, forensics, diagnostics and therapies — has been an exclusive territory of high-end research labs with millions of dollars to spend because of the expensive chemical and optical equipment needed for research. That is changing, thanks to complex integrated circuits, a.k.a. systems-on-chip (SoC), which are overcoming cost and technical hurdles to bring the price of human DNA sequencing to US$ 1,000 or less with the eventual goal of reaching US$ 100.

Although DNA sequencing technology based on semiconductor products is still in an embryonic stage, single-chip solutions clearly seem its best hope. Take DNA Electronics (DNAe), for instance. The London-based (UK) firm has embedded the whole diagnostic process on a single chip to sidestep the need for measuring optical signals or using lasers and microscopes. The lab-on-a-chip — as the company founder Christofer Toumazou likes to call it — is a fusion of semiconductors and sensors that uses very small amounts of chemicals to conduct tests on the spot.

DNAe’s lab-on-a-chip that can be inserted into a USB stick

Toumazou claims that this single-chip device — built around the company’s Genalysis platform — can be inserted into a USB stick and that it will provide results that are viewable on a computer within 20 minutes. “Genalysis can perform both PCR (for speed) and sequencing (for content) on the same chip in the same analysis, to arrive at a fast, accurate and informative diagnosis.”

According to the European Patent Office data, by 2016, the DNA sequencing market is expected to be worth US$ 6.6 billion and will grow by 17.5 percent annually. But this era of personalized medicine will require highly complex SoCs and ultra high-tech semiconductor tools in order to turn the chemical information of the DNA into a change in the electrical signal.

How it Works

DNA sequencing determines the order of nucleotides (building blocks of DNA) in a DNA strand, which provides scientists valuable information and serves as the basis for diagnosis of diseases, detection of genetic predispositions to diseases, etc.

In all living organisms, a hydrogen ion is released when DNA strands are extended by a nucleotide, the individual chemical bases of the DNA (known by their abbreviated letters of A, C, T or G). The game-changing technology of DNA sequencing requires signals that are sensitive enough to detect tiny amounts of DNA (nanomolar concentrations). When a signal current is passed through the nanopore (a very small hole created in synthetic materials like silicon), it causes a spike in the current unique to each chemical base (A, C, T or G) within the DNA molecule.

The human DNA set or genome is already mapped, and the order of genetic mutations is known; so a pre-set sequence of nucleotides can be designed that matches genetically mutated ones. Once the target matches, it releases many hydrogen ions, which in turn is detected by the chip. The DNA sequencing is a matrix of hundreds of tiny wells, each well containing a fragment of the subject DNA.

The crossroads of biology and physics is going to be a challenge for the DNA chip developers in their bid to sequence single DNA molecules. But they are steadily overcoming these challenges related to signal accuracy and stability through innovative design and manufacturing techniques and a variety of SoC tools. That’s partly because there is an increased use of semiconductor technology in non-traditional markets like biotechnology.

For instance, Genia Technologies — acquired by Swiss drug giant Roche in June 2014 — is developing a nanopore sequencing technique that is based on a mix of SoCs and NanoTag chemistry. Genia’s NanoTag sequencing technique, developed in collaboration with Columbia University and Harvard University, uses a DNA replication enzyme to sequence a template strand with single-base precision as base-specific engineered tags cleaved by the enzyme are captured by the nanopore.

Schematic of a single molecule DNA sequencing by a nanopore with phosphate-tagged nucleotides

Genia’s SoC-based solution bypasses specialized, expensive optical sensors while detecting changes in electrical current through chips that aim to be as inexpensive as the ones found in mobile phones, PCs and other consumer electronic products.

The GENIUS system of GenapSys marks a shift from optics to electronics

SoC tools to the rescue

GenapSys Inc., the Redwood City, California, based chipmaker that provides DNA sequencing solutions, has been, like Genia Technologies and DNAe, using SoC-centric data management solutions such as ClioSoft’s SOS for handling analog, digital and firmware parts of its GENIUS sequencing chip. ClioSoft’s SOS data and IP management platform is a hardware-centric system that streamlines design flows and helps design teams collaborate more efficiently to ensure project timelines are met.

Like many SoC device makers, GenapSys doesn’t do all of its development at a single site, but it hosts all the data on a single server. “A lot of ClioSoft technology is tightly integrated into Cadence’s Virtuoso custom IC flow, so it’s not necessary to spend a lot of time interfacing directly with ClioSoft tools,” said Hamid Rategh, VP of engineering at GenapSys. “Like many SoC designs, the GENIUS sequencing chips of GenapSys use Virtuoso’s analog design environment.”

ClioSoft SOS is closely coupled up with EDA tools and syncs-up analog, digital and firmware parts of an SoC

Rategh added that ClioSoft links the whole work area, and that makes a big difference to the amount of disk space required. “You would think this would be less of a problem, with disks continuing to get cheaper, but management overhead for backups is still an issue.”

The GenapSys example shows that tools like Cadence Virtuoso coupled with ClioSoft’s SOS design management platform can bring necessary impetus to the DNA sequencing SoCs in their bid to bring stability and scaling to semiconductor-based solutions and eventually to bring down the costs of next-generation DNA sequencing technology to affordable levels.

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronicsand The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

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January 27, 2015

Xilinx ships the VU440 and its 4M logic cells

Xilinx ships the VU440 and its 4M logic cells
by Don Dingee on 01-27-2015 at 8:00 pm
Categories: FPGA, Xilinx

Xilinx has delivered not only “the biggest FPGA on the planet”, but what it claims is currently the world’s largest integrated circuit: the Virtex UltraScale VU440, with 19 billion transistors fabbed in TSMC 20nm. The list of first customers to receive parts says a lot about the state of SoC design today, and the vital role FPGA-based prototyping and hardware-aware synthesis plays.

Fabs love massive FPGAs to prove out sophisticated process nodes. Around the periphery, there is certainly some magic with high-speed SERDES transceivers and other interfaces. The interior is where scale lives. Laying down a sea of equally sized logic cells in an interconnect fabric is ideal territory for fabs to show their process can maintain planar consistency across space and environmental variables.

The VU440 has 4,432,680 of those logic cells, along with 88.6Mb of block RAM, 1404 single-ended HP and 52 single-ended HR I/Os, three 100G Ethernet ports, and 48 GTH 16.3 Gbs transceivers among other features. Its package is a marvel unto itself: a 55x55mm flip chip BGA with 2892 pins, with 3D techniques including stacked silicon and 600,000 micro bumps. Getting that all in a part, and getting that part reliably attached to any board, is just plain amazing.

What does one do with something this big? Xilinx cites some top-of-pyramid applications: digital array radar, LTE-A wireless, 8K Ultra HD broadcast video, and 1Tb/sec optical transport networks. Performance is welcome, however not all of these applications need this many logic cells. Currently, six smaller UltraScale parts with similar features fill those requirements just fine. Single board computing vendors, who used to be the prove-out platform for large FPGAs, are probably going to be content at smaller capacities and lower price points.

Where capacity still can outstrip FPGA state-of-the-art is SoC design. 4M logic cells translates to roughly 50M ASIC gates. This fits a lot of things. In an introductory video, Xilinx shows just such an example: a Xilinx AFX board with a single VU440 holding a cluster of 10 ARM Cortex-A9 cores. It is filled to the brim: 94% of CLBs, and 77% of LUTs are used. The ten CPU cores are running at 50 MHz. While a demo system, it illustrates the potential.

Among other improvements, Xilinx spent a lot of time completely revising the clocking scheme in UltraScale, making it more ASIC-like with respect to how slice boundaries are dealt with. They also improved routing the routing architecture and logic cell packing. Even with these improvements and the massive resources of the VU440, current SoC designs are often far bigger than 50M gates, and RTL has to be partitioned across multiple FPGAs.

Synopsys was among the first to receive VU440 parts, and is working on an even bigger version of the HAPS prototyping platform. As we explored in a recent post on prototyping the Imagination PowerVR Series6XT, having a big enough gate pile to hold logical partitions of a design is the start. Synopsys ProtoCompiler performs hardware-aware synthesis, using constraints defining FPGA and board-level resources such as interconnect and multiplexing. When they get their arms around the UltraScale architecture, and leverage the VU440 capability fully in synthesis, designers will have incredible capability.

Of course, there is still the old school of “manual” tool-assisted partitioning. Some designs are cleanly separable. Capability of Xilinx Vivado Design Suite for tasks like partitioning continues to improve. Some designers like the control, and the challenge. Another FPGA-based prototyping system vendor, The Dini Group, also has VU440 parts in house. In an homage to just how far we have come in being able to cut large and unruly ASIC designs into manageable pieces, they have proudly dubbed their newest prototyping engine as “Godzilla’s Butcher on Steroids.”

For more information on the VU440, and to launch the full video, see the Xilinx press release:

Xilinx Delivers the Industry’s First 4M Logic Cell Device, Offering >50M Equivalent ASIC Gates and 4X More Capacity than Competitive Alternatives

Scalability, as the name implies, is central to the Xilinx UltraScale strategy. The shipment of the VU440 is a stunning accomplishment, one likely to be unmatched for a while. We seem to have arrived at a point where the practice of FPGA-based prototyping is ready for prime time. The costs of committing to silicon without complete hardware and software co-verification, and rapid changes leading to retesting, are too big to risk. The capacity of the VU440 applied to FPGA-based prototyping should bring in more developers.

January 27, 2015

Shorten the Learning Curve for High Level Synthesis

Shorten the Learning Curve for High Level Synthesis
by Daniel Payne on 01-27-2015 at 4:30 pm
Categories: EDA

When chip designers moved from a gate-level design methodology to coding with RTL there was a learning curve involved, and the same thing happens when you move from RTL to High Level Synthesis (HLS) using C++ or SystemC coding. One great shortcut to this learning curve is the use of pre-defined library functions. I just heard about a new library of 1D signal processing hardware ready to use in an HLS flow from Calypto:

The library is called CatWareand you get a set of filter and FFT models that can be customized with parameters and then synthesized using the Catapult tool. Some designers prefer to use C++, while others are attracted to SystemC, either way the CatWare libraries support both languages. You add these library models to your C++ or SystemC source code, and then set the parameters, like:

Input precision
Output precision
Number of stages
Number of taps
Architecture

During synthesis with Catapult is where you constrain the design to use a specific technology and define the clock frequency. Because you are receiving the source code for each library, you can even change it to better meet your needs or create derivatives.

Each of the CatWare models has been run through a set of regression tests, so you’ve got something that has been verified in Simulink, C++ and RTL simulations already. Two extra verification techniques are also used: assertion synthesis and SLEC C property checking, helping to verify consistent behavior through synthesis.

Here’s what you get in the FFT library:

[TABLE] style=”width: 100%”
|-
| Catware FFT Blocks
| Radix 2 Fixed Point DIT
|
| Radix 2 Fixed Point
DIF
|
| Radix 2^2 Fixed
Point DIF
| Mix Radix Fixed Point
(2 and 2^2) DIF
| Configurable
Radix Fixed Point DIF
|-
| Supported Architectures
| Single Delay
Feed-back
| In Place
| Single Delay
Feed-back
| In Place
| Single Delay
Feed-back
| Single Delay
Feed-back
| In Place
|-
| Synthesizable C++ Model
| √
| √
| √
| √
| √
| √
| √
|-
| Synthesizable SystemC Model
| √
| √
| √
| √
| √
| √
| √
|-
| Simulink Model
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Bit Precision
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Stage-wise Scaling
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable FFT Point
| √
| √
| √
| √
| √
| √
| √
|-
| Streaming Interfaces
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Delay Buffer Impl.
(Register/Memory)
| √
| NA
| √
| NA
| √
| √
| NA
|-
| Constant Twiddle Implementation
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Radix
| NA
| NA
| NA
| NA
| NA
| NA
| √
|-
| Option to Mix Radix
| NA
| NA
| NA
| NA
| NA
| NA
| √
|-
| Configurable Output Oder
(Natural or Bit-Reversed)
| X
| X
| X
| X
| X
| X
| √
|-
| C++ Interface Synthesis
| √
| √
| √
| √
| √
| √
| √
|-
| Multiview IO – HLS/TLM
| √
| √
| √
| √
| √
| √
| √
|-

For filters, the CatWare library has:
[TABLE] style=”width: 100%”
|-
| Catware Filter Blocks
| FIR Constant Coefficient
| FIR Programable
Coefficient

| FIR Loadable
Coefficient

| CIC Interpolator
& Decimator

| Moving
Avergage

| Integrate
& Dump

| Poly Phase Interpolator
& Decimator
|-
| Supported
Architectures
| Shift Register Circular
Buffer Rotational Shift
Folded – Even Taps
Folded – Odd Taps
Transpose
| Shift Register Circular
Buffer Rotational Shift
Folded – Even Taps
Folded – Odd Taps
Transpose
| Shift Register Circular
Buffer Rotational Shift
Folded – Even Taps
Folded – Odd Taps
Transpose
| Limited
Precision^
Full Precision
| 1D
Windowing
| NA
| NA
|-
| Synthesizable C++
Model
| √
| √
| √
| √
| √
| √
| √
|-
| Synthesizable SystemC
Model
| √
| √
| √
| √
| √
| √
| √
|-
| Simulink Model
| X
| X
| X
| √
| √
| X
| √
|-
| Multi-Channel Support
| X
| X
| X
| √
| X
| √
| X
|-
| Configurable Bit-Widths
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Rate
| NA
| NA
| NA
| √
| NA
| NA
| √
|-
| Configurable Number
of Taps
| √
| √
| √
| NA
| NA
| NA
| √
|-
| Streaming Interfaces
| √
| √
| √
| √
| √
| √
| √
|-
| Configurable Window
Type (Clip or Mirror)
| NA
| NA
| NA
| NA
| √
| NA
| NA
|-
| Configurable
Differential Delay
| NA
| NA
| NA
| √
| NA
| NA
| NA
|-
| C++ Interface Synthesis
| √
| √
| √
| √
| √
| √
| √
|-
| Multiview
IO – HLS/TLM
| √
| √
| √
| √
| √
| √
| √
|-

Summary

Give HLS a try on your next DSP design, and shorten your learning curve by using parameterized libraries for filters and FFT functions. This approach is sure to save you many days of engineering effort compared to starting from scratch.

January 27, 2015June 14, 2019

Sigrity Focuses on LPDDR4 Compliance Analysis in 2015 Release

Sigrity Focuses on LPDDR4 Compliance Analysis in 2015 Release
by Tom Simon on 01-27-2015 at 10:00 am
Categories: Cadence, EDA

It was back in July of 2012 that the acquisition of Sigrity by Cadence was announced. Although Cadence is a dominant player in both IC and board layout tools, they did not have an electromagnetic (EM) signal integrity solution in their portfolio. This acquisition marks a turning point for the EM/SI sector – tight integration into the design flow is now exceedingly important for designers. As always there is a lot of anticipation to see how things go after a smaller technology company is brought in under the wing of a larger player.

Cadence is announcing the features in the new 2015 release of Sigrity at DesignCon this week. This is an ideal time and place for the announcement. DesignCon is a leading event in the board design space. The tag line for DesignCon is “where the chip meets the board”. With that in mind, the main features of the Sigrity 2015 release are right on target. Of the things intheir press release, the one that jumps out is added support for analysis and qualification of designs using the newLPDDR4 high-speed low-power memory interface standard.

The driver for this is the growth of mobile devices – more data and more graphics. According to a presentation at Mobile Forum 2013 by Samsung’s JungYong Choi, data traffic on PCs will grow by only 2X from 2012 to 2017, but smartphone data traffic will grow 8X in the same timeframe. Concurrently, higher resolution displays on mobile devices are also driving bandwidth. UHD needs 9X the bandwidth than HD does.

The JEDEC specification for LPDDR4 came out in August of 2014. Not only is it a faster interface standard, but it uses less power. Power is reduced by lowering the operating voltage from 1.2V in LPDDR3 to 1.1V in LPDDR4, Significant power is also saved by using Low Voltage Swing Terminated Logic. This uses a signaling voltage of around 400mV, 50% lower than the previous LPDDR3. Transmitting a ‘0’ requires almost no current. To save even more power DBI is used to invert the data bits when a byte has more ‘1’s than ‘0’s. Overall LPDDR4 is said to use 40% less power than LPDDR3.

LPDDR4 runs at 3.2B transfers per second; at the bus level that translates to a bandwidth of 25.6GB/s (2ch). The bus is divided into 2 parallel 16 bit buses with their own clocking to help improve signal line layout and avoid skew issues.

With low swing voltage and higher operating frequency comes the need for added diligence on interconnect to memory chips. Signal traces need to be analyzed to ensure that they do not contribute to excessive bit error rates. According to Brad Griffin, Product Marketing Director at Cadence, trace geometry and ground plane structure affects signal integrity and needs to be modeled and simulated to understand how the whole system will operate. Also ground bounce and power rail integrity will have a dramatic effect on LPDDR4 compliance.

Sigrity 2015 not only provides modeling for board and package interconnect, but can simulate the system using its power aware system signal integrity feature to ensure that the bit error rate complies with the specification. Sigrity ties into package level simulation and up through chip level models that can be generated in the Cadence suite.

Looking at things from a system perspective, it seems that Cadence is well positioned to leverage its entire flow to help validate and qualify designs from on-chip all the way to the board and system level. After all, things will only get more complicated. The next revision of the LPDDR4 spec will go from the present 3200 MT/s to 4266 MT/s, a much higher transfer rate. Griffin expects channel equalization to become a necessity before long. If so, this will add the requirement to model equalization algorithmically to perform end to end qualification.

I look forward to visiting the Cadence booth at DesignCon this week to learn more about Sigrity 2015.

January 27, 2015

FPGA vendor to buy IC vendor Silicon Image

FPGA vendor to buy IC vendor Silicon Image
by Eric Esteve on 01-27-2015 at 9:35 am
Categories: FPGA, IP

Interesting news today : Lattice Semiconductor, FPGA vendor is buying Silicon Image. In fact, Silicon Image is a chip vendor, but also an innovator, licensing well known IP like HDMI, MHL and more. If we consider the amount paid for Silicon Image ($600 million), compared with the last full year revenue, $276M in 2014, that’s a 2.2X multiplicator… not really a success story for Silicon Image !

I am following the company since 2007, as I wanted to understand the SATA IP market and Silicon Image was the #1 with 80% market share or $16M on a $20M market. Thus I have continued to look at the company, as HDMI technology was starting a penetration which is today at 100% in many segments like PC or TV, and very strong in adjacent segments like Mobile. At that time Silicon Image was credited to (almost) 100% on the HDMI IP segment, no surprise.

You can take a look at the above results, you will see that the company was healthy, and growing fast between 2005 and 2007, passing from $212M to $320M in two year, which is more than 50% growth ! But if you look at the results for the last three years (below) you will see that none of the annual revenue is surpassing this made in 2007 :

So what’s has happened to Silicon Image ?

Looking at the company behavior through the prism of IP, we can say that Silicon Image has been a real innovator, inventing HDMI (after DVI). HDMI was a true revolution in the consumer market, as you can transfer Image through a serial high speed link, and that’s make a real difference ! Just try to use that we call a « Peritel » in France, a parallel link and you will jump to buy an HDMI cable.

Along with the patent, silicon Image has created the « HDMI Licensing LLC » to collect the royalties, 4 cent per HDMI port.

On top of HDMI Licensing LLC, Silicon Image has created the Authorized Test Center (ATC) policy : « The HDMI Founders have established Authorized Testing Centers (ATC) where licensed manufacturers can submit their products for compliance testing. Upon successful compliance testing, take advantage of the HDMI Product Finder to promote your Fully-Compliant products.” Good idea? Certainly for Silicon Image, as their direct competitors had to pass by these ATC to have the right to put the “HDMI” Logo! Such a policy can be a good way to accelerate Silicon Image time-to-market… or slow down competitor release.

From informal discussion that I had with application processor chip makers integrating HDMI –and paying the royalties to HDMI Licensing, it seems that these chip makers were upset by Silicon Image. Arrogance is not a guarantee of success…

To come back to the IP business, Silicon Image was making $50M with licensing in 2007 (SATA + HDMI + DVI) but around $44M in 2013 (replace DVI by MHL). On a product family (Interface IP) exhibiting 10% CAGR between 2007 and 2013, this is clearly a counter performance. To make a comparison, on the same products (SATA and HDMI) an IP vendor like Synopsys has made $5M in 2007, but $25M in 2013!

We can’t explain everything by only looking at the IP revenue evolution, but it’s clear that Silicon Image had some nuggets like HDMI in their port-folio, a good strategy back in 2007, and has failed to continue on the long term and develop new technologies, or new market. That’s why Silicon Image revenue has been 20% less in 2013 than in 2007, that’s the reason why Lattice has acquired the company for 2.2X the yearly revenues…

Eric Esteve from IPNEST

January 27, 2015June 14, 2019

ANSYS Talks About Multi Physics for Thermal Analysis at DesignCon

ANSYS Talks About Multi Physics for Thermal Analysis at DesignCon
by Tom Simon on 01-27-2015 at 9:00 am
Categories: Ansys, Inc., EDA

ANSYS makes a big deal of being a multi-physics company. Still it has taken them a while to fully integrate Apache. Nevertheless it seems like there is a compelling argument for combining technologies to solve SOC design problems. Frankly most chip designers would be hard pressed to think of a reason for using computational fluid dynamics (CFD). However it turns out that there is good reason to use it when looking at a comprehensive solution for determining electromigration.

ANSYS’s Ravi Ravikumar shared with me some slides that they are using atDesignCon this week in Santa Clara which outline the flow for thermal analysis of contemporary system designs, such as cell phone processors and other SOCs. Their flow accounts for cases where 3D ICs are used as well. The thing that stands out is that unless you understand the chip in detail along with the environment it is in, including interposer, package, board and cooling regime, you cannot come up with good thermal data – for example like what is needed to determine electromigration effects.

Sources of self heating include dynamic and static device power, as well as on-chip interconnect, bumps and PCB interconnect. Interconnect power consumption goes up linearly with temperature. The real problem is leakage or static power dissipation. We all know at advanced nodes leakage power has grown as a percentage of overall chip power. What is important for electromigration analysis is that leakage power is temperature dependent, dramatically increasing with temperature. So really we cannot talk about how much power the chip is dissipating until we know the temperature. This is where it starts to get interesting.

Until we take first-cut power numbers and propagate them from the chip to the interposer, through the package, board and whatever thermal environment the board is in, we can’t get to the actual power numbers. In fact, once we update the power numbers, we will have new self heating data to propagate again through this flow. It turns out to be an iterative process that eventually will converge. However it requires a tool chain that can accurately calculate results for each level of the design.

In the ANSYS flow here is what this looks like. At the chip level, their Chip Thermal Model (CTM) produced by Totem and/or Redhawk breaks each layer of the chip into small squares and characterizes them at several different temperature points for power consumption. This includes devices and all interconnect layers. With initial temperature information, this can be used by the iterative flow described below to predict power dissipation – leading to better temperature numbers. The chip level information is fed to Sentinel-TI which can take the CTM models to make more compact models that contain thermal information for the die.

Sentinel-TI predicts the thermal behavior of the package. Next we have to consider power dissipation on the board. ANSYS SIwave is used for this purpose. However, unless the housing and external cooling is accounted for these numbers don’t mean anything. This is where ANSYS Icepack comes in with the computational fluid dynamics. You were probably wondering when this was going to get brought up again. Icepack looks at things like airflow and heat transfer in the board housing – i.e. cell phone chassis.

It should be mentioned that different chip thermal models are produced for different modes of operation of the chip. Clearly the power consumed by a chip depends on activity information. Viewing a video will consume much more power than reading email, for instance. The ANSYS flow can accommodate different modes of operation and can even give information about temperature rise given certain usage profiles, such as busts of higher compute intensive usage, etc.

Delving in further there are internal issues in interposer designs that require rigorous analysis. Heat will flow from internal source through the microbumps and/or interposer to get to the exterior of the package. For example, when there are TSVs, there will be metal on the back side of the substrate. This will affect thermal flux. Sentinel-TI can analyze for these and many other cases.

Getting back to the reliability issues related to properly analyzing for electromigration, this flow looks to do a much better job than using guidelines that do not include accurate operating temperature information. Below is a graphic showing calculated electromigration effects with and without consideration of on-chip operating temperature.

ANSYS makes a strong case for using multi-physics for analysis of semiconductor designs. One would be hard pressed to think of another company that can provide a solution that combines such breadth of analysis in solving these tough design problems.

I expect the DesignCon presentation to go into much more detail than I have been able to cover here.