I heard a rumor at lunchtime that Tabula was closing its doors. A friend of mine talked to a couple of employees and it is true. They have to be given 2 months notice apparently so the doors don’t actually close until March 24th. I thought they had raised $150M but Wikipedia (not always reliable of course) says $215M. They were one of Intel’s first foundry customers (at 22nm) and Intel capital provided some of that money. It was founded in 2003 by Steve Teig who had been CTO of Cadence. I saw a presentation about the technology at DAC organized by CEDA a couple of years ago.
Tabula had a unique Spacetime 3D FPGA technology but it seemed very hard to master. I heard a couple of years ago that they had needed to do a complete redesign or maybe even two. But the real weakness, I suspect, was the complexity of the software required to program it. The technology is supposed to give a two process node advantage over traditional FPGA approaches.
As the Tabula website puts it:A Spacetime device reconfigures on the fly at multi-GHz rates executing each portion of a design in an automatically defined sequence of steps. Manufactured using a standard CMOS process, Spacetime uses this ultra-rapid reconfiguration to make Time a third dimension. This results in a 3D device with multiple layers or “folds” in which computation and signal transmission can occur. Each fold performs a portion of the desired function and stores the result in place. When some or all of a fold is reconfigured, it uses the locally stored data to perform the next portion of the function. By rapidly reconfiguring to execute different portions of each function, a 3D Spacetime device can implement a complex design using only a small fraction of the resources that would be required by an FPGA, with its inherently 2D architecture.
Obviously taking a standard synthesis flow and making it dynamically continuously reprogram itself at very high speeds sounds like it would be very complex. They have software products to do this, primarily a synthesis tool called Stylus Compiler.
I suspect that the real problem was the red queen problem, that it takes all the running you can do to stay in the same place. By the time they got things working at 22nm they need to be on the node soon, they needed an IP portfolio, I’ve heard the tools were buggy at least a couple of years ago.