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Silvaco Swallows Invarian

Silvaco Swallows Invarian
by admin on 03-20-2015 at 7:00 am
Categories: EDA

Yesterday, Silvaco announced that it has acquired Invarian Inc. Details of the transaction were not disclosed.

Who is Invarian? They are a recognized leader in block-level to full-chip sign-off analysis for complex, high-performance ICs. Their unique methodology utilizes a parallel architecture and concurrent power-voltage-thermal analysis to provide engineers with fast, accurate, and consistent results from the gate level through the 3D package environment.

Invarian has several products, all under the InVar umbrella name:

  • InVar Pioneer Power, power analysis platform for custom and standard cell based designs
  • InVar Pioneer IM/ER, full visibility of supply networks from top-level connectors down to each transistor
  • InVar Pioneer Thermal, the industry’s largest capacity and most accurate thermal sign-off analysis
  • InVar Pioneer Macro Modeling, hierarchical modeling to enable fast full-chip analysis while maintaining true to life accuracy from IP and blocks to top-level design
  • InVar Frontier 3D Thermal, static and transient thermal simulator based on the variable splitting method for efficient prediction of temperature distribution for 3D ICs

Having great technology is a good start but on its own it is not enough, foundry support is also important, and given its gorilla status nowhere is as important as TSMC. The InVar product family is TSMC certified for 20nm and 16FF+ v0.9 to enable sign-off analysis accuracy for static & dynamic IR drop analysis and EM verification, and the collaboration is on-going to conclude 16FF+ v1.0 certification.


My old Cadence colleague Suk Lee, now TSMC’s Senior Director of Design Infrastructure Marketing said:TSMC and Invarian have collaborated to ensure that customers have confidence when they perform EM or IR-drop analysis. We look forward to continuing this collaboration with Silvaco with our advanced process nodes.

Today I met with Dave Dutton, Silvaco’s CEO. One piece of trivia I learned is that the Silvaco name was never intended to be the permanent name of the company, it just stands for “silicon valley company” and is not some clever acronym involving simulation, layout and verification. But company names are not always very deep: Apple was supposedly so-named primarily to be alphabetically ahead of Atari.

Another thing he told me is that after several years of absence Silvaco is going to be back at DAC with a 600 square foot booth (#532 for those of you making really early plans). It is no secret that Silvaco’s founder Ivan Pesic, before his unfortunate death, was not really a believer in marketing (except billboards) and as a result Silvaco’s visibility in the industry is a lot less than it should be for a company of their size. Some people are surprised to discover that they even still exist, let alone that there are market segments in which they are the leader. Amit Nanda, the VP marketing, joined us in the meeting: it is his job to change that perception.


There is already some level of interoperability. For example, the above diagram shows co-simulation using Silvaco’s SmartSpice with Invar Electrothermal co-simulation.

The Silvaco press release is here. The Silvaco page on InVar is here.

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Closure: Kilopass v. Sidense

Closure: Kilopass v. Sidense
by Daniel Nenni on 03-19-2015 at 11:00 pm
Categories: IP, Kilopass Technology, Sidense

The long running legal action between the top two NVM IP companies is now finished after close to five years of lawyering. By the way, I write about this stuff in hopes of limiting the future earning power of lawyers that prey on our R&D budgets. This one is significant because Kilopass was not successful in a patent infringement case and now has to pay for the associated legal expenses incurred by Sidense.

Justice is open to everyone in the same way as the Ritz Hotel. ~Judge Sturgess

As I mentioned before, in the U.S., parties in a lawsuit pay for their respective attorney fees which can be staggering. However, U.S. law allows the courts to shift the payment of the winner’s attorney fees to the losing party for “exceptional” reasons. Based on recent legislation “exceptional” now has a much less stringent definition as reflected in recent case law and Kilopass v. Sidense is one of those cases.

You can see the final ruling HERE. This is a must read for any IP company considering patent action against a competitor. The award is for attorneys’ fees in the amount of $5,315,315.01 and other expenses in the amount of $220,630.53. Mediation costs a fraction of that of course but you have to really put your ego in check for that to work. By the way, the court documented the associated legal fees and the hourly expense Sidense paid was between $275-$830 and deemed within reason. So that is what you can expect to pay for fancy San Francisco patent lawyering.

Both Sidense and Kilopass did what I hope is a final press release:

Judge Orders Kilopass to Pay Sidense $ 5.5 Million in Legal Fees and Costs for Baseless Patent Infringement Lawsuit
Ottawa, Canada – (March 16, 2015) – Sidense Corp., a leading developer of nonvolatile memory OTP IP cores, today announced that U.S. District Judge Susan Illston has ordered Kilopass Technology to pay Sidense $5.5 million for its “objectively baseless” patent infringement lawsuit initiated against Sidense in May of 2010. The fee recovery represents attorneys’ fees and associated costs.

Kilopass Focuses on Market and Roadmap Expansion After Sidense Patent Litigation
Kilopass Has Reserved the $5.5M Award, but Moving Beyond to New Business
SAN JOSE, CALIF. –– March 16, 2015 –– Kilopass Technology, Inc., a leading provider of semiconductor logic non-volatile memory (NVM) intellectual property (IP), acknowledges the recent ruling of the U.S. District Court awarding Sidense Corporation $5.5 million for patent litigation legal fees. Kilopass has set aside cash in the full amount of the award.

“We are disappointed in the ruling but, as customers and the market have the substance of the litigation behind them, so do we,” remarked Charlie Cheng, Kilopass’ CEO. “Operationally, we have been busy with 10nm-16nm nodes for OTP roadmap, low-power IoT challenges, and new memory technologies.”

My final thoughts in the form of a cartoon:

Absolutely.

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Full Spectrum Analog FastSPICE Useful for RF Designs on Bulk CMOS

Full Spectrum Analog FastSPICE Useful for RF Designs on Bulk CMOS
by Tom Simon on 03-19-2015 at 1:00 pm
Categories: EDA, Siemens EDA

It has been about a year since the acquisition of Berkeley Design Automation by Mentor Graphics. Berkeley was doing quite well in the somewhat crowded SPICE simulator market. In many respects they broke new ground for high speed and accurate SPICE simulators. Since the acquisition we know that former Berkeley executives are now in significant roles at Mentor. Mike Ellow, former Berkeley Sales VP, is now Senior VP of Mentor’s World Trade Organization; and Ravi Subramanian, former Berkeley CEO, is now Mentor’s General Manager of the Analog Mixed Signal BU.

But more important than how the former Berkeley execs are doing, is how well the products from Berkeley are faring at Mentor.I had the pleasure of reading a white paper from Mentor on their Analog FastSPICE RF suite. The paper is written by two key members of the Berkeley team. David Lee was a co-founder of Berkeley Design Automation, and has a background that spans Bell Northern, Bell Labs and Lucent. The other author is Mick Tegethoff who has worked both in the semi industry and in EDA. He is responsible for marketing in Mentor’s AMSV business unit.

The paper, which can be found here, delves into the challenges faced by high speed analog designers who are increasingly required to work in bulk CMOS and at RF speeds. RF today really no longer implies just radio circuits: SerDes circuits often operate at over 20GHz – well above many RF circuits such as those in the 2.4 or 5 GHz range. The other problem facing analog RF designers is increasing complexity. The circuits have more devices, there are more circuits that must be analyzed concurrently (without making simplifications and approximations), and parasitics play an increasing role in circuit behavior and cannot be ignored.

As high speed analog circuits progress through the design process, their analysis needs progress as well. Estimated parasitics are added followed by device noise analysis and actual parasitics. Finally PVT variation needs to be considered as part of design verification. SPICE simulation is pivotal in each of these steps.

The Mentor white paper points out that Periodic Signal Analysis of near-linear circuits without sharp transitions can be analyzed using Harmonic Balance (HB) techniques. However designers must rely on time domain methods such as Shooting-Newton when the circuits have less linearity or have sharp transitions – which is happening increasingly. Nevertheless, achieving Periodic Steady State (PSS) convergence on the circuits is difficult for many traditional SPICE simulators.

Mentor’s AFS has unique abilities that let it work effectively on non-linear circuits in the frequency domain. First, it uses a Direct Solver, instead of a Krylov based solver for HB. This improves convergence and dramatically improves performance. Secondly, AFS is able to use a full spectrum approach. Instead of limiting the harmonics, it includes noise effects from all the sidebands or harmonics. This graphic from the white paper illustrates how full spectrum simulation in AFS gives better transient results.

There is much more in the white paper. It goes on to talk about Noise Floor improvements in transient sims. Other sections discuss Periodic Device Noise Analysis, Transient Device Noise Analysis, and full parasitic simulation. It closes with more information on circuit characterization, including PVT effects. Lastly it goes over their multi-core parallel operating mode for getting faster results.

Designing at RF frequencies, be it for an optical, RF or a copper medium, is an increasing challenge, especially in bulk CMOS with ever tighter design criteria and specifications. Analog circuit simulation is a mainstay of this process. Mentor appears to have brought on board some key technology as it grows its investment in analog RF design tools and expertise. If you want to read the full white paper, it can be found here.

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SystemC Co-Simulation of NoCs and IP Blocks

SystemC Co-Simulation of NoCs and IP Blocks
by Paul McLellan on 03-19-2015 at 7:00 am
Categories: IP, Sonics

Verification in general suffers from a couple of fundamental problems. Availability of models and performance of different levels of representation.

The first problem, availability of models, is that you would like to start verification as soon as possible but all the representations are not ready early enough. Obviously it is impossible to verify the RTL before writing the RTL, but you may still need to do some simulation of the block to design other parts of the chip.

The second problem, performance, is that it is very difficult to get more than a factor of 10 or 20 out of a representation by discarding detail rather than using a completely different model. You can throw away as much detail as you like in a gate-level representation and you won’t get an RTL simulation. If SPICE simulations ran as fast as emulators then we might not bother with any intermediate representations but obviously they don’t. They can’t even get close to gate-level performance.

As chip design has morphed over the last decade or two from building everything from scratch to integrating IP blocks, the verification problem has got more complex. You would like to verify architectural level performance early in the design cycle. After all, there is little point in going to the effort of assembling the IP blocks if you can tell in advance that the performance will be inadequate.

Another verification challenge is to avoid consuming too much simulation bandwidth on the known-correct parts of the design in order to verify the parts that are still being validated. For example, doing RTL simulation of an entire SoC to validate a single block of RTL is not a good tradeoff of simulation resources.

Many, if not most, advanced SoCs now handle the connectivity of the IP blocks using network-on-chip (NoC) technologies such as those available from Sonics, ARM and others. This means that the IP blocks on the SoC are mostly interconnected through the NoC. One attractive level of simulation is using SystemC. There are actually multiple layers of SystemC although with careful design much of the code can be shared.


Sonics has been creating SystemC IP models since 2005. Initially this was just for performance modeling and functional verification of the NoC itself, but since 2010 they have also provided TLM 2.0 models with OCP/AXI sockets. These models provide their customers with architectural executables for performance/complexity tradeoffs, and also fast models to validate performance on realistic NoC traffic scenarios. This makes it possible to analyze things like bandwidth and latency versus system power, arbitration, buffer sizing and other factors that affect performance, power and area (PPA).

Sonics SystemC models are written to be cycle-accurate. The reason for this is that in a NoC, mico-architectural subtleties (such as missed cycles) can affect performance unduly. While other blocks on an SoC can be modeled approximately, interconnect performance is too central to give up accuracy. The interaction of the NoC with overall system performance is further complicated by features such as clock gating, automatic power-down and wake-up and that have major high-level effects.


Under the hood of Sonics models are equivalence checkers (EC) that ensure that the behavior of the hardware being simulated matches the protocols and catches blocks that “misbehave” and violate some aspect of the protocol (such as sending a message when they should not, or sending a message to an incorrect block). In essence, this compares behavior to the underlying reference model.

Modeling at this level allows co-simulation with models of the IP blocks at different levels, making good use of simulation cycles and allowing investigation to take place at levels from architecture down to RTL verification.


Sonics gave a presentation on co-simulating their NoCs with Cadence’s Incisive at CDNLive earlier this month. The presentations for this year’s conference are not yet on Cadence’s website, but the CDNLive page where they will presumably eventually appear is here.

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TSMC ♥ UMC?

TSMC ♥ UMC?
by Daniel Nenni on 03-18-2015 at 8:00 pm
Categories: Foundries, TSMC

The relationship between TSMC and UMC is one of the more interesting ones in the fabless semiconductor ecosystem in my opinion. Both are headquartered in Hsinchu Taiwan and it is very hard to visit one company without seeing the other as they have facilities right across the street from each other. They also share humble beginnings from inside the same incubator (ITRI) so to me TSMC and UMC are brothers.

Industrial Technology Research Institute is a nonprofit R&D organization (incubator) for applied research and technical services based in Taiwan. ITRI is credited with transforming Taiwan’s labor-centric economy into a technology powerhouse originating more than 260 companies including UMC and TSMC. In fact, UMC spun out of ITRI in 1980 as Taiwan’s premier semiconductor company. TSMC spun out in 1987 as the world’s first pure-play foundry and the rest is as they say history.

Having worked with both UMC and TSMC for much of my career I can tell you that they are two very different companies with unique business models. While TSMC has always been a leading edge company, UMC has perfected the “second source” foundry business model like no other. Chartered Semiconductor tried it and failed, SMIC tried it and is failing, Dongbu, X-Fab, Siltera, the list goes on and on… The jury is still out on GlobalFoundries but with the acquisition of the IBM Semiconductor business they have a legitimate claim to leading edge foundry technology, absolutely.

Unfortunately for UMC the foundry landscape has changed. With the re-entrance of leading edge IDM Foundries (Intel and Samsung) technology requirements are moving at a much faster pace and the Capital Expenditure requirements are well out of UMC’s reach. UMC’s CAPEX for 2015 is less than $2B while TSMC’s 2015 CAPEX is greater than $10B! This CAPEX explosion started at 28nm but with FinFETs (16nm and 10nm) plus new devices coming at 7nm the CAPEX requirements will continue to skyrocket as we desperately try to keep up with Moore’s Law.

What is UMC to do?

If you remember, at 28nm UMC joined the Common Platform Fab Club and licensed the IBM Gate-First implementation. Fortunately UMC changed to the Gate-Last version of 28nm which is used by TSMC and is now reaping the rewards of its continued “T-Like” compatibility. I do not see UMC licensing the Samsung version of 14nm like GF did so what choice do they have but to develop their own T-Like 16nm? With the help of TSMC and UMC shared customers: Qualcomm, Texas Instruments, MediaTek, etc…

The alternative of course is for TSMC to license the FinFET technology to UMC in a similar “copy exact” agreement to what Samsung and GF did. Morris change joked that this made GF Samsung’s “accessory” but as you may have read both Apple and Qualcomm pushed for this agreement so it needs to be taken seriously. There is no way the big fabless companies will be satisfied with just one foundry source moving forward. It is no coincidence that Apple is ping ponging between Samsung and TSMC, right?

So what do you think will happen here? Will TSMC help a brother out?

Also Read: Apple Leaks Chip Sources?

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ARM & Cadence IP Partnership for Faster SoC Design

ARM & Cadence IP Partnership for Faster SoC Design
by Eric Esteve on 03-18-2015 at 9:50 am
Categories: Arm, Cadence, EDA, IP

IP vendors always try to create differentiation, especially when designing protocol based IP. You can differentiate by building the most performing controller but you will probably miss the expectation of these customers who don’t search for performance but just compliance to a specific standard. Or the vendor may want to design features rich controller supporting every possible capability included in the protocol specification but in this case not addressing customer demand for a compact IP optimized for area and power…

What could be the common requirement, for customer designing SoC addressing various market segments like mobile, consumer, networking, storage, automotive and the Internet of Things (IoT)? Time-To-Market (TTM) is the answer! If you are able to provide pre-integrated IP solutions, not only silicon proven but also validated in a design environment similar to this your customer will follow, available on a single development platform, then you will bring TTM advantage through faster integration of the most important IP.

Designing a SoC means using foundation IP (libraries and memory compilers), integrating CPU and probably GPU core(s) and interface IP (USB, PCI Express, DDRn or LPDDRn, etc.). Cadence offers a wide interface IP port-folio, ARM Ltd is the CPU (GPU) IP core leader supplier (and also #1 IP vendor, by the way). If these two companies build an agreement based on pre-integration of their respective IP, running interoperability of these IP and going up to test chip design, such cooperation may really offer TTM advantage to SoC design team. Extracting from the join Press release, this sentence clearly describe the scope of agreement between ARM and Cadence:

“This multiyear agreement provides reciprocal access to relevant IP portfolios from the Cadence[SUP]®[/SUP] IP Group and ARM. Additionally, the agreement grants both companies rights to manufacture test chips containing Cadence IP and ARM IP and to provide development platforms to customers. The ability to test the IP interoperability in silicon is intended to enable Cadence and ARM to optimize performance and interoperability within systems on chip (SoCs) while accelerating time to market for customers in markets such as mobile, consumer, networking, storage, automotive and the Internet of Things (IoT).”

If you evaluate the TTM impact, it’s clear that this engineering time spent in advance by IP vendors to optimize performance and interoperability during the Test Chip integration phase just become a net time benefit for customer SoC design team. This team should shorten the design phase by an equivalent amount of time during SoC integration. Moreover, the agreement allows ARM (resp. Cadence) to design development platforms built around ARM (resp. Cadence) test chip integrating IP from both sources and to deliver this platform to ARM (resp. Cadence)’s customers.

As mentioned by Pete Hutton, executive vice president and president of product groups, ARM: “This agreement expands upon the successful EDA Technology Access and EDA Subscription Agreements ARM signed with Cadence last year to further enable our customers’ designs to reach peak performance and power efficiency.”

And Martin Lund, senior vice president, IP Group at Cadence points the TTM advantage: “This new agreement allows customers of both companies to get to market faster with pre-integrated IP solutions and continue pushing the envelope on low-power and high-performance SoC design.”

If we look back in the 2000’s the IP market has been completely re-engineered for quality: all the providers not able to meet customer demand for high quality IP have disappeared or been acquired. Then at the end of the 2000, the mantra became “Integrated solution” for interface IP and “one-stop-shop” for most of the IP. If one-stop-shop can help saving legal or purchasing resource, the impact on chip integration is weak.

IP vendors understood at the beginning of the 2010’s the need for providing development platforms, virtual prototyping and hardware prototyping systematically. The goal was to improve TTM by improving software development. Chip integration is the heart of SoC development but little has been done since 2000, or at function level (integrated interface IP and PHY and controller IP interoperability), but not at SoC level. This partnership between ARM and Cadence is one step beyond in the race for faster TTM as it helps improving the SoC integration itself, and this agreement is the first of this kind…

By Eric Esteve from IPNEST

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SEMI: All This and Breakfast Too

SEMI: All This and Breakfast Too
by Paul McLellan on 03-18-2015 at 7:00 am
Categories: ESD Alliance, Semiconductor Services

Are you interested in any of these?

  • Internet of Things
  • Trends and Forecast for Fabs
  • Inflections Points
  • Semiconductor CAPEX
  • Cost Effective Scaling
  • Prospects for 450mm
  • Future of EUV
  • Mobile Machine Learning
  • Robotics/Drones
  • Cybersecurity
  • Used Equipment Markets
  • World Fab Databases
  • Free breakfast

No? Then I think you got the wrong website to be visiting. This Friday 20th March at 7.30am (yes, but there will be coffee to wake you up) is the SEMI Silicon Valley Breakfast Forum. This time it is subtitled Wafers to Wall Street, a Semiconductor Outlook. The meeting will take place at SEMI’s headquarters at 3081 Zanker Road (map). Registration and breakfast from 7:30am and the meeting proper starts at 8am.


The presentations are:

  • Dean Freeman of Gartner on The Impact of IoT on Semiconductors
  • Christian Dieseldorff of SEMI on SEMI’s World Fab Forecast, Trends and forecast for spending, capacity and more
  • Patrick Martin of Applied Materials on The Role of Materials in Scaled Architecture
  • John Pitzer of Credit-Suisse on The Semiconductor Outlook: Bigfoot, UFOs, Sustained Upturns
  • Samir Kumar of Qualcomm on How today’s processors will power other devices beyond phones

Each presentation is 20 minutes. The meeting will wrap up by 10.30am.

More details including a link for registration are here.

About SEMI
SEMI is the global industry association serving the nano- and microelectronic manufacturing supply chains. Our 1,900 member companies are the engine of the future, enabling smarter, faster and more economical products that improve our lives. Since 1970, SEMI has been committed to helping members grow more profitably, create new markets and meet common industry challenges. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information on SEMI, visit www.semi.org.

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Webinar: Choosing IP for your next IoT Design

Webinar: Choosing IP for your next IoT Design
by Daniel Payne on 03-17-2015 at 8:00 pm
Categories: eSilicon, IoT, Semiconductor Services

My favorite IoT device is a cycle-computer from CatEyeand it has GPS for tracking my bike routes, and an LCD display that shows me speed, cadence, heart rate and time. After each ride I connect my CatEye device to a USB connector, upload my data to Strava.com, and then see how I’m doing versus other cyclists and my own personal records. This computer holds a charge of some 12 hours, doesn’t require any phone to operate, and is wireless, so you don’t see any wires stringing around my bike frame. Even the heart sensor is wireless, thanks to bluetooth.

I can only imagine the kind of IP that CatEye and other companies must choose to get their products to market quickly and capture the loyalty of consumers looking to get and stay healthy. The folks at eSiliconinvited me to a webinar last week on the topic of IP and IoT designs, and I learned quite a bit. Analysts estimate that the IoT market could create $300B to $19T in revenue with 25B to 100B devices by 2020. Segments for IoT devices and services include opportunities for many semiconductor products in diverse markets:

  • Connected Vehicles
  • Healthcare
  • Smart Homes
  • Wearable
  • Computing
  • Industrial Internet
  • Communications
  • Smart Cities

Depending on the IoT application you could use a range of process technologies from 180 nm all the way down to 14/16 nm, it all depends on the power, performance and area required.

Related – IP for IoT: Thanks for the Memory

Microcontrollers are often used in IoT devices and you can select the best MCU by choosing from 8 to 64 bits, clock speed, embedded FLASH, OS, radios, and process nodes.

What eSilicon has to offer your IoT team are ASIC design services along with IP. They have online tools for multi-project wafers, IP libraries, and tracking of manufacturing. They use their own IP for client designs that require ultra low voltage (ULV) and ultra low power (ULP). IP blocks for IoT devices include:

  • ULP/ULF SRAM & ROM
  • Pseudo DP SRAM
  • Low leakage SRAM
  • 65 nm, 55 nm, 40 nm, 28 nm
  • Planar CMOS and FDSOI technologies

Related – eSilicon Just Taped-out a SonicsGN-based SoC. And it’s not a Secret

For high-performance networking, communications and networking devices their IP blocks are:

  • TCAM
  • Multi-port & Asynchronous Register Files
  • SRAM, ROM
  • Memory PHYs and interposer design
  • 28 nm, 16 nm, 14 nm, 10 nm
  • Planar CMOS and FDSOI technologies

Requirements for IP that are both ULV and ULP are not met with the standard IP offered by most vendors and foundries at the 28 nm node, so eSilicon has IP and the ability to customize the IP to meet the needs. One client chip that eSilicon designed was in 28 nm technology, had 16.84 million gates and used about 42 Mb of memory. They were able to analyze and optimize the IP to show an 8X reduction in standby power and 20X improvement in idle power by using customized IP.

For a Medical IoT application eSilicon was able to provide a 40 nm Single Port SRAM that was not available anywhere else:

Another specialty SRAM instance was for a 1K x 24 size operating at just 720 mV and 36 MHz, using 55/65 nm technology.

Related – IP Market at your Desk!

Ternary CAMs are used in high-performance networking applications in the Cloud, and eSilicon has created a family of CAM compilers to work with multiple technologies.

Summary
For IoT designs you can get to market more quickly by re-using specialized IP or even consider using ASIC design services from a company like eSilicon. View the entire 35 minute webinar online for more details.

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Exploring IP You Didn’t Design Yourself

Exploring IP You Didn’t Design Yourself
by Paul McLellan on 03-17-2015 at 7:00 am
Categories: Concept Engineering, EDA

Starvision Pro from Concept Engineering is a bit like one of those Leatherman multi-tools, it has a huge number of different functions, some of them fairly specialized but nonetheless incredibly useful. Many of these functions are unique to Starvision Pro, with nothing else like it on the market. Some new videos, produced by EDA Direct, who are Concept Engineering’s US distributor, show some of these applications.

Designing an SoC these days is mostly about IP assembly. This means that design teams acquire IP blocks which they did not design themselves and so are not familiar with. Working on these blocks, to customize them or even just understand them, requires the capability to manipulate them in various ways quickly and efficiently.

The first video is taking in a large complex netlist and pruning it down to something more manageable for detailed analysis. Large netlists create confusion and are simply less productive when all you want to do is find a single trace, a single critical path or a small sub-chunk of a module. Starvision Pro has an incremental design navigation feature called cone-extraction which allows you to focus on the part of the netlist in which you are interested while hiding the rest of the netlist that is not of immediate interest. In a special cone-window you can explore the connectivity up and down the hierarchy or, with a flat netlist, nagivating through the sea (ocean) of logic gates. The chunk/fragment/partition/pruned netlist can also be saved as a Verilog or SPICE netlist for further simulation.

Click on the picture below for the video (9 minutes)

Next up, how to take a flat netlist and add hierarchy. Why might you want to do that? If you have received 3rd party IP then it might not have enough hierarchy to make the design easy to understand or manipulate. Never fear, Starvison Pro can make it easy to turn flat into hierarchical quickly.

Click on the picture below for the video (8 minutes)

Finally, processing post-layout parasitic files like DSPF/SPEF. You often find yourself trying to read lines of text and figure out the connectivity between different nets with lots of parasitics. Starvision Pro lets you read the file and
view the entire connectivity of the parasitic network in the form of a schematic. YOu can not only examine the schematic but the tool helps you debug the RC network net by net.

Click on the picture below for the video (6 minutes)

The video gallery, containing all these videos and more, is here.

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Mapping Focus and Dose onto BEOL Fabrication Effects

Mapping Focus and Dose onto BEOL Fabrication Effects
by Tom Simon on 03-16-2015 at 7:00 pm
Categories: Coventor, EDA, Events

With today’s ArF based lithography using 193nm wavelength light, we are hard up against the limitations imposed by the Raleigh equation. Numerous clever things have been devised to maximize yield and reduce feature size. These include 2 beam lithography, multiple patterning, immersion litho processes to improve NA, thinner resists, etc. While we wait for EUV to become feasible, those responsible for manufacturing current production chips work with tuning the dozens of aspects in the existing lithography and fabrication process.

We have talked before about the utility of modeling what happens during the IC fabrication process. The ability to simulate the outcomes of fabrication steps is enormously valuable. Coventor’s Semulator3D is a proven tool for performing these simulations. They have a number of white papers on their website that go through the process step by step. The BEOL paper that they feature on this page highlights a tri-layer mask process that uses a thin photo-resist to improve transfer of the aerial image. The latent image is also improved by the middle anti-reflective layer which avoids reflected interference patterns in the resist. These can notably affect edge definition and can undercut the resist at the bottom.

The Coventor Semulator3D shows exactly what happens during processing. This is invaluable in determining the reliability and electrical properties of the resulting wafer. However the developed resist image depends on a myriad of factors. So before we can look at the effects of wafer processing, we need to have a good starting point with physically accurate resist geometry. Focus and dose both have profound effect on the resist sensitization. This is often visualized with a Bossung curve such as that show here from Chris Mack’s excellent lithography lecture series.

Let’s say we wanted to model the whole process from litho to fabrication. This is exactly what Coventor, Panoramic Technology and ASMLdid in material they showed at SPIEa few weeks ago. They used HyperLith from Panoramic Technology to predict the resist contours at a variety of doses and defocus values (0 to +/-50nm). We can see the wide variation in resist quality. Then they took this output and ran it through Coventor’s Semulator3D to see what the resultant wafers would look like.

Coventor can run simulations using their SWA (side wall angle) Variation and look at results with a range of side wall angles. The tradeoff here is line width versus line spacing. If the line widths are too small you have opens in the interconnect and high resistance that can affect circuit operation. If the line to line spacing becomes too small it’s possible to get shorts or proximity failures.

The flow that was used in their SPIE material shows a matrix of dose and defocus values that is then run through Semulator3D with SWA variation. This provides a comprehensive set of data to help understand yield effects. I was lucky to speak with Bill Clark who works in Semiconductor Process and Integration Engineering at Coventor after the SPIE conference. He explained in more detail how this data was prepared. The resist masks came over from Panoramic’s Hyperlith as STL files. Then in Semulator3D they used the Expiditer option to perform batch runs on the dose and focus values with SWA Variation. The output is available in CSV for further processing as needed. Or as you can see the results are available to examine visually.

According to Bill, this demonstration shows a unique approach to better analyzing effects that occur during lithography and fabrication. Hopefully using analytical software in this fashion will help improve visibility into the manufacturing process with the goal of improving yield.