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I Don’t Know Much About Aart…

I Don’t Know Much About Aart…
by Paul McLellan on 06-15-2015 at 7:00 am

Actually, like anyone who has been in EDA for more than a decade or two (or three) I know quite a bit about Aart. But I still learned quite a bit about his views at the Fireside Chat at DAC where Ed Sperling talked to Aart for three-quarters of an hour.

Aart has a great talent at taking various small trends in the industry and aggregating them up to a significant trend. Or looking at some aspect of the industry and generalizing it in an interesting way. I won’t try and cover everything (it took Aart 45 minutes to say it and it would take you 45 minutes to read it…not to mention my note-taking skills are not that good.)

One area where Synopsys is different from the other big 3 EDA companies is its recent (starting last year) foray into the software quality and security space with its acquisition of Coverity and a couple of other smaller companies or parts of companies. One of the things that Aart has learned, he said, was never to say something is secure. It is no more plausible than saying that Design Compiler is bug-free. Hopefully things are more secure than they were yesterday, just as hopefully Design Compiler has fewer bugs today. But security is just one angle in the software space, since it is not possible to have secure software if it is poor quality. There is no silver bullet in software quality but many things are pretty easy to check for so it is stupid not to do them.

In the automotive keynote on Tuesday Jeffrey Owens of Delphi pointed out that a car has 100M lines of code, more than Android and Facebook and…well, Aart saw Jeffrey’s 100M and raised him to 400M. Synopsys has 400M lines of code in its portfolio. It invests 31-34% of revenue in R&D. Plus they have done 17 or 18 acquisitions over the years to add additional capability over and above what they invest directly.

Ed asked Aart if internal development was cheaper than acquisition. Aart agreed that it was but the timing is not always right. If a company develops a technology and makes it a commercial success, it may be too late to start an internal project to copy it. This is classic innovator’s dilemma stuff, by the time the future is obvious it is too late. Aart said that VCs are always complaining about bubbles in valuations, but what they really mean is that they want to be inside one. “Lord let there be one more bubble” was a bumper sticker he had seen on Sand Hill Road. But for sure, right now, internet software companies are valued more highly than EDA companies.

Ed asked Aart about Moore’s Law and Dennard’s Law (the one about scaling transistors). Does everything go more slowly? Are there too few companies at the sharpest end of the arrow? I think Aart actually ducked the question by saying that exponential ambition is alive and well in hardware and software and developments in hardware and software will continue for another 30 years or more. For a couple of years Aart has had a keynote built around what he calls Technomics, the combination of economics and technology.


He admits that there are economic challenges and the way that profits in the value chain may need to move. We see some of that already in the big investments that semiconductor companies need to make in equipment companies, especially for EUV, since there is not enough profit in simply selling equipment in the normal way. Similarly foundries have huge capex budgets, $10B for a new fab plus $3B for a new process to put in it. One solution that we have been living through is siloing everything aka disaggregation of the supply chain: materials companies, equipment companies, foundries, fabless design companies, EDA, embedded software and so on. That works for efficiency but often it is breaks down such as now where we are moving from Moore’s law (scale complexity) to systemic complexity. Coooperation is one way to break down silos, but not always that good. Mergers and acquisitions is more forceful.

IoT will change the equation since it is going to use older nodes. But there may not be enough older node capacity. But Aart says that might be a good thing. The memory companies (especially DRAM) have be come much more disciplined about overinvestment. In fact most of the recent growth in semiconductor is entirely due to prices firming in memories. With the big 3 EDA companies going in slightly different directions there is some of that too. “A certain amount of not beating each other into the ground is good.”

Management of all this is a big change since companies are change averse. Change can be driven by stress (no alternative) or courage. Stress is the easy way, but great companies have courage. They are not always successful but courage and perseverance are very valuable. The smoke has not cleared yet but for sure the age of IoT (smart everything) is a massive wave that will impact mankind.

Manufacture + design + EDA has moved the world already and it will continue to do so. But exponential ambition only gets paid for linearly, which is one of the challenges of being courageous.


Eyes Meet Innovations at DAC

Eyes Meet Innovations at DAC
by Pawan Fangaria on 06-14-2015 at 7:00 am

It gives me a very nice, somewhat nostalgic, feeling after attending the 52[SUP]nd[/SUP] DAC. There was a period during my final academic year in 1990 and my first job when I used to search through good technical papers in DAC proceedings and try implementing those concepts in my project work. In general, representation from ‘R&D teams’ is less in DAC, unless an engineer has a paper to present. So, I didn’t have many opportunities to attend DAC in the past. Now that I am in consultancy and marketing role, when I attended DAC, I felt it to be overwhelming in terms of dissemination of technological information. I found DAC to be one of the best forums for learning about most of the new innovations in the semiconductor space. We get an opportunity to see the new innovations working through live demos at DAC year after year.

I must confess that I could not see all of it in DAC 2015; missed a few booths even though I had planned to visit them. The environment was so vibrant from the first day that it was difficult to manage time between various presentations, talks, demos, keynotes, invited talks, panel discussions, and so on to attend one after another. The most interesting part I found about the DAC is that it has many facets of opportunities for everyone to avail of what they desire and strive for. One of my agendas in DAC has been to find out the top innovations of the year. This year also, fortunately being physically present at DAC, I found some of the compelling technologies which are going to add great value in the semiconductor ecosystem. This may not be the whole list of top innovations, but here are the ones I could observe myself.

ARM IP Tooling Suite: The ARMIP Tooling Suite provides a very innovative and relevant capability for SoC integration in today’s design environment. The Socrates DE provides a design environment where multiple IPs including third party IPs can be configured and assembled together to optimize your BOM for the SoC. There are CoreSight and CoreLink Creators that help in micro-architecture creation and further improvement in configuration efficiency. The whole estimation and creation can be done in a matter of minutes or hours. This solves one of the key issues in the semiconductor design industry where SoCs have to be targeted according to the market segment and integration of right IPs has to be pre-determined for the success of the SoC. This is a key innovation in today’s context; I will be writing more specifics about this separately, stay tuned.

Veloce + PowerArtist: This is a great example of competitors complimenting their tools for larger benefit of the semiconductor ecosystem. Interestingly this is integration between two competitor tools. Mentor’sVeloce emulator generates real-time dynamic power data for the SoC, and that is read directly by ANSYS’ API for dynamic power analysis in PowerArtist. This approach provides accurate power analysis in order of magnitude lesser time.

JasperGold Formal Verification Platform: Formal and assertion-based verification technologies are gaining ground in SoC verification space. Designers are not able to use them in the main stream verification, primarily due to lack of ease-of-use. JasperGold platform solves the ease-of-use problem by offering automated ‘Verification Apps’ and seamlessly integrating them with the Incisive Verification Platform and Cadence System Development Suite where coverage driven verification methodology takes place and verification gets further complemented by simulation, emulation and debugging environment.

Cloud Cube: The Cloud Cube 32 is an innovative solution from S2C that enables FPGA-based prototyping of large SoCs of sizes up to 1.4 billion gates. It provides a complete prototyping platform that lets designers start the design at any stage, from anywhere in the world and the design size can grow up to any extent with this scalable architecture.

GENUS: A new generation RTL compiler from Cadence that has a massively parallel architecture providing order of magnitude faster synthesis and significant improvement in PPA over previous solution.

IC Compiler II: A major improvement in Synopsys’ IC Compiler for order of magnitude higher throughput and better QoR of placement and routing.

Spice Simulation and DFY tools in the cloud: This is a novel idea from ProPlusDesign Solutions, RuntimeDesign Automation and ZenteraSystems where NanoSpice and NanoYield are managed by NetworkComputer workload manager from Runtime DA and run on a public cloud managed and secured by Zentera’s Hybrid Cloud Solution over virtual network.

These are some of the new innovations of this year. Also, there are good innovative products from previous years which are proving to be valuable by now. We are seeing good new acquisitions as well that are expected to drive more innovations in future. Some of the innovations from past acquisitions (e.g. Jasper acquisition by Cadence) are already visible today. I also learnt about other innovations from past acquisition that are in work and expected to come out soon; will write more about those later.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com


Design Data Management: An Analog IP Porting Case Study

Design Data Management: An Analog IP Porting Case Study
by Majeed Ahmad on 06-13-2015 at 9:00 am

IQ-Analog Corp. offers “off-the-shelf” data converter intellectual property (IP) for multiple foundries. The San Diego, California–based semiconductor design firm also provides analog front-end (AFE) technology that it tailors according to customer needs. And that’s where the dilemma begins.

IQ-Analog’s customers have different requirements, and they use different foundries and manufacturing processes. For a start, the IP products that IQ-Analog delivers requires customization for a new fab and technology node. They also require back end of line (BEOL) metal stack variations. Furthermore, IQ-Analog has to customize IPs in a tight delivery schedule while leveraging the existing designs.

Then, there are analog IP porting challenges regarding the availability of similar active and passive components. And different BEOLs and DRC rules lead to manual physical layout modifications. Inevitably, these design updates and verification iterative cycle result in project delays.


Data management tools allow to pick a coherent set of changes

According to Dan Woodard, Director of Operations at IQ-Analog, IC design changes happen on multiple axes, and we need to pick these changes from multiple lines of development. “These changes are dynamic with a number IC designers operating on the same data, so we need to reliably select a coherent set of changes.”

Analog IP Porting: The Solution

Woodard took the floor at the 52nd Design Automation Conference (DAC) and shared the details of the solution that has worked well for his company. He told the DAC audience that IQ-Analog couples EDA tools to data management tools to keep track of various versions of IP content, including schematics, layout, simulation setups, technology kits, etc.

That helps the design firm leverage the use of an organized library with numerous tags and branches and assemble the targeted IP core. The combo of EDA and data management tools specifically helps IQ-Analog address customer requirements as the company can clearly establish the project configuration to efficiently leverage its ever-growing library of IP content without redundancies.


Dan Woodard speaking at DAC’s IP Track

IQ-Analog, which uses ClioSoft’s SOS data management platform, follows a strict rule-based system using tags and branches. Tags are employed to mark meaningful development milestones while branches are used to represent alternative development paths. The tagging feature in SOS allows labeling a revision with a meaningful name so that a revision of a file can have multiple tags and a tag on a file can be moved to a different revision.

Next up, the branching feature provides the ability to create an alternative path of development. Sub-branches can be created off branches. Moreover, all branches of development are visible to all design project team members, allowing changes on multiple branches to be selected.

ClioSoft’s SOS data management platform also provides revision search order (RSO) feature, a priority ordered list of tag and branch names, which serves as a rule to pick revisions to create a workspace. Here, revision with the first matching tag or branch name is selected.

ADC Case Study

IQ-Analog’s Woodard presented analog-to-digital converter (ADC) as an example of how analog IP is ported to a chip design. An ADC cell has a poly resistor component for which initial implementation is carried out by creating libraries for all anticipated fabs. These libraries are segregated by branches and tags.


ADC sub-component example

“If we want to move to a new fab, we simply update the RSO with the new reference libraries,” Woodard said. “The updated resistor now references the proper cell for the new fab.” He further explained how an IP product containing resistors, capacitors and related analog components is migrated from TSMC 40nm process to GlobalFoundries 40nm process in just two weeks.

The library has a built-in capability of rapid transition and can move from one foundry technology to another without carrying out the layout work twice. Woodard also showed how retargeting from TSMC’s 40nm BEOL of 5x2x to 6x2z takes just two days. “IQ-Analog was able to maintain TSMC branch and only branched further the layout views in which the metal transitioned above the thin metals.”

The Net effect

IQ-Analog’s Woodard told the DAC crowd that a design data management tool like ClioSoft’s SOS allows IC designers to augment only a few items to implement a fix rather than traversing all implementations to incorporate fixes and corrects. “Changing the underlying reference and then re-running verification may be all that is needed for delivery.”


Analog IP migration from one fab to another

He also acknowledged the value of using data management tools that comes with the automation of the process; it allows IQ-Analog to reduce the time required to map an analog IP from one foundry node to another.

The upfront work of creating the content in a given node facilitates an IC designer to implement fixes in all the nodes instantly, saving the time it would take to implement the changes uniquely in each project. “The automation enabled by tools like SOS design data management platform avoids clerical errors that can be manually introduced in mapping from one node to another,” Woodard concluded.

Also read:

Why Design Data Management: A View from CERN

The Secret Sauce for Successful Mixed-signal SoC Tapeouts

Managing Design Flows in RF Modules


Extending EUV Lithography

Extending EUV Lithography
by Scotten Jones on 06-12-2015 at 1:00 pm

I have previously written about SPIE day 1 and 2 so I want to wrap up my coverage with some impressions from days 3 and 4. My single biggest take away from the conference is that EUV has made tremendous progress in the last 12 months. Last year the mood of the conference was in my opinion pessimistic with respect to EUV, this year the mood appeared to me to be much more optimistic.
Continue reading “Extending EUV Lithography”


eSilicon@Samsung: ASIC Design, IP Enablement, and Cloud Platform

eSilicon@Samsung: ASIC Design, IP Enablement, and Cloud Platform
by Paul McLellan on 06-12-2015 at 7:00 am

Earlier this week at DAC, Javier DeLaCruz of eSilicon presented at the Samsung booth. They presented an introduction to what eSilicon does. However, since what they do has changed over the years it is useful to recap. If you know about eSilicon then you probably think of them as a fabless ASIC company. The old ASIC model back in the 1980s and 1990s was that the system house would do design to netlist and then pass that to the ASIC company who would do physical design, manufacture the design and deliver packaged parts.

Designs are much more complex these days. eSilicon typically will partner with the customer from the very beginning of the design. So eSilicon either does or helps the customer do:

  • technology selection
  • IP selection
  • design
  • assembly and test development
  • manufacture


The area where there is the most variation is doing the design itself. If the customer has a lot of design expertise in-house they may basically do the entire design and deliver mask data to eSilicon. If they have none they may deliver some higher level specification of the design and have eSilicon do the design for them.

Some companies just get eSilicon to do manufacturing. Since eSilicon doesn’t actually have fabs of its own, this seems self-contradictory, but in fact a lot of running a design in production is management and tracking of the design through the manufacturing process. In high volume, a design might be millions of parts per month for many months, so it is not a one-shot deal. eSilicon calls this SMS (for Silicon Manufacturing Services).

Another area where eSilicon has a lot of expertise is IP selection, especially in memories. They have their own memory IP development groups (mostly in Vietnam). These groups can provide standard IP but they can also customize IP for specific designs. For example, in the chip below, which is a broadband processor for the handheld market, the memory was 50% of the die area but by doing a customized memory solution they saved 20% of the memory area, or 10% of the complete die area.

eSilicon have also been a pioneer in HBM (high bandwidth memory), starting with HBM1 in 2013 and with HBM2 IP development underway. HBM is thru-silicon-via (TSV) memory stacked on top of the logic die. To be useful, just as with standard DRAM, there needs to be a standard interface (where the TSVs are, what the signals are and so on) and indeed JEDEC produced a standard JESD235. By definition, HBM is not just a design issue, it is a packaging and manufacturing issue too since these are true 3D chips. See the picture to the right.

Another area where eSilicon has been a pioneer is in bringing more and more of the customer interface online so that it can be accessed by users directly without requiring human involvement. So just as an ATM makes getting money easier and more convenient, so customers can help themselves to:

  • IP selection
  • MPW shuttle quotes
  • Production quotes
  • Design optimization quoting (this one is not untouched by human hand but the early acceptability analysis is)

These all go out under the new STAR banner (standing for self-service, transparent, accurate, real-time) which I wrote about in detail last week.

See eSilicon Lyfts Its Game

Samsung Foundries’ website is here. eSilicon’s website is here.


ARM and frog Team up with UNICEF to Foster Creation of Wearables for the Developing World

ARM and frog Team up with UNICEF to Foster Creation of Wearables for the Developing World
by Tom Simon on 06-11-2015 at 5:00 pm

When the term wearables is mentioned most people’s first thoughts go to devices like the Apple Watch, Fitbit Flex, or Nike Fuel Band. Wearables such as these solve first-world problems like how much exercise am I getting, or what is my heart rate. The developed world drives the development of new technology in most cases, and wearables are no exception. Nevertheless we see many instances where our toys and gadgets become important problem solvers for developing countries.

There are many examples of the application of high tech devices to solve developing world problems. Cell phones have brought communication to remote and hard to ‘wire’ locations. LED’s, lithium batteries and solar panels have brought light to places that had to rely on flame based light sources previously. Incidentally my son, Kevin Simon, is working at MIT on developing highly efficient water pumps for the farmers of developing nations that are optimized for solar and small scale power sources.

Many of us are familiar with UNICEF. It is the wing of the United Nations that is solely focused on improving the welfare of children in the developing world. UNICEF has 7 pillars that they relentlessly focus on: Health, Education, HIV/AIDS, Water, Sanitation/Hygiene, Child Protection, and Social Inclusion. UNICEF is partnering with ARM and the design firm frog to explore how wearables can effect dramatic change for the children in the developing world. This initiative is called Wearables for Good. They have set up a web site and have published collateral material.

At the heart of this effort is achallenge open to anyone who has an idea or wants to build something to use wearable and sensor technology that serves people in resource constrained environments. From now until August 4[SUP]th[/SUP] anyone is welcome to apply to participate. The combined resources of UNICEF, ARM and frog will be available to coach and advise applicants. After a project refinement phase, final judging will take place from October 2[SUP]nd[/SUP] to Novemer 2[SUP]nd[/SUP], when the winners will be announced. There is an excellent handbook for applicants to learn about considerations and guidelines that is available on their website.

The handbook talks in more detail about what is meant by wearable technology. Despite our preconceptions, they have expanded the idea to include mobile technology that is not only on a wrist or ankle. Wearables can be devices that are close at hand, worn, or even ingested. They need to do one or more of four things: Alert/Respond, Diagnose/ Treat/Refer, Change Behavior, and/or Collect/Analyze Data. At the same time these wearables must live within a design approach that includes these characteristics: Cost effective, low power, rugged & durable, and scalable.

Designing things for the developing world is tricky. They have to work in an environment that must be fully understood. There are cultural issues, infrastructure limitations, and all sorts of pitfalls, such as limited resources for repair and deployment. Users may not have skills that we take for granted. There are even political barriers, such as privacy concerns. The handbook has a list of use cases that are suggested as possible areas of focus. One of them suggests helping alert people in dense slums when there is a fire. Another is looking for a way to modify people’s behavior so they wash their hands more frequently, thus reducing disease. One of the most compelling was helping to document births so people have official ‘identities.’ Without birth records, it is impossible for individuals to get aid, education and even own property. They suggest that a portable/wearable device that could be used in remote villages to record birth records and convey them to official agencies to alleviate this problem.

ARM is offering its development tools and mentoring from their wearable tech experts to help bring projects to fruition. The design firm frog is making available its design and product strategy expertise to the winners. frog is the renowned company that had a hand in the distinctive design of many of Apple’s products. Finally UNICEF has a network of innovation labs and many partners that can provide valuable insight into the real world needs to the ultimate users.

Probably the best ideas will not come from someone in who grew up in Palo Alto or New York City, but rather someone who has encountered the environments where the final projects are destined to operate. The invitation to the challenge is casting a big net and there will be entries from all over the world. It’s exciting to see opportunities for applying technology to address pressing problems around the world. The value here will be a lot more than a higher stock price or better revenues – people’s lives will be improved in significant ways. When you read about the preventable infant mortality rate or the numbers of preventable infections in developing nations, it is clear that this could be a truly meaningful effort.


Application Specific Integrated Comedy

Application Specific Integrated Comedy
by Paul McLellan on 06-11-2015 at 7:00 am

Tuesday night I got to meet an old colleague. OK, this is DAC, that is hardly a story. I was at the Synopsys media dinner and John Koeter handed out free wristbands to the Stars of IP party taking place later that evening. Remember, Synopsys is #3 in IP overall and #1 in interface IP. Talking of which, earlier in the day I was at the Synopsys custom IC lunch which I will cover later which had an especially interesting presentation from the Synopsys IP group who, not surprisingly, are big users of the custom IC product line.

The party was the 3rd Stars of IP party organized by IPextreme (although now most of the IP companies participate too). I had lunch with Warren Savage a few years ago and he told me the genesis of what became IPextreme. At the time he was at Synopsys. Also at the time, ARM supplied their microprocessor as hard IP, a physical process-dependent layout. Actually there was really only one core back then, the ARM7TDMI which became the standard in mobile phones and set ARM on the course to where it is today. As an experiment Warren and his team did a synthesizable version of the ARM7TDMI, after all they were at Synopsys. ARM were skeptical it could be done. What nobody, even Warren, really expected was that the synthesizable core would turn out to be smaller than the hard core. It wasn’t an overnight change but it completely altered how cores would be delivered. Except for a parts of the PHYs for interfaces, and some other analog areas, everything would be synthesizable, which is where we are today.

Performing at the Stars of IP party was Don McMillan. I first met Don when we were both at VLSI Technology where he was an IC designer. Last night I talked to Don about his early days in stand-up and he told me he was at a comedy club on open-mike night. “You mean I can just go up there and perform?” So he tried it. As he says, there is probably no business where you get quite such instant feedback. In 1991 he won the 16th San Francisco stand-up competition and then was the overall winner on Star Search the following year. By then he’d given up being a chip designer and was doing stand-up full time. Although he has performed on the tonight show and done commercials for Budweiser and all sorts of other things, a lot of his bread-and-butter comes from being able to do comedy in technical environments where he actually is as much of a geek as his audience. Engineer jokes are just a lot funnier coming from an engineer.

Another person working the same idea is Scott Meltzer who I hired for his first time at DAC when I was at VaST and for many years has been seen on the Apache booth doing a strait-jacket escape on a unicycle and other things. He has a degree in computer science from Berkeley. At VaST he ran the demos himself since he already knew Linux.

When I was at Compass we would hire Don to be our presenter on the booth, although the most interesting performances were always the last couple on the last day when we told him we couldn’t face hearing his routine about our products one more time and we just unleashed him to do whatever he wanted. It was always the biggest crowd of the entire show.

His first time working our booth we had a big deep-submicron (DSM) theme going so he came up with the first deep-submicron joke. And I still remember it:”A neutron walks into a bar and says how much for a beer?”
“For you, no charge.”

OK, I’ll stick to blogging. Don’t forget to tip your server.

Don’s website TechnicallyFunny is here.


Why silicon photonics and 2.5D design go together

Why silicon photonics and 2.5D design go together
by Beth Martin on 06-10-2015 at 4:30 pm

Silicon photonics is one of the upstart “More than Moore” technologies designed to enable the next generation of high-performance devices. Photonic design is the art of moving and transforming signals in the form of photons, allowing the message to literally travel at the speed of light, and bringing the promise of significant performance gains. I’m starting to see evidence that silicon photonics is moving from the research phase into development. The adoption of silicon photonics will be driven by the demands of data center and high-performance computing.

Another “More than Moore” technology is 3D IC design, in which a design is partitioned into smaller pieces that can be stacked, resulting in smaller form factors and thus allowing more functionality to be packed into tablets and other hand-held devices. Aside from some novel design concepts (such as the memory cube), you will not typically see a performance advantage with 3D designs. In fact, it may degrade performance by introducing longer paths between devices on separate dies.

“As luck would have it,” says John Ferguson, a product marking manager in the Calibre group at Mentor, “silicon surrounded by silicon-oxide makes an almost ideal waveguide material, meaning the optical signals can traverse with very little degradation.” This means that photonics can be designed and manufactured using the same fabs already in place for traditional IC design. Indeed, Intel has already demonstrated this last year when they introduced a 100 Gigabit silicon photonic product (prematurely, it turns out.)

But, of course, there is always a catch. Photonics design is purely passive. If you want to change an optical signal, you must induce that change using either heat or a magnetic field (or both) in the vicinity of the waveguide carrying the signal, says Ferguson. So, just create a design with some photonics components and some electronics components, pass timing-critical data as optical photons and use tried and tested electronics elsewhere, right? Well, maybe not, said Ferguson. If the electrical components are complex, you may need to target those expensive CMOS processes again. Unlike the CMOS transistor, however, there is little benefit in porting a silicon photonic waveguide to an advanced node. That is because the optical behavior for such components is set by the total length and width of the wave guide, along with some other concerns, like bend structures or how close it is to other components. The widths for waveguides in silicon are very large (100-200 nm) compared to today’s CMOS devices. So, even if you go to a new process node, the photonics section stays the same size. Also, Ferguson says, putting photonics on the same die as electronics uses up a lot of expensive silicon real estate for the relatively large photonics structures.

But, you could combine silicon photonic processing with 2.5D processing–partition the optical components to a less expensive process, such as those typically targeted for interposer use (like, say 65nm or 90nm), while targeting those more critical electrical components to a die on a more advanced process node, maybe 28nm. This is where a lot of photonics research is currently targeted. Almost all silicon photonics designers are putting photonics into the interposer itself, which is usually at a more matrure process node like 65nm or 90nm, and then connecting to the electronics as a die on top. In fact, Cisco showed a silicon photonics/2.5D prototype at a 2013 DesignCon keynote. That technology came from Cisco’s 2012 acquisition of optical interconnect company Lightwire.

There are lots of questions to be answered regarding silicon photonics and 2.5 and 3D design. For example, in some designs, like the memory cube, you can actually gain performance by connecting through a TSV, but it requires careful die to die placement such that the critical devices on either side are close to the TSV, says Ferguson. In such a case, you can have an electrically closer signal. Usually this means stacking directly on top of the signals in question. Unfortunately, outside of the memory world, so far this approach typically fails due to thermal impact. An active die with lots of switching can produce a lot of heat. Setting it on top of another active die can cause problems for the neighboring die devices. This problem is even more concerning to the photonics design because heat will change the behavior of the optical signals through the wave guide Fortunately, we’ve already learned to stack them like a stair case, Ferguson says, where the interposer juts out from the die and in the extruding area the photonics are inserted. Doing this in the less expensive interposer is far less costly than folding it all into the same expensive advanced-node die.

What impact will this have on the photonics components? The photonics will require a laser source, but because we’ve yet to produce a usable silicon laser in standard CMOS process, it will need to sit off-die. What impact will this have on the form-factor? What impact will the heat generated by the laser have on the near-by electronic components?

Is there was a way around the limitations imposed by TSVs? Oh, say, with photonics? Because light signals can pass through each other essentially unimpeded, this also brings the theoretical ability to eliminate the need for vias, dramatically reducing the power required to pass said signal. There is some high-level research in this area, but nothing practical yet.

There is a lot of work to do, and silicon photonics is a dynamic industry. A major hint that this is big-time interesting is that the government set up a National Photonics Initiative in 2013 and seeded it with $200 million. In the private sector, start-up Luxtera uses CMOS photonics to get around limitations of electrical chip I/O bandwidth. Another silicon photonics start-up, Kotura, was swallowed up by Mellanox in 2013. ST Microelectronics and Infinera are also active in the field. The global silicon photonics market is projected to grow from about $25 million in 2013 to between $400 and $500 million by 2020. And while it is exciting to think of what silicon photonics will do for our data centers, it also promises equally exciting advances in powerful and compact chemical and biological sensors.


DAC: Self-driving Cars

DAC: Self-driving Cars
by Paul McLellan on 06-10-2015 at 7:00 am

The keynote on Tuesday at DAC was by Jeffrey Owens of Delphi. For those of you that don’t know, Delphi used to be the part of General Motors dealing with electronics spun out from GM as a separate company in 1999.

Jeffrey pointed out that a modern automobile is the most complex device any of us own, with over 100M lines of code (loc) compared to 70M for Facebook and 12M for Android. A lot of his presentation was about general trends in automotive electronics but the most interesting was towards the end when he finished with talking about the Audi/Delphi self-driving car that recently drove from San Francisco to New York across the entire US. They learned a lot such as the cameras had problems at sunrise when the sun was very low in the sky (I have the same problem driving down 101 when the cameras in my head known as eyes always get blinded at the curve in Redwood City). Road markings differ a lot from state to state but it is necessary to understand them to keep in the correct lanes. The radar they used works fine in tunnels and in the biggest nightmare, crossing old metal bridges with reflecting surfaces everywhere (think of the old cantilever section of the Bay Bridge, for example).

Google’s self-driving cars get a lot of press but Jeffrey pointed out something that they had done with Audi which was to make much of the electronics vanish into the vehicle. There is no Lidar on the roof, in particular. Delphi assumes that would be completely unacceptable from an aesthetic point of view to any OEM (that’s what vehicle manufacturers such as Audi are called in the automotive world, companies like Delphi being known as Tier 1 suppliers). If the mythical soccer mom can veto a car because there are not enough cup-holders for the back seat then she can probably veto a car for having an ugly spinning thing on the roof.

Jefferey said that the car did 99% of the driving autonomously. But as the Wired magazine article on the trip says:Nine days after leaving San Francisco, a blue car packed with tech from a company you’ve probably never heard of rolled into New York City after crossing 15 states and 3,400 miles to make history. The car did 99 percent of the driving on its own, yielding to the carbon-based life form behind the wheel only when it was time to leave the highway and hit city streets.

So the car did all the highway driving autonomously but it couldn’t drive on city streets since they hadn’t done all the detailed mapping information that the Google car, for example, uses to make it possible to handle towns and neighborhoods.

On the show floor I talked to Matt Lewis, also of Delphi, who was one of the engineers that had worked on the cross-country Audi. The picture at the top is the car on the DAC show floor, which is the actual vehicle that drove across the country. As Matt said, “we cleaned it up a bit, it had a lot of bugs on by the end.”

Jeffrey had challenged us to find the sensors since they are not that obvious. Indeed, compared to the Google car they are well camouflaged. Behind plastic panels the radar is out of sight (plastic is transparent to radar). In the centre of the front grille there is Lidar (laser radar). There are cameras behind the mirror on the top of the windshield where they have a good view. Also rear-facing cameras too. Matt pointed out that the radar is standard Delphi radar already shipping in millions of units, as are most of the cameras. So while this is obviously not a production car it is close to a prototype.

See also the Wired magazine article This is Big: a Robo-car Just Drove Across the Country


DAC Keynote: Moore’s Law Isn’t Dead

DAC Keynote: Moore’s Law Isn’t Dead
by Paul McLellan on 06-10-2015 at 5:00 am

There were two keynotes at DAC this morning. I think the official designation of the first one was a “visionary talk” and the main difference was that it was only 15 minutes long. Vivek Singh, an Intel fellow, talked about Moore’s Law at 50: No End in Sight.

He started with a graph showing transistor speed versus leakage which is as good a measure as any of how good a transistor is. When it is on we want it to switch fast and have good drive, when it is off we want it to consume no power at all.

For now things are on-track. Haswell is 960M transistors in 22nm, but Broadwell is in 14nm and 1.3B transistors, an increase of 35%. From 22nm to 14nm the metal pitch decreased from 80nm to 52nm, a reduction of 0.65x which is slightly ahead of Moore’s Law.

The end of Moore’s Law has been predicted for years. Vivek had a few of the comments that have been made over the years (decades even):

  • optical lithography will reach its limits in the range of 0.75um
  • minimum geometries will saturate around 0.5um
  • X-ray lithography will be needed below 1um
  • minimum gate-oxide thickness is limited to about 2nm
  • copper interconnect will never work
  • scaling will end in about 10 years

As he pointed out, things look no different in 2015 (although the precise details of what people worry about have changed, obviously).


For me the big question has always been whether the cost per transistor reduces. After all, Moore’s Law was always an economic law, namely that the cost per transistor is minimized in a given process technology at a certain number of transistors, and that number seemed to increase by a factor of 2 every 2 years (or 18 months depending on which version of Moore’s Law you look at). Intel have always claimed that their cost per transistor continues to decrease in a way that they feel is not happening for their competitors.

Cynics might point out that since Intel manufactures at such high margins, it has never been under pressure to have a competitive wafer price and so it can keep transistor counts decreasing in a way that is not available (or less available) to foundries that have to manufacture chips that are competitive at much lower margins for the mobile industry in particular. As if Rolls-Royce pointed out that they could make cheaper cars if they had to in a way that Ford, say, would find hard.


Vivek’s speciality is in lithography. A simplified view of a stepper has a light source, a mask, some focusing, and a wafer. You probably know that we have not been able to get a light source with a smaller wavelength that 193nm. EUV is the big hope but it is always a few more years out. So we have had to use increasingly complicated optical proximity correction (OPC) to ensure that what we put on the mask produces what we want on the wafer, adding little corners to stop rounding, adding extra bars to stop necking, and so on. But even that has reached its limit and going forward we need to use inverse lithography.

Inverse lithography means starting from the geometry that we want to print and working out what patterns we need on the mask and what light source we need, to get it. This is computationally very expensive but Intel, handily, is in the business of decreasing the cost of computation (I believe Moore’s Law might apply here!).

So for now the innovation continues. 14nm is in full production, 10nm is on track, and 7nm is in research. Vivek is confident Moore’s Law will continue. For the most leading edge designs for the foreseeable future, I’m sure he is right. Whether the cost of computation will continue to fall fast remains to be seen. After all, twice is many cores is roughly twice as many transistors and if the cost per transistor remains flat(tish) then the cost doesn’t come down as you add cores every couple of years.