In the third installment of this series we discussed the status of DRAM scaling and Moore’s law. In this installment we will tackle logic. The focus will be on foundry logic.

Logic technology challenges
In the second installment of this series we discussed constant electric field scaling. As we mentioned in that installment at 90nm logic hit a scaling wall. Basically the gate oxide thickness had become so physically thin that leakage was exponentially increasing with decreasing gate oxide thickness and gate oxide thickness scaling stopped.

Strain
In order to continue to drive performance logic manufacturers turned to mobility enhancement using strain. Carrier mobility in a MOSFET channel is a major component in transistor drive current and it was possible to use strain to continue to drive up drive current while holding oxide thickness constant. By applying tensile strain to NMOS MOSFETs and compressive strain to PMOS MOSFETs significant mobility enhancement was achieved. At TSMC, the world’s largest foundry, dual strain layers (DSL) were implemented at 90nm by applying and patterning compressive and tensile silicon nitride films. DSL layers were also used at 65nm. The tradeoff for DSL is that it requires two additional masks and associated additional processing.

At 40nm two more strain techniques were added by TSMC. Stress memorization was added and embedded silicon germanium (eSiGe). eSiGe is a particularly powerful method for adding compressive strain. Since PMOS typically under performs NMOS on the same process having an extra performance knob for PMOS is a big advantage. eSiGe adds one mask and associated processing.

High-k gate oxide
Although strain provided several nodes of scaling, a solution for gate oxide leakage was badly needed. If a high dielectric constant (high-k) dielectric is substituted for a lower dielectric constant dielectric, the high-k dielectric can be physically thicker than the lower k dielectric while maintaining good electrostatic control over the gate of the MOSFET. After many years of development, Intel introduced the industry’s first high-k gate dielectric at 45nm and TSMC followed at the 28nm node. High-k dielectrics also required metal gate electrodes to maximize the capacitance so the transition was actually to high-k metal gates (HKMG). HKMG reduced gate oxide leakage by several orders of magnitude. The HKMG transition also added process complexity and cost.

Threshold voltage control
At the same time that HKMG was being implemented additional process complexity and masks were also required for threshold voltage control. One of the techniques to prevent transistor punch-through at short gate lengths is the use of halo implants. As gate lengths shrunk to 40nm, the halo implants began to influence threshold voltage so strongly that not only were NMOS and PMOS threshold implants required for each threshold voltage but tailored extension/halo implants were required as well. Some tailoring of the source/drain implants was also sometimes required. This added masks and associated complexity and cost to logic processes.

Fully depleted devices
A standard bulk planar MOSFET has highly doped source and drains of one dopant type separated by a lightly doped channel of opposite dopant type. Above the channel is a dielectric layer with the gate electrode on top. When the gate is properly biased it inverts the channel surface allowing current to flow between the source and the drain. In the off state the gate is supposed to deplete the region between the source and the drain of carriers preventing leakage. The problem is the gate only controls the surface. As gate lengths shrink, leakage currents develop below the region the gate controls. See figure 1, left side.

An alternative to bulk silicon is the use of silicon on insulator (SOI). Early versions of SOI had a thick enough silicon layers that leakage could still occur deep under the gate, see figure 1, second from the left. The “thick” silicon layer SOI is referred to as partially depleted SOI (PDSOI).

The solution to this problem is to constrain the “depth” of the channel region so the gate can fully deplete the channel. There are two main approaches to fully depleted devices, fully depleted SOI (FDSOI) and FinFETs.

FDSOI, figure 1 second from the right makes the silicon layer so thin that the gate fully depletes the channel.

Finally, FinFETs fabricate a narrow fin with gates on both sides or on both sides and the top to fully deplete the channel, see figure 1, right side.

In order to insure a MOSFET is fully depleted in the off state, the silicon layers must be thin enough. For a standard “FinFET” with gates on both sides the fin thickness must be less than one half the gate length, see figure 2, left side. For a “TriGate” with gates on both sides and the top the silicon thickness requirement is relaxed to one times the gate length. Please note that TriGate and FinFET are used interchangeably in the industry today with all “FinFET” implementations being done in the “TriGate” configuration. For FDSOI to be fully depleted, the silicon thickness must be less than one third the gate length, see figure 2, right side.

The merits of FDSOI versus FinFETs have been hotly debated in the industry and on SemiWiki. I will not repeat the arguments here but rather just note that the world’s four largest foundries have all adopted FinFETs for their 16nm/14nm node solutions.

The transition to fully depleted devices actually offers some process simplification in terms of number of steps but FDSOI starting wafer are expensive and fin formation is very difficult to control well enough for high yield.

Other factors
In addition to the factors listed above, each new node has generally increased the number metal layers needed for interconnect and around 20nm local interconnect and metal-insulator-insulator capacitors were added to many processes. At 10nm we also expect to see air gaps introduced in some interconnect layers to reduce parasitic capacitance.

Multipatterning
In installment 2 multipatterning was introduced. At 20nm foundries implemented multipatterning for the shallow trench isolation, gate, contact, and M0 through M5 levels plus associated vias. This dramatically increased mask counts and cost.

Logic scaling
As logic scaled down to 40nm there was a gradual increase in masks and process complexity. At 40nm the addition of eSiGe and the need to tailor implants drove a jump in mask counts. At 20nm the introduction of multipatterning drove another jump in masks and at 10nm additional multipatterning requirements and the introduction of air gaps will likely drive a big jump. At 7nm we have assumed that EUV is available and we see a big reduction in mask count. Assuming this actually happens it drive a lot of other things as we will see later. Figure 3, illustrates the mask count trend for a foundry logic process.

Figure 4. illustrates the resulting wafer cost increases versus node. The big jump in masks and process complexity seen at 10nm also drives a big jump in wafer cost. At 7nm the introduction of EUV has the potential to actually decrease the wafer cost versus 10nm.

Figure 5. illustrates the gate density for foundry logic processes. The logic gate density continually increases until 16nm where the foundries decided to maintain the same back end of line (BEOL) linewidths while transitioning to FinFETs. 10nm is expected to be a full shrink and we are forecasting 7nm as a full shrink as well.

Figure 6. puts together the wafer cost and gate density to produce a cost per gate trend. Once again we have spaced this chart out to align the nodes with years to better show the cost trend. Some other analysts are claiming no cost reduction at 28nm or 20nm, we don’t see that. We do see a slight increase in cost per gate at 16nm due to the lack of a shrink. We also only a small decrease in cost at 10nm due to all the required multipatterning masks. At 7nm assuming EUV can be implemented we see a cost reduction that is pretty close to the historical trend.

Conclusion
The need for multipatterning at 20nm and the pause is scaling at 16nm for the FinFET transition lead to an increase in cost per gate at 16nm and therefore a pause in Moore’s law. At 10nm we see some cost reduction but less than normal due to extensive multipatterning. At 7nm we see the prospect to return to “normal” Moore’s law cost reductions if EUV meets its promise keeping Moore’s law alive for at least 3 more nodes. Without EUV 7nm is likely to be another smaller than normal cost reduction assuming a full shrink is even possible.

Also Read:
Moore’s Law is dead, long live Moore’s Law – part 1
Moore’s Law is dead, long live Moore’s Law – part 2
Moore’s Law is dead, long live Moore’s Law – part 3
Moore’s Law is dead, long live Moore’s Law – part 5