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Predictions about EDA and IP at #52DAC

Predictions about EDA and IP at #52DAC
by Daniel Payne on 06-10-2015 at 4:00 am

On Sunday night at DAC this week I sat in the front row and listened to Gary Smith give his predictions about EDA and IP as an industry. His financial forecast was a $6.8B industry in 2015, growing to $9B in 2019. An ideal company for Wall Street to invest in would have slow and steady growth. If you add semiconductor IP into the forecast then the size would be $12.147B in 2019, where they are tracking 10 categories of IP.

For new markets of growth he sees Mentor expanding into the automotive market, while Synopsys invests in the software market. The embedded SW market has a $2.7B size, so Mentor is best positioned to take advantage of this.

The mechanical design market started out larger than EDA, however EDA has now caught up to mechanical in size. Dominant mechanical companies are PTC and Siemens

Synopsys has acquired some Optical technology, to create a dominant niche strategy. Another new market for Synopsys has been in application development software (Coverity).

Potential adjacent markets for automation include chemical design and Biomedical. This started to remind me of how ANSYS has already been offering multi-physics tools as a more holistic product design approach.

Companies in big data like Google have lured EDA developers away, although ANSYS just acquired Gear in that space

Will mechanical companies try to acquire an EDA company? Does EDA have a choice?

Question: Is the IP market in 2015 and 2019, still $3B?
A: Yes, it’s basically flattening. IP used to cost something with logic synthesis, now its free. The royalty model is weakening, up-front charges still happen, however it is a less profitable market segment. The growth market is for platform-based IP, they have royalties and up-front fees.

DesignWare size IP is becoming a commodity (SNPS is #3 in IP for quite a while), less revenue is expected in the future, causing flattening of IP market. So both SNPS and CDN have to go upstream, like with ARM IP.

Q: What is platform-based IP?

A: Platform-based IP mostly what ARM does (Processor plus memory, 4M gates). As DesignWare ages its value goes down.

Mentor has been able to figure out how to make SW IP for automotive standards.

SDA – System Design Automation tools, need SW ip based on standards.

Q: Is MEMS included in your EDA forecast?
A: Yes, MEMS – design tools are included in EDA market (modified PCB tools)

Q: Are there any growth areas for IP?

A: Yes, Analog and RF IP – will grow, but overall IP is flattened.


Google Smart Lens: IC Design and Beyond

Google Smart Lens: IC Design and Beyond
by Paul McLellan on 06-09-2015 at 1:00 am

Today’s DAC keynote was by Brian Otis of Google about their project, working with Novartis, to build disposable contact lenses that perform continuous glucose monitoring.

Why is this important? There are 382M people around the world with diabetes who typically have to check their blood glucose levels four times a day. This involves pricking the skin and then using a monitor to analyze a drop of blood. There are also continuous glucose monitors (CGM) which also require a needle under the skin connected to a monitoring device. Neither approach is all that pleasant.
Continue reading “Google Smart Lens: IC Design and Beyond”


EDA Acquisition to Drive SoC realization

EDA Acquisition to Drive SoC realization
by Pawan Fangaria on 06-08-2015 at 8:00 pm

A week ago I was reading an article written by Daniel Nenni where he emphasised about semiconductor acquisitions to fuel innovation. We would see that in a larger space, not only in semiconductor and FPGA manufacturing companies (e.g. Intel and Altera) but also in the whole semiconductor ecosystem. If we see it from technical perspective, acquisition will take place whenever there is some value in a company which can produce a larger sum by merging with its acquirer. Although I am not going into financial aspect here, but would like to mention that the financial stress also reduces with the merger of innovative companies.

EDA is an essential enabler of the large size and high complexity SoC realization today. As we see it today, an SoC description has to start from RTL or even from a higher level of abstraction. The design has to converge into the most optimized PPA (Power, Performance and Area) layout in the minimum possible time. So, definitely a large scale innovation is required in EDA space too.

Last week I wrote about an innovative approach taken by Atrenta for designing a lint-clean RTL design that can provide very fast closure of the design. This week, at the start of DAC 2015, we are hearing about this important acquisition in EDA space. Synopsys, the leader in EDA space is acquiring Atrenta, a true RTL implementation, optimization and verification company. Last month, I had written about Synopsys’ ‘Silicon to Software’ solution for semiconductor system design and I see that strategy being implemented quite fast. I have been following Atrenta for some time and I see its SpyGlass platform providing a complete solution at RTL level. In my view, it will complement quite well with Synopsys’ strength in design and verification platform.

Atrenta’s GenSys provides a unique solution for RTL re-structuring for design optimization at RTL stage. And Atrenta’s formal verification technology provides one of the most effective solutions for verification at RTL level. The BugScope provides a very effective ‘Assertion-based Synthesis’ solution. These products can complement quite well with Synopsys’ Verification Continuum and Galaxy Design platforms.

Also, Atrenta’s SpyGlass power, CDC, Physical, constraint management solution, and IP Signoff kit are state-of-the art solutions that work at the RTL level. Clearly this RTL level platform is in the right direction towards ‘Silicon to Software’ strategy of Synopsys.

This combination of technologies will further accelerate the convergence of the overall design towards closure as most of the verification and optimization loops will close at the RTL level. A design re-work loop at the RTL is order of magnitude faster compared to that at gate or layout level. So, this will further boost Synopsys’ ‘Shift Left’ strategy.

Read the press release here for more information.
Also read: “Semiconductor Acquisitions will Fuel Innovation!
A Robust Lint Methodology Ensures Faster Design Closure
SoC’s Shift Left Needs Software Integrity

Pawan Kumar Fangaria
Founder & President at www.fangarias.com


TSMC Shows 10nm Wafer!

TSMC Shows 10nm Wafer!
by Daniel Nenni on 06-08-2015 at 4:00 pm

If you really want to know why I write about TSMC it is all about ego, my massive ego, absolutely. Blogs about TSMC and the foundries have always driven the most traffic and they most likely always will. Semiconductor IP is second, Semiconductor Design is third, and I don’t think that is going to change anytime soon:

SemiWiki BI: Daniel Nenni: TSMC: All
Total Blogs: 137
Total Views: 878600
Average: 6413

SemiWiki BI: Semiconductor IP: All
Total Blogs: 431
Total Views: 1641911
Average: 3810

SemiWiki BI: Semiconductor Design: All
Total Blogs: 1367
Total Views: 4157039
Average: 3041


TSMC came to the Design Automation Conference 16 years ago ushering in a new level of collaboration amongst the fabless semiconductor ecosystem. Other foundries have followed and one could argue that they are the center of the DAC universe. In that time TSMC has completed 15 reference flows (the latest being 10nm) with 7,500+ tech files, 200+ PDKS, and more than 8,600 silicon proven IP titles from .35u to 10nm.

Today, the first day of #52DAC, my prediction of a big crowd has come true. This year the big foundry buzz is around 10nm. TSMC is showing a 10nm wafer for the first time and everybody is wondering if in fact 10nm will arrive in 2016 like promised. I certainly believe it will and so does the majority of the fabless semiconductor ecosystem.

Let’s take a quick look at the TSMC process node revenue start history just for fun:

[LIST=1]

  • .35u 1996
  • .25u 1998
  • .18u 2000
  • .13u 2002
  • 90nm 2005
  • 65nm 2007
  • 40nm 2009
  • 28nm 2011
  • 20nm 2014
  • 16nm 2015
  • 10nm 2016
  • 7nm 2017

    Seriously, we are doing four new process nodes in four years? The fabless semiconductor ecosystem is truly an amazing thing. In regards to process ramp challenges, I remember .13u being very difficult because of the new copper interconnect. 40nm was certainly not easy. 40nm was the last node where TSMC gave you the option of using recommended (yield centric) design rules. Which one of these nodes was the most challenging? You tell me. If you have a design horror story please share it in the comments section and I will give you a free Kindle version of “Fabless: The Transformation of the Semiconductor Industry“.

    TSMC has the Open Innovation Platform Theater again this year in booth #1933. You can see the schedule HERE.The other TSMC related #52DAC activities are HERE:

    TSMC’s booth is jam packed, probably because they are giving away iWatches and other cool stuff. TSMC also had some interesting IoT press today, one even mentioning 10nm:

    Imagination and TSMC collaborate on advanced IoT IP platforms
    Imagination Technologies (IMG.L) and TSMC announce a collaboration to develop a series of advanced IP subsystems for the Internet of Things (IoT) to accelerate time to market and simplify the design process for mutual customers. These IP platforms, complemented by highly optimized reference design flows, bring together the breadth of Imagination’s IP with TSMC’s advanced process technologies from 55nm down to 10nm…

    Cadence Announces Collaboration with TSMC on IoT IP Subsystem
    Cadence Design Systems, Inc. (NASDAQ: CDNS), today announced that it is collaborating with TSMC on the development of an Internet of Things (IoT) intellectual property (IP) subsystem demonstration platform for TSMC’s ultra-low power (ULP) process. Targeting wearable, home automation, always-on and industrial control applications, this IP subsystem, with the support of the Cadence suite of digital and custom/analog tools, provides the opportunity to simplify IoT designs and accelerate the time to market for mutual customers…

    Synopsys and TSMC Collaborate to Develop Integrated IoT Platform for TSMC 40-nm Ultra-Low-Power Process
    Synopsys, Inc. (Nasdaq:SNPS) today announced a collaboration with TSMC to develop an integrated Internet of Things (IoT) platform on TSMC’s 40-nm ultra-low-power (ULP) process technology. The IoT platform incorporates a broad range of DesignWare® IP, including an integrated sensor and control IP subsystem with the ultra-low-power ARC® EM5D processor core, power-and area-optimized logic libraries, memory compilers, NVM, MIPI and USB interfaces as well as an analog-to-digital converter (ADC). The high-performance, low-power IoT platform provides designers with a pre-validated solution that enables them to deliver the energy-efficient, always-on processing required for applications such as sensor fusion and voice recognition…


  • Next Generation Formal Technology to Boost Verification

    Next Generation Formal Technology to Boost Verification
    by Pawan Fangaria on 06-08-2015 at 12:00 pm

    With growing complexities and sizes of SoCs, verification has become a key challenge for design closure. There isn’t a single methodology that can provide complete verification closure for an SoC. Moreover creation of verification environment including hardware, software, testbench and testcases requires significant resources and time. Formal verification tools have been there in the semiconductor design industry and are known to provide exhaustive verification coverage without the need of any testbench. However, they use assertions for particular verification tasks. For performing assertion checks, specific properties are defined in standard languages such as SVA (System Verilog Assertion) and PSL (Property Specification Language). Here is the problem; for designers it’s very difficult to learn assertion languages and use them for design verification to get the full benefit of formal technology.

    Clearly, this is an opportunity available for EDA vendors to automate and ease the verification process where formal technology is combined with ABV (Assertion-based Verification). This approach can provide tremendous benefits provided it can be used efficiently in the overall verification environment. Cadencehas been working since a few years on filling up this gap. Today, I am happy to see this approach really working in Cadence’s JasperGold Formal Verification Platform which is quite nicely integrated with the Incisive Platform.

    This platform provides a unique and innovative way to address the pain points of using formal and ABV technologies. JasperGold (Cadence acquired Jasper Design Automation in 2014) provides Verification Apps that are targeted to solve specific verification problems. The apps are seamlessly integrated between different applications through a common database. They can be easily setup and run. As they are vertically integrated into the overall system, the problems are solved most efficiently using the formal and ABV methods with support from simulation and other metric-driven technology. The needed properties for ABV or formal verification can be automatically created or even pre-packaged properties can be used. Also, Jasper’s patented Visualize[SUP]TM[/SUP]Formal Debug and What-If Analysis environment provides instant feedback on any change in any particular parameter. The effective verification, analysis and debug platform provides 15x performance gain compared to previous solutions.

    The JasperGold Apps Platform is very rich with several verification apps including ‘Formal Property Verification’, ‘Behavioral Property Synthesis’, ‘X-Propagation Verification’, ‘Control/Status Register Verification’, ‘Coverage Unreachability’, ‘Sequential Equivalence Checking’, ‘Security Path Verification’, and many more. Also a custom app can be created for any specific task. The platform architecture is extensible for developing and deploying new apps as needed in the future. There is a single GUI that allows different applications to work together with a consistent look and feel, thus improving designers’ productivity and analysis efficiency.

    Incisive and JasperGold formal engines are combined together for an exhaustive search to find deeper bugs quicker. With the support of different engines, complete proof of properties is obtained on datapath, control logic as well as memory. All combinations of inputs are tried without a testbench. With new formal-assisted simulation methods, deep state-space penetration is done for very deep bug hunting. The new Trident engine provides word-level and memory abstractions that significantly boost performance.

    This platform is integrated with the Cadence System Development Suite where formal-assisted simulation, emulation and verification closure management can be performed in sync with each other. The Indago[SUP]TM[/SUP] debug infrastructure provides a powerful debugging environment. The Indago resources include ‘Debug Analyzer App’, ‘Embedded Software Debug App’, ‘Protocol Debug App’, and ‘Advanced Debug Analyzer App’ that provides on-the-fly what-if analysis for design exploration and debugging.

    In formal-assisted emulation with Palladium XP II, the assertion-based VIP complements accelerated VIP. The assertion-based VIP coded in SVA can replace the checkers which cannot be compiled on Palladium platform and hence removed by accelerated VIP. The formal property creation from emulation traces also assists in debugging.

    The JasperGold is integrated with Incisive vManager to assist in verification status management and closure. The report can clearly show the status of tasks completed by formal. The coverage unreachability app (UNR) automatically generates properties to explore coverage holes and determines if the holes are reachable or unreachable. The unreachable cover points form an unreachable coverage database that guides users to exclude these unreachable cover points, thus saving time.

    The JasperGold SPS (Structural Property Synthesis App) integrates automatic formal analysis with the basic HAL (Cadence HDL Analysis) and provides a fully integrated lint solution. Property grading, violations, and waivers can be analyzed and managed with ease in the Visualize[SUP]TM[/SUP] GUI environment.

    A new LPV App for low-power verification has also been added in JasperGold platform. It performs all low power functional checks, power-aware sequential equivalence check, and runs other formal apps in power-aware mode. This combined with Incisive low-power simulation and Conformal low-power capabilities form a powerful low-power verification solution.

    It was a very pleasant occasion talking to Pete Hardee, Product Management Director at Cadence who explained about this innovative solution in detail. I see this as a unique solution in the verification segment of EDA that significantly boosts verification performance and productivity. The Next-generation JasperGold Formal Verification Platform is being released this month. A live presentation/demo can be seen at Cadence booth #3515 in DAC.

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com


    Synopsys to Acquire Atrenta

    Synopsys to Acquire Atrenta
    by Paul McLellan on 06-07-2015 at 11:17 pm

    I was at the DAC kickoff this evening in the Intercontinental Hotel. I was talking to Dave DeMaria, the senior marketing guy at Synopsys and he told me of a couple of minor press releases due to hit the wire tomorrow morning, didn’t sound important enough to be blogworthy. Aart was there too although I didn’t speak to him. Then at 8pm (11pm eastern) Synopsys put out something much more interesting, a press release that they are acquiring Atrenta, subject to the usual caveats. In particular there will be a waiting period due to HSR review since Atrenta is over the threshold even though it is a private company (when we sold Compass to Avant! we had to go through HSR filing too).

    There have been lots of rumors about potential suitors for Atrenta, not just recently but over the years. Since they operate at the RTL and IP level there is clearly potential for other companies than the usual suspects of Cadence, Synopsys and Mentor. Two that have been much-rumored were ANSYS (who acquired Apache a few years ago) and Dassault (who have some process management solutions and acquired Tuscany Design Automation [disclosure: I was on the board] right at the end of 2012). I’ve never heard it mentioned but another possible candidate might have been TSMC who have used Atrenta’s SpyGlass solution as their “signoff” tool for IP qualification as part of their OIP ecosystem.

    The financial details of the deal were not disclosed. But for sure it was not a fire sale. For a start, the current threshold for HSR filing, the so-called “$50M threshold”, is actually $76.3M this year so we know that the price was at least that high.

    However, since there were multiple companies rumored to be interested I think it is logical to speculate that the price will be at a reasonable multiple on their revenue, itself rumored to be running in the $60M range. At 3.5X revenue that would be $210M so I’ll go with that as my guess. Final answer.

    Of course Synopsys plans to integrate the Atrenta technology into their verification continuum, especially SpyGlass which has wide acceptance. Manoj Ghandi, who is the GM of verification, adds a bit of color (not much, to be honest):Atrenta’s demonstrated leadership in static and formal technologies is recognized throughout the EDA industry, and its technology is used by design and verification teams around the world. Synopsys expects to leverage this strong technology to further improve our Verification Continuum platform to address continually increasing verification challenges, and to support our ongoing R&D collaborations with customers in both verification and implementation.

    Atrenta will be at DAC on booth #1732. Interestingly they just announced the date of their user conference in October. Of course that may take place, since under the rules for an acquisition like this the two companies are not really able to work together until the deal is closed (on the basis that if the deal is struck down then everything should go back to exactly how it was before). However, I think it is more likely that it will just get folded into SNUG.

    The Synopsys press release is here.


    5 Things Chipmakers Are Missing on the IoT

    5 Things Chipmakers Are Missing on the IoT
    by Don Dingee on 06-07-2015 at 7:00 pm

    When the RISC movement surfaced in 1982, researchers analyzed UNIX to discover what instructions multi-user code was actually using, and then designed an instruction set and execution pipeline to do that better. Fewer instructions meant fewer transistors, which led to less power consumption – although in the original Berkeley RISC disclosure, the word “watts” never appears. Even during the early development of ARM, lower power consumption was completely serendipitous.

    As the mobile SoC began gathering momentum in 1992, the benefits of fewer transistors, smaller dies, and less power were obvious. New developments were necessary. Low power DSP capability, whether through hardware multipliers and SIMD enhancements, or efficient DSP cores, was a must for GSM signal processing. Code density expansion was a BOM killer, giving rise to the ARM Thumb instruction set. Efficient Java execution gave rise to ARM Jazelle.

    In 2002, smartphone efforts ramped up. Faster processors such as ARM11 appeared. Graphics needed to improve, leading to development of mobile GPU cores such as the Imagination PowerVR MBX Lite, and later development of OpenGL ES. Operating systems started to change, indicating a shift from Symbian, Palm, and Microsoft to newer ideas. Android was just a twinkle in Andy Rubin’s eye, and Apple playing with the beginnings of Project Purple and multi-touch.

    Each of these phases blew up everything we thought we knew about chipmaking. Running in parallel was a constant push for more, smaller transistors, driven by the economics of the PC and later by consumer devices. This lead to bigger wafers and smaller geometries and FinFETs and FD-SOI and gigantic FPGAs and manycore processors.

    It’s 2015, and the Internet of Things is here. We should be talking about a fundamental shift in the way chips are designed and made specifically for the IoT – but, we’re not, because it hasn’t really happened yet.

    True, we have dozens of microcontroller architectures and billions of chips out there. These were designed to put intelligence on a point. Control some buttons. Light some LEDs. Spin a motor. Read a sensor. Automotive and industrial types discovered they could be put on a simple bus, like CAN. Some really brave folks started putting radios on chip, like 802.15.4 or ISM band, and protocol stacks like ZigBee and Bluetooth and Thread found homes. That lead to substantial IoT progress from the likes of Atmel, Microchip, NXP (nee Freescale), Silicon Labs, TI and others – but not a breakthrough of the likes we saw in earlier phases, at least so far.

    DAC52 is offering a Management Day session on June 9th to discuss “big data” in two sessions, one from the perspective of behavioral analysis and design closure in EDA, and the other from possible trade-offs in connectivity. At least we are talking. We know we have way too many connectivity standards, and not enough data-level interoperability, when it comes to the IoT.


    But we still don’t have the right chips, or the right discussion. What we have is what I call “the IoT paint job”, where everyone lists IoT on their website and booth signage to draw traffic. Just watch how many press releases come out of DAC with the term IoT somewhere. Not to disparage anyone in particular, there is some good stuff happening, and there’s some fluff. ARM is making great strides with a focus on the IoT. Mentor understands embedded software versus SoC design, and Synopsys has its ARC core and virtual prototyping.

    What I’m saying is we need more actual IoT progress. At least 5 things are missing:1) Processes. Somewhere in between 14nm FinFET and 130nm BCD lies a sweet spot for the IoT. We know mixed signal and embedded flash get difficult below 28nm. MEMS also presents some challenges in economics. Talk of trillions of chips and 2 cent parts makes most chip firms yawn – it hasn’t happened, and frankly isn’t a sustainable model for most companies, especially the ones tied up at the 14nm end of the spectrum needing bigger ASPs to offset billions of cap ex dollars. Where is a true, dedicated IoT process, that can handle both the technology and the business model? (Hint: ARM announced 55ULP initiatives with TSMC and UMC recently.)

    2) Subthreshold. The MCU firms all understand ultra-low power, and are fast to point out metrics like uA/MHz and various modes from catnapping to comatose. Super. Business as usual, hasn’t changed much since the 1980s except the power figures have gotten smaller. The fundamental change that has to happen is subthreshold logic, or something akin to it, that redefines the equation. Companies like Ambiq and PsiKick are out there. Sunrise Micro Devices, incubated by ARM and recently reacquired, is now the technology inside the ARM Cordio radio.

    3) Mixed signal. I cut my teeth making drones fly (we didn’t call them that then, they were RPVs) with a lot of LM148s and Siliconix analog switches way back when. Mixed signal is near and dear to my heart. We integrated mixed signal on MCUs, great. I get to choose from a thousand parts using a parametric search hoping I can find the exact combination of resolution, channels, and pinouts I need. There is Cypress PSoC, and Triad’s VCA, and a MAX11300 from Maxim Integrated, and not much more in configurable mixed signal. The counter argument is just put a dedicated IP block on an dedicated SoC design, and that works if you have a few million dollars. When mixed signal gets as easy to create with as CPLDs, we’ll have something.

    4) Optimization. If all the rage in server design is workload optimized processors, why isn’t that true for the IoT? A lot the focus on the IoT is on one tier: the edge. But there is so much opportunity to optimize at the gateway and infrastructure levels. Network-on-chip is a big help in making MCU architecture more SoC-like. We need to start looking at IoT traffic not as a bunch of packets, but in thread form, and figure out what makes it go faster. “Meh, IoT is low bandwidth.” I hear that all the time and for a particular sensor at the edge that may be true – but toss 10,000 sensors together in real time with predictive analytics engaged and tell me how bandwidth looks then. It worked for RISC, workload optimization is needed for IoT parts.

    5) Programming. ARM is rallying around their vision, mBed OS, with optimized Cortex-M IP. Check. How about optimizing for Google Brillo? Or maybe something that runs MQTT or DDS better? This may be the biggest opportunity yet, really understanding IoT software. Another change that chipmakers need to be aware of: not everything is C, or Java. Those are two of the most popular languages in the world. C was especially great when we worked with Unix and programmed hardware down to the bit level. On the IoT, many other languages are emerging (and yes, some are on top of C). Coders today are learning in Python – embedded purists need to stop barfing on it as interpreted. For distributed data analysis there is Lua. For safe, concurrent threads, there is Rust, which has just put out its first stable release. It’s a new world, and the C compiler and debugger isn’t the only vehicle anymore, or even the right one.

    We’re still working very much on the old chip technology base when it comes to IoT design. When Steve Jobs introduced the iPhone in 2007, he quoted Alan Kay: “People who are really serious about software should make their own hardware.” We saw what Apple did, making its own chips to run its own software better.

    Well, the IoT is all about software. It’s time we make chips just for it.


    Turning the Automotive Development Process Upside Down

    Turning the Automotive Development Process Upside Down
    by Daniel Payne on 06-07-2015 at 2:00 pm

    Most of us drive automobiles and have a vague idea that the development of our cars takes many years, millions of dollars, is a proprietary process and require huge factories to produce. A relatively new company called Local Motors founded in 2007 has started to turn the automotive development process upside down because they do things differently, like:

    • Have a community of over 30,000 designers online that collaborate
    • Complete product developments 5X faster
    • Use 100X less cost for development

    Take a look at some of the cool ideas that have been brought to life by Local Motors with their collaboration process:

    In the DAC pavilion on Wednesday, June 10th from 10:30AM to 11:00AM you will hear Corey Clothier talk about, “How Open Collaboration is Fostering the New Mobility Revolution“. We’ve all heard about how Google has a self-driving car project, however the folks at Local Motors are also entering that market, so stay tuned to hear about their developments in the near future.

    Instead of using a large, centralized, traditional manufacturing factory the vision at Local Motors is to use local, micro factories, where they can produce a 3D printed car. Their current headquarters is in Phoenix, but soon you’ll see micro factories in Tennessee, Maryland, Detroit, Florida and Europe. If all goes to plan then in 10 years their will be 100 micro factories around the globe.

    They have an electric vehicle that will be through all of the mandatory testing procedures in 2016, ready for sale in 2017. One intriguing aspect of a 3D printed car is that you can actually have your car recycled in a few years, then receive a new body style in return as an upgrade.

    The general process at Local Motors is:

    [LIST=1]

  • Design community submits new ideas
  • Community then votes to decide on the best ideas
  • Prototypes are made
  • Micro-manufacturing is done
  • Consumers can buy, then designers share in the revenue

    Here are a few more photos from transportation systems designed by this collaboration process:

    All of this collaboration vision from Local Motors reminds me of the book from Alvin Toffler called The Third Wave, where the concept of mass customization was introduced. Consumers could create their own personalized automobile in the color, length, weight and other features to suit their individual tastes, instead of having the factory limit them to a few makes, models and trim packages. Attend the DAC Pavilion session and see the future now.


  • ESD Protection Network Checking is Difficult But Necessary

    ESD Protection Network Checking is Difficult But Necessary
    by Tom Simon on 06-06-2015 at 6:00 pm

    I’ve written before about anti-fuse non-volatile memory, where the gate oxide is intentionally damaged in order to create a readable bit of data, but this is what most circuit designers never want to have happen to their logic gates. However, since the advent of MOS transistors the issue of Electrostatic Discharge (ESD) and the resulting damage from voltage induced currents has been a key reliability issue. While it is possible to reduce the likelihood of an ESD event though proper handling and environmental controls, it is not possible to completely prevent them. An ESD event can cause excessive current that can damage or vaporize wires and vias, it can melt p-n junctions, and of course it can damage gate oxide.

    The world of ESD is a world of things out of the normal. Circuit designers like it when transistors and interconnect are behaving linearly. There is nothing linear about ESD. Understanding and preventing ESD events and the resulting damage takes us into a world where everything is operating at extremes.

    Shunting damaging currents caused by high electric potential is done by protection circuity in the pad ring. The protected devices in the core should never see high voltages or currents. It is the behavior of the ESD protection network that determines how the chip will fare. While the protection network is made of devices that are familiar, they are operating in modes that cannot be easily simulated using traditional circuit simulation methods.

    There are a number of commercial solutions for analyzing ESD protection networks. Magwel is a company that started out developing field solvers for modeling transistors, but at the behest of several customers has developed a comprehensive ESD analysis solution called ESDi. I have been learning about Magwel and ESDi because I am working with them on several projects.

    Magwel’s ESDi has a number of notable advantages over the previously existing tools. For one, ESDi can identify triggering of parasitic Bipolar junctions in MOS devices. It does this as it extracts the ESD protection network in the layout. These devices can be pre-characterized by the TCAD group and table models can be used to predict their behavior as part of the ESDi tool run. The same goes for the parasitic junction diodes formed in the MOS devices. This allows for proper modeling of avalanche and snap back behavior during ESD events.

    Another key analysis capability of ESDI is that it models triggering of multiple protection devices, and can allocate the current among the various paths available. ESDi can do this because it uses extracted network resistance to calculate voltages at all the device pins. ESDi has a sequential algorithm that then allows for multiple devices to trigger. This avoids pessimistic current predictions, eliminating extra downstream work fixing problems that do not exist. It also can report electro-migration violations and high current densities along discharge paths.

    Another advantage of ESDi is that it goes beyond what electrical rule checkers (ERC) do in determining if there is an adequate current limiting resistor in the discharge path. Rule checkers can tell you if you missed a resistor, but it cannot check to see if it has the correct value.

    Magwel’s ESDi has many other unique features that make it extremely fast and accurate. Magwel will be at DAC in June this year in San Francisco. You will see their booth right as you enter the exhibit hall. Please contact them at sales@magwel.com for a demo at DAC or just drop by to learn more about ESD protection network verification. Magwel also has tools that address power transistor switching analysis, and thermally adjusted spice modeling for transistors.


    Vacationing with the Fabless Semiconductor Ecosystem!

    Vacationing with the Fabless Semiconductor Ecosystem!
    by Daniel Nenni on 06-05-2015 at 4:00 pm

    The Design Automation Conference is the largest and most diverse event in the fabless semiconductor ecosystem. Next week in San Francisco you will see technology and people you have never seen before. You will benefit from the efforts of hundreds of thousands of semiconductor professionals like myself who have dedicated their careers to this industry. This is my 31[SUP]st[/SUP] DAC and judging by the keynotes, panels, fireside chats, and other events, this year looks to be both interesting and entertaining, absolutely!

    You can check the #52DAC highlights HERE.

    The Design Automation Conference (DAC) is recognized as the premier conference for design and automation of electronic systems. DAC offers outstanding training, education, exhibits and superb networking opportunities for designers, researchers, tool developers and vendors.

    Besides being the number one EDA Company, having the largest semiconductor IP portfolio, and the biggest user group, Synopsys is also one of the most diverse companies with the deepest executive bench in the fabless semiconductor ecosystem. Take a look at theEDA Mergers and Acquisition Wiki and you will see why. Synopsys is made up of more than a hundred different companies from around the world. I worked for several of those acquired companies so I know this by experience.

    Synopsys is the Silicon to Software partner for innovative companies developing the electronic products and software applications we rely on every day. Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity solutions. Whether you’re an SoC designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products.

    What happens when you put the number one event and number one company together? Some very cool stuff of course:

    Silicon to Software Theater
    Join us in Synopsys Booth #2133 to hear industry leaders discuss exciting new developments and the latest trends in IoT, automotive, FinFET, and mobile computing design and use.

    Conference Presentations
    Hear Synopsys speakers at conference panels, tutorials, poster sessions, and more.

    Special Events (free food!)
    Join us at the Park Central Hotel (formerly Westin) to hear users discuss the latest industry trends and their experiences using Synopsys technologies, including AMS verification, custom implementation, IC Compiler, PrimeTime, SoC verification and more, in their SoC designs.

    Partners & Standards
    See Synopsys highlighted in the DAC exhibit hall at many of our partners’ booths and learn about standards activities at DAC.

    Automotive Village
    Learn about the newest advancements in automotive design.

    ARM Connected Community
    Learn how ARM and Synopsys collaborate to enable you to create leading-edge ARM Powered products.

    My beautiful wife and I will be attending many of the parties but not all. Hopefully we will see you at the Love IP Partyon Monday night. SemiWiki is a participating company so when you register select us as your sponsor and be our guest (space is limited).

    On Wednesday night SemiWiki is again sponsoring a DAC reception. Last year we did a book signing, this year there will be SemiWiki bloggers mingling and it would be a pleasure to meet you. In addition to free food and drink there will also be tokens of our appreciation available in thanks of your support in making SemiWiki one of the top rated industry portals! I hope to see you there…

    WEDNESDAY June 10, 6:00pm – 7:00pm | Esplanade Foyer
    NETWORKING: Reception – All Invited!
    Join attendees for refreshments and lively discussion recapping the days’ events.

    Sponsored by: SemiWiki.com

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