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GlobalFoundries Adds RF to 28nm

GlobalFoundries Adds RF to 28nm
by Paul McLellan on 06-05-2015 at 7:00 am
Categories: Foundries, GlobalFoundries

The internet of things (IoT) or internet of everything is a term that is into the red zone on the hype-meter. But it does genuinely have something of substance behind the hype. The thing that is a little deceptive is that the IoT term makes it sound like it is a market, but in fact it is several different markets: medical, automotive, industrial, metrology, fitness and more. But these different applications largely have several things in common. They are cost-sensitive, they require long battery life (or even scavenging power from the environment) and they require connectivity, almost always wireless.

My expectation is that very few IoT designs will be large SoCs in advanced FinFET processes. The costs are too high, the difficulty of doing the design is too high, and the need for that many gates doesn’t exist. As for many other classes of design, I think the sweet spot for some time will be 28nm. This is the last process node that doesn’t require the expense and delay of double patterning, a lot of capacity is in place from a number of foundries, and much of the equipment is depreciated. I am not alone in believing that 28nm will be a very long-lived process generation. But for IoT there is a problem: wireless interfaces require RF.

A couple of weeks ago GlobalFoundries announced a new 28nm process 28SLP-RF that is targeted at IoT and mobile applications. This is a process that is built on the foundation of the existing field-proven cost-optimized 28SLP process adding RF modeling. This is a HKMG (high-K metal gate). It is gate-first which GF claims is “up to” 30% cheaper than equivalent gate-last processes (10% mask adders, 10% power management and 10% area scaling disadvantage of gate-last).

I talked to Mike Chen (Deputy Director, Product Line Management) and Peter Rabbeni (Director, RF Segment Marketing) about the new process and the ecosystem around it. What is being announced is essentially adding an RF component to the existing ramped 28SLP process. GF already have some customers who have designed their own RF on top of the basic process but this is purely as a COT design. What is new is that the RF is being made available to anyone doing design at 28nm. The PDK exist and can be downloaded from the GF website (for qualified companies). There are reference flows.

Compared to the previous process node, 40LP, it has:

  • Twice the gate density
  • 36% speedup with full overdrive option
  • 40% power reduction
  • 1.6GHz performance for the ARM Cortex-A9
  • And now RF

I asked Mike and Peter about IP. After all, most groups designing IoT applications are not really capable of designing radios on the bare silicon and even for groups who have in-house RF designers, it is slow and expensive to design a wireless interface. They told me that they were working to make available both bluetooth and WiFi interfaces although it was too early to tell me which company they were working with and giving early access to the process.

Silicon results have demonstrated high-frequency performance (310GHz) and low flicker/thermal noise providing chip designers flexibility in optimizing core RF performance and functionality. The 28SLP-RF process technology is designed for devices that require low standby power and long battery life integrated with RF/wireless functionality. The technology is enabled with key RF features, including core and I/O (1.5V/1.8V) transistor RF models along with 5V LDMOS devices, which simplifies RF SoC design. For passive RF devices, 28SLP-RF offers alternate polarity metal-oxide-metal (APMOM) capacitors up to 5V, deep n-well devices, diffusion, poly and precision resistors, inductors and an ultra-thick metal (UTM) layer.

The process is fully qualified from -40° to 125° and MPW shuttles run quarterly, and perhaps more frequently depending on demand and urgency. GF are already working with some lead customers. The expectation is that lead customers will have prototypes available late 2015 with production in 2016.

The press release with more details is here.

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Automate those voltage-dependent DRC checks!

Automate those voltage-dependent DRC checks!
by Beth Martin on 06-04-2015 at 10:00 pm
Categories: EDA, Siemens EDA

Because IC design and verification never gets simpler, verification engineers now have to comply with voltage-dependent DRC (VD-DRC) rules. What does this term mean, and what new challenges does it bring to the DRC task? I’d like to share what I learned during another water-cooler conversation with Dina Medhat, senior technical marketing engineer at Mentor.

VD-DRC rules require different spacings based on either the operating voltage on the geometries being checked, or the difference in voltages between different geometries (wires) running next to each other. Because there might be many voltage domains and voltage differentials in a modern SoC design, a designer can no longer apply just one spacing rule per metal layer.

The traditional challenge, says Medhat, is how to get the voltage information for each net to apply the appropriate spacing rule. She said customers often ask questions like, “How can we create an automated solution to this checking task?” Or more specifically, “How can we capture the voltage information without having designers add layout markers to designate them?” Before answering these questions, let’s have a deeper look at the technical problem that they’re facing.

In VD-DRC, spacing requirements between nets are determined by the operating voltages present on the nets. But, how do you define these voltages in a layout? The best-known method is to add markers (either text layers or polygons) to the layout with the expected voltage value. Because the designer must add the correct marker manually, the process is subject to human error. If the markers are not present, or they are incorrectly placed, false violations can occur. These false errors can be very difficult and time-consuming to debug, which is a waste of time and resources. But even worse, marker errors can result in rule violations that sneak by the check, and result in device failure down the road. Moving to more complex designs and advanced process nodes, says Medhat, greatly increases the complexity of VD-DRC and the challenge of defining voltages in a layout.

Checking errors that are introduced during DRC because of improper rule coding or erroneous voltage markers can generate hundreds of errors that need to be analyzed and debugged, and the false DRC violations then need to be waived by the designer, which introduces even more time and overhead. Inaccurately marked layouts can also result in substandard routing optimizations, if the router uses general worst case rules, rather than rules based on the actual voltages present on various nets of the layout.

Medhat wants to solve VD-DRC challenges with an automated flow that can propagate realistic voltage values to all points in the layout, eliminating the more fallible manual process. Mentor has worked directly with customers to build such a flow based on Calibre PERC. “The VD-DRC flow first identifies the supply voltages for the design, and then uses a voltage propagation algorithm to determine the voltages on internal layout nodes,” says Medhat. “The voltages are computed automatically based on static propagation rules, which can be user-defined for specific device types. The algorithm is applied to the netlist to identify target nets and devices needed for VD-DRC.”

Because the netlist information is preserved along the entire flow, the results are context-specific, making them easy to debug. This integration between netlist, connectivity-based voltage analysis, and geometric analysis is important. Once the node voltages are computed, the tool writes out the voltage information as text markers into a separate file, which is given as an input to the Calibre tool running the DRC sign-off deck.

This automated flow doesn’t require any changes to sign-off decks, and it generates the voltage information automatically, without requiring any manually added physical layout markers. This approach reduces both the design team workload, and the chance of missing real violations or producing false violations.

If you’d like to learn more, Dina Medhat is presenting this work at the DAC Work-In-Progress session Wednesday evening, June 10, from 6:00-7:00 pm. Bring your questions and observations!

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Is Avago Chip Industry’s Cisco?

Is Avago Chip Industry’s Cisco?
by Majeed Ahmad on 06-04-2015 at 3:00 pm
Categories: EDA

If Ford is a reference model for value chain in the Industrial Age, Cisco is the icon of the twenty-first-century digital economy. The networking gear maker, who achieved phenomenal growth with the rise of the Internet, has been remarkably successful in snapping up and integrating scores of companies for products it could not innovate.

Take Crescendo Communications, for instance, the company that Cisco bought in 1993 just to meet needs of two of its major customers: Boing and Ford. Eventually, the acquisition transformed Cisco from a router company to a routing-plus-switching vendor.


Avago’s aggressive acquisitions are reminiscent of Cisco’s 1990s era of takeovers
(Image: Avago)

Cisco made one acquisition after another to capture intellectual assets and next-generation technologies during the 1990s. By the end of the decade, Cisco had purchased more than 50 companies to dominate the enterprise networking market. Cisco mastered the art of mergers and acquisitions, meeting immediate objectives to expand into new market opportunities. This aggressive pattern had become its modus operandi to assemble new market strategies.

It’s pretty ironic that Cisco copied the HP model of dividing the market into small segments and leading each one of them. However, HP itself failed to respond to the web challenge while rivals like IBM and Sun Microsystems quickly identified themselves with the Internet tidal wave. In 1999, the company that more or less invented Silicon Valley decided to break itself to get more focused and nimble. The new HP would take care of computing and printers business while spin-off Agilent Technologies would oversee test and measurement operations.

Avago’s HP Lineage

And that fascinating technology history brings us to the talk of the town, Avago Technologies Ltd, an HP progeny that has rocked the semiconductor industry by gobbling a larger chipmaker than itself. Avago has mounted an ambitious $37 billion takeover of Broadcom Corp., the largest acquisition in high-tech history.

Avago has been a relatively less known company that usually remained outside the media limelight. That’s partly because its chief Hock Tan wanted to spend less on marketing. So it’d be worthwhile to take a peek at the company’s lineage to the HP Way and see how it has managed to become the sixth largest semiconductor company in the world.


In 2000, Agilent’s IC division created first-generation lab-on-a-chip that integrated a large number of chemical manipulations on a single die (Image: Agilent Technologies)

Avago’s genesis can be traced back to 1961 when HP started a semiconductor products division and began the pioneering work on products such as light-emitting-diode (LED) displays, fiber-optic transmitters and optical mouse sensors. However, after HP spun off Agilent Technologies in 1999, the history began repeating itself. The testing and measurement business took over the limelight in the new company and semiconductor products went to backwaters.

Consequently, Agilent, still a big piece of old HP, was ready to be split again in 2005. Private equity firms Silver Lake and Kohlberg Kravis Roberts & Co. spent $2.66 billion to acquire Agilent’s semiconductor business and created a new chip outfit: Avago. The new chipmaker—which specialized in markets such as lighting, fiber-optic gear and power amplifiers—went public in 2009 at $15 a share.

Avago’s Acquisition Spree

Avago has shown that it can make deals work. For example, in 2013, it acquired LSI Corp. for $6.6 billion. The purchase of LSI, a maker of networking and storage chips, allowed Avago to gain traction in rapidly growing cloud computing, web services and data center markets. Avago’s market value has tripled since it bought LSI less than two years ago.

Emulex Corp. is Avago’s most recent acquisition before the Broadcom deal. It’s interesting to note that Broadcom had tried to buy Emulex in a hostile takeover bid back in 2009. In February 2015, Avago gobbled the maker of network connectivity and monitoring chips for $600 million.

Avago—itself a product of two spin-offs—first went to shopping in 2008 when it bought Infineon’s bulk acoustic wave business for $23 million. The first full-fledged company that Avago acquired was CyOptics Inc., a supplier of optical chips and components for telecom and data communication markets that Avago snapped for $400 million in cash.


Hock Tan: A big job ahead of him

For the Broadcom takeover, interesting bits have surfaced in the media, and they clearly show that Avago’s latest chip deal is more about gaining scale than anything else. Back in February this year, when the news about NXP’s acquisition of Freescale surfaced, it has been reported that Avago was also a contender for Freescale.

There are other media reports about Avago being out with a horde of cash and trying to buy another chip company. The names Maxim Integrated, Renesas and Xilinx have emerged in relation to Avago’s pursuit of an acquisition just before the Broadcom deal.

The merger of Avago and Broadcom creates the second largest communications chipmaker after Qualcomm and fourth largest wireless chipmaker after Qualcomm, Samsung and MediaTek. That’s quite a bit of scale. Now Hock Tan and his lieutenants have to show that they can execute. The scale in case of “New Broadcom” is going to be much larger than LSI operations.

The new company will use the Broadcom brand once the merger is complete. The name Avago won’t be there anymore, but if Tan and his team are able to pull this off, the legacy of Avago will remain just like HP’s DNA. The scale of Avago’s acquisitions is nowhere near Cisco, but there are still similarities between the two companies.

Also read:

Semiconductor Acquisitions will Fuel Innovation!

End of the Road for Micrel

Three Colorful Bytes from the NXP History

Majeed Ahmad is author of books Smartphone: Mobile Revolution at the Crossroads of Communications, Computing and Consumer Electronics and The Next Web of 50 Billion Devices: Mobile Internet’s Past, Present and Future.

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The Transistor is the Foundation of TCAD to Signoff

The Transistor is the Foundation of TCAD to Signoff
by admin on 06-04-2015 at 7:00 am
Categories: EDA, Silicon Photonics

At the most basic level, semiconductor design is all about transistors. Any report on a large microprocessor or mobile application processor is in awe about how many transistors it contains. Moore’s Law is all about the most economic way to manufacture transistors. Each process generation for the last decade and looking ahead is built around new transistor types: strained silicon, Hi-K metal gate, FinFET, FD-SOI, silicon nanotubes, carbon nanotubes, spintronics. Outside of SoC memory architectures have always been about transistors, deep trench DRAM, vertical Flash. Power (high voltage) is moving to new materials such as SiC and GaN.

The transistor starts with the process. Technology CAD (TCAD) is the method of building up the transistor according to the process recipe and then analyzing the resulting transistor(s) to gradually converge on the desired characteristics.

The TCAD models are too slow and unwieldy to be used directly for design, a model extraction phase is required whereby the results of many TCAD characterization runs are coalesced to create a SPICE model that can be used in simulation and PDKs to allow larger designs to be undertaken.

The next level up is a traditional analog (or custom digital) flow. This consists of a high capacity layout editor (some cells are small, but others such as memories or flat-panel-displays are huge), a full 3D field-based extractor to get all the precise parasitics, and then accurate SPICE circuit simulation that can take the models from TCAD (or silicon characterization) and produce the usual performance data.

One level up from there is the requirement for full power integrity analysis: current droop due to resistance (IR drop), electromagnetic effects (EM) and thermal effects (heating due to design activity). For the most extreme environments, such as space or even avionics, single-event effects and threshold drift due to dose over time may also be required.

These transistor technologies can be applied to provide solutions in a wide variety of vertical markets. The key markets where Silvaco’s suite of products is used are:

  • Displays: this includes TFT, LCD and OLED
    • Almost all manufacturers of displays use the Silvaco suite for design and most of these designs are in high-volume manufacturing.
  • Power (high voltage/current): including DMOS, IGBT, SiC and GaN
    • Recently silicon-carbide (SiC) and gallium-nitride (GaN) and other materials have started to gain attention. Their wide bandgap means that they should have better performance than silicon. But that wide bandgap also leads to some challenges in simulation since accuracy needs to be very high.
  • Radiation and soft error reliability: SEE, SEGR, total dose
    • High energy particles cause two big problems. First, single-event-effects (SEE) including single-event-burnout (SEB) and single-event-gate-rupture (SEGR). A second effect is that the build up of the dose of radioactive particles can cause threshold shifts in the transistors which can result in long-term reliability issues.
  • Optical: including CCD, CIS, solar, silicon photonics and laser
    • The optical segment deals with the design of semiconductor devices that interact optically with the environment, either where light is an input (such as optical sensors) or where light is an output (such as semiconductor lasers).
  • Advanced CMOS process development: FinFET, FD-SOI and more advanced
    • Design of advanced CMOS processes starts with TCAD. It is too slow and expensive to run real wafers until relatively late, and much better to use rapid prototyping in TCAD to decide on an integrated flow followed by detailed simulation to determine process recipe details.
  • Analog and high-speed I/O design: PLL, ADC, SERDES etc
    • The real world is analog and as more and more of a system is integrated onto a single SoC, the requirement for high accuracy analog design in a mainstream processes becomes increasingly acute. At the same time, digital interfaces such as SERDES have to be designed as analog blocks.
  • Foundation library and memory design: standard cell, SRAM, DRAM, flash
    • One of the critical aspects of bringing a new process into production is getting the foundation IP designed (at a minimum, standard cells and SRAM memories).

Today Silvaco brought their new website online. This reflects the emphasis on these 6 vertical markets. The navigation is now across the top. A good place to start is to click on “Solutions Overview” and you will see the graphic above. This is clickable for both the technologies involved (down the left hand side) and for the vertical markets (across the top).


Silvaco will be back at DAC for the first time in a decade or more. They will be on booth 532. If you are coming to DAC then come by and see how Silvaco’s TCAD to Signoff technologies can help you in your own vertical markets.

Silvaco’s new website is here.

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MIPI Beyond Mobile, Semiwiki Blogger Paper at #52DAC!

MIPI Beyond Mobile, Semiwiki Blogger Paper at #52DAC!
by Daniel Nenni on 06-03-2015 at 10:00 am
Categories: EDA, IoT, IP

IoT or wearable: it’s fascinating to see how many articles, blogs, and comments have been posted about them during the last two years! IoT business potential is huge as are the number of possible applications. If we summarize the functions within a wearable system we can count:

[LIST=1]

  • CPU: it can be a standard Microcontroller or an embedded CPU core (IP)
  • Wireless communication sub-system (ZigBee, BLE, WiFi, etc.)
  • Display device (screen)
  • Sensor(s)
  • Camera and Sound (both optional)

    What is most important for a wearable device? I would put ultra low power consumption (or power efficiency) as the very first and TTM a close second. The equation can be synthesized as: a successful wearable device will need internal interfaces between the chip being designed for low power, functionally and silicon proven to accelerate Time-To-Market, and sized for Mobile application. Does this ring a bell?

    MIPI specifications from the MIPI Alliance have been successfully integrated into smartphones and even low cost phones for years. A quick evaluation suggests that about 7 to 10 billion MIPI powered chips have been in production this last year. It’s tantalizing to imagine that some of these MIPI specifications could be used to support wearable applications! The paper to be presented at DAC IP track by Semiwiki blogger Eric Esteve “MIPI Beyond Mobile” is trying to give some answers. Just to clarify, this paper has been written from the results of the “MIPI Ecosystem Survey” generated by IPnest (5 to 6 weeks of full time work). It’s not an opinion but the result of systematic research. One of the key findings is synthetized in the above table “MIPI Specification Adoption in Mobile (phone and media tablet)”. Because MIPI specifications were originally developed to support these applications this table is our reference, based on facts.

    We clearly see that the Multimedia specifications for Camera and Display have the higher adoption rate. Soundwire adoption looks low but when you consider that the preliminary specification had been released a few weeks before the survey there is no doubt that this 3[SUP]rd[/SUP] Multimedia specification has a bright future!

    Still in Mobile, the Radio frequency (RF) specifications, DigRF, and RFFE are seeing a good level of adoption. They are almost at the same level as Universal Flash Specification and UniPro, both being used together to support the interface with MIPI powered flash.

    Just a word about the various PHY specifications (D-PHY, C-PHY and M-PHY). To support a Camera, Display, DigRF, and UFS you need to implement one of these. I could try to explain how to select one PHY or another but it would require many more words than I have left here! Just keep in mind that the lower speed D-PHY (up to 2.5 GTransfer/s and per lane) is the most commonly used because the cost of ownership (development or IP cost and area impact) is lower.

    The paper to be presented at the DAC IP Track will address the following questions:

    • Which specifications are expected to be used in IoT? In Wearable? In Automotive?
    • Can we find a correlation between these emerging segments and the geographical locations? The company type (small or large company, long time established or start-up)?
    • What will the impact be on the IP business of these emerging applications? What is the impact of the emerging (Asian) chip makers targeting mobile on this IP business?

    Just come to the IP Track 23, Dr. Eric Esteve will answer these questions and more. If you can’t attend DAC in San Francisco the presentation will be posted by the DAC committee after the conference.

    I hope to see you there!

    • Posted on

    Logic Synthesis Reborn

    Logic Synthesis Reborn
    by Daniel Payne on 06-03-2015 at 9:45 am
    Categories: Cadence, EDA

    Combine the pressures of Moore’s Law which enable billion transistor SoCs and the shortened time to market from consumer electronics product cycles and you have the perfect storm for EDA tool vendors. A modern SoC can have 500 or more blocks, creating both a design and verification challenge. How in the world do you write software that can handle larger designs, in a shorter amount of time, with better PPA (Power, Performance, Area) results?

    Logic synthesis is a workhouse EDA tool that converts a design written in languages like SystemVerilog and VHDL into technology-specific gates that are logically optimized and take into account physical effects like interconnect estimates. The design process with logic synthesis is quite iterative, so any improvements in run time, capacity and PPA make a big difference to product schedules.

    What’s New

    The trend over at Cadence and other EDA vendors is to rewrite their code in order to meet these increasing market challenges. Paul Cunningham of Cadence spoke with me last week about a new logic synthesis tool called Genusthat is the successor to RTL Compiler. The benefits of using the new Genus tool for logic synthesis are:

    • Speed, up to 5X faster than RTL Compiler
    • 2X fewer iterations at unit-level
    • Timing and wire length estimates are within 5% of Innovus place & route
    • Smaller area and lower power on datapath, up to 20%

    How it Works

    A new logic synthesis architecture was selected that uses a massively parallel approach, with multiple machines and CPUs, while being timing-driven. Your design is automatically partitioned into smaller instances, split up across multiple machines and CPUs, exploiting multi-threading, then balancing the load between machines and CPUs through adaptive scheduling.

    Results

    If you are an RTL Compiler user today and switch to Genus then expect run-time improvements between 3X to 5.5X, now that’s a huge gain. Capacity is impressive with Genus, so a design with 34M cell instances will run logic synthesis on 16 machines with 4 CPUs each in 2 days, something that you couldn’t do with RTL Compiler.

    The next tool run after logic synthesis is place and route, so following Genus you can run the Innovus place and route tool for an all-Cadence flow. These two Cadence tools share code for:

    • Parasitic extraction
    • Delay calculation
    • Global routing
    • User interface

    Related – Cadence’s New Implementation System Promises Better TAT and PPA

    Benefits of this unification are that you can expect 4X faster routing times compare to using the Encounter Digital Implementation System, and that the timing and wirelength calculations are within 5% meaning quicker timing closure. If you have the Synopsys ICC2 tool for place & route, then you can use Genus for logic synthesis as well.

    The two new Cadence tools Genus and Innovus will out-perform the previous generation tools RTL Compiler and Encounter Digital Implementation System. Here’s a table comparing timing and wirelength results between the old and new generation of tools:


    RCP – RTL Compiler, EDIS – Encounter Digital Implementation System

    Another part of the secret-sauce inside of Genus is how it does architecture-level PPA optimization by characterizing different architectures and then analytically solving for the best solution.

    Datapath designs will see improvements with Genus, and one customer design using a datapath inside of a video codec showed an area reduction of 16% while meeting the timing specs, while running 2.3X faster.

    Related – High Level Synthesis Gets Stronger

    Summary

    It’s quite natural for new technology to replace old as the design challenges increase, and in EDA this means that Cadence has a new generation of logic synthesis tool in Genus that raises the bar in our industry. Engineers at TI found that Genus produced results 5X faster, and Imagination Technologies used this new logic synthesis tool on their PowerVR GE7800 GPU.

    Users of RTL Compiler can try Genus without making any changes to existing scripts, so there’s no learning curve. If you’re looking at Genus and have no RTL Compiler experience, then expect a learning curve of just a few days.

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    Even More Integration and Automation for ARM-based Designs

    Even More Integration and Automation for ARM-based Designs
    by Daniel Payne on 06-03-2015 at 8:00 am
    Categories: Arm, EDA

    The attraction to an IP-based design methodology is that you can assemble an SoC from ready-made IP blocks, saving you valuable engineering development and verification time, while reducing risks from having to develop something from scratch and hoping that they meet industry standard specs. ARM is well known for supplying processor IP, interconnect IP and even debug IP, but how do you quickly connect all of that IP together correctly along with 3rd party IP? The clever engineers at ARM have just come to our rescue by announcing three configuration and integration tools:

    • CORESIGHT Creator
    • CORELINK Creator
    • Socrates DE

    Here’s the high-level view of where each of these three tools are used to enable you to quickly configure and integrate IP:

    As a methodology you would start with the Socrates DE tool and browse the IP catalog for the processor or subsystem you want, and configure that IP, creating an actual Bill of Materials (BOM) for your new system. Double-clicking on the CORELINK block takes you to a GUI called CORELINK Creator where you create a micro-architecture synthesis and even generate RTL code that includes testbenches. Your AMBA interconnect is now correctly constructed and ready to use as part of your RTL-based design and verification flow. CORESIGHT Creator will generate your debug and trace IP blocks.

    With these new levels of automation in Socrates DE you can expect to save months of effort versus manual integration because the configuration is correct-by-construction, lowering the amount of verification you would normally require.

    Related – New Suite of ARM IP for Mobile

    ARM has been using this more automated approach internally as they develop IP, and now ARM partners can start to enjoy the benefits as well. You will see ARM adding more IP to their catalog in Socrates DE with each new quarterly release cycle, and ARM partners will be adding their IP too. There are at least 50 system IP tooling partners now, giving you a lot of IP choices. Within the next few months you’ll find all of the ARM IP included in the IP catalog of Socrates DE.

    I was so pleased to learn that when ARM acquired Duolog last year along with the Socrates technology that it would be further developed to automate IP configuration and integration on ARM and 3rd party IP. The ARM systems and software group really is bringing it all together for the SoC community to benefit.

    Related – EDA Mergers and Acquisitions Wiki

    For those of you attend DAC next week in San Francisco, then visit them at booth 2414, or see all of the community partners at booth 2428.

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    Making Things Visible for 25 Years

    Making Things Visible for 25 Years
    by Paul McLellan on 06-03-2015 at 7:00 am
    Categories: Concept Engineering, EDA

    This year is most notably the 50th anniversary of Moore’s Law. It is also the 25th anniversary of Concept Engineering. They were founded in 1990 in Freiburg Germany. They started by providing automatic schematic generation from netlist. They sold primarily to other EDA companies and to internal development groups in semiconductor and system companies. As synthesis became the dominant methodology for digital design in the 1990s, it became necessary to visualize the output of synthesis. The challenge was to make a schematic from a netlist in a way that was understandable by the designer. Just randomly throwing the gates on the screen and hooking them up with wires wouldn’t work. Concept became the standard for doing this and pretty much every EDA company (except Synopsys which created their own viewer earlier) standardized on Concept’s viewer. When I was VP engineering at Ambit in the late 1990s, we used it too. I was by no means alone, they have over 40 OEM customers in the EDA and semiconductor markets (including FPGA).

    With the growth of IP-based design in the 2000s to today, the need to take netlists of various kinds and visualize them became even more important. IP from 3rd parties and even from other groups inside the same company needed to be understood by the designers building the SoCs, so that they could use the IP correctly and, often, remove functionality from the IP that was not required on that design. So Concept started to sell tools for visualizing netlists, RTL, transistor netlists and system. Over 250 chip design companies have licensed Concept’s VISION line of customizable products to debug digital, analog and mixed-signal designs.

    As the company’s tag-line says “We make things visible.”

    It is impossible to argue with Gerhard Angst, Concept’s CEO, when he says:
    A quarter of a century is a significant milestone for any technology company. We could not have reached this milestone without the continued support and trust of our customers, and the passion and commitment of our staff.


    But they are not just blowing out candles on their birthday cake, they have a complete new release, version 6, of their product line. This will be on show next week at the DAC on booths 2208 and 2210. You can see the latest releases of StarVision PRO, RTLvision PRO, GateVision PRO and SpiceVision PRO.

    What’s new in version 6? Some notable enhancements are:

    • Improved netlist pruning: In addition to Verilog and SPICE netlist export and pruning, StarVision PRO now also allows netlist pruning for the most common post-layout formats, DSPF and SPEF.
    • Advanced post-layout debugging: Improved visualization and debugging of parasitic networks.
    • API improvements: Improvements in the database API and GUI API allow even more sophisticated code to be developed and executed by the tool.
    • Advanced batch processing: Enhanced batch processing capabilities allow more efficient processing of user-defined analysis and debugging tasks.
    • Unified File Open Dialog: Makes it easier to load complex mixed-language SoC designs and libraries.
    • Improved visual debugging capabilities such as: Smart connectivity lens view, improved schematic navigation history, and on-the-fly hierarchy exploration with built-in fold and un-fold controls.

    As an example of how other EDA companies use Concept’s technology as a foundation, earlier this week Aldec and Concept Engineering announced that Aldec’s ALINT-PRO-CDC clock-domain crossing verification tool is using Concept’s Nlview schematic visualization engine. This allows the tool to combine Aldec’s advanced analysis with Concept’s easy-to-read schematic diagrams to create an advanced debugging cockpit for tracking down and fixing clock-domain crossing problems.

    The press releases are:

    • 25th anniversary here
    • Version 6 of the product line here
    • Aldec’s clock domain crossing solution here
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    A Robust Lint Methodology Ensures Faster Design Closure

    A Robust Lint Methodology Ensures Faster Design Closure
    by Pawan Fangaria on 06-03-2015 at 4:00 am
    Categories: EDA

    With the increase in SoC designs’ sizes and complexities, the verification continuum has grown larger to an extent that the strategies for design convergence need to be applied from the very beginning of the design flow. Often designers are stuck with never ending iterations between RTL, gate and transistor levels at different stages of designs. In this light, full-chip analysis and verification completion for a large SoC may look like a distant dream. A significant number of iterations can be reduced by identifying and fixing bugs at the source, i.e. RTL.

    One of the most effective ways to fix issues in the RTL is by running lint checks on the RTL code. But imagine the RTL code for a design with several hundred millions of gates; not only can the tool’s capacity and performance become prohibitive, but a huge number of violations can also become a problem to manage. So, what are the alternatives? Well, if we could use the link checks in a smarter way to cover the complete design in a reasonable time and effort, it could be a great alternative to make the design robust at RTL, for better convergence throughout the downstream design flow.

    For complete analysis coverage, a flat design investigation is required which necessitates longer runtime and higher memory consumption. Also, block level waivers are required to defer violations for verified sub-blocks when run at the top level without sufficient or consistent constraints. It could be difficult and time consuming to resolve inconsistencies between the block and chip level lint rules.

    A flat design analysis can also be carried out with IP or bocks used as black boxes, thus focusing only on chip level modules and glue logic. This approach can improve analysis runtime and reduce memory consumption and violation management. However, a major drawback in this approach is reduced analysis coverage and poor QoR. In this approach inter-block issues and several other issues such as improper use of clock and set/reset signals generated by an IP module remain undetected and uncovered.

    Atrentahas come up with a novel approach that can provide the complete analysis coverage for an SoC with shorter runtime and lower memory consumption, and without the need of any waiver at the block level. They use smart or “Abstract Models” for IP blocks, a concept pioneered by Atrenta for full-chip analysis. How does the methodology with abstract models work? Let’s see an example –


    In the above pictures there are abstract model views with a couple of typical input and output ports. An abstract model contains important information about the block’s interfaces such as its port types, their directions and the connected signals with them. This information is utilized in inter-block lint checks such as combinational loop fanning across multiple blocks, un-driven input terminal and so on. The abstract model also allows constant propagation that helps in detecting structural issues. The comprehensiveness of interface level information in the abstract models ensures the completeness of analysis coverage at the SoC level.

    The “Abstract Model” based SoC lint analysis is done hierarchically in two steps –

    In the first step, the block level constraints and assumptions are verified within the context of the SoC. This step ensures that the abstract models are in sync with the SoC analysis environment and requirements. Any inconsistencies and mismatches between block and chip level analysis are identified at this stage. In the second step, the final SoC analysis is done by using these verified abstract views for lower level blocks or IPs. No waiver is required at the SoC level. Since the lower level blocks are fully verified, the violations occur only at the chip level and can be easily managed.

    Atrenta’s customers have verified many SoCs with this approach. The larger SoCs of the order of 200 to 350 million gates show an improvement of ~10x in runtime and reduction of ~5x in memory consumption with this hierarchical approach compared to the flat analysis approach. The hierarchical approach also shows better inter-block coverage compared to the IP black-box approach. At the same time, the violations are meaningful and easily manageable.

    By using this lint methodology effectively at the RTL level, designers can quickly identify and remove potential issues related to design initialization, bus integrity, unreachable or unknown states, underflow or overflow of FIFOs, and so on to signoff the RTL for synthesis and implementation. The lint-clean RTL makes way for faster convergence of the SoC through downstream implementation and verification flow.

    Atrenta is unveiling this new lint methodology for SoC signoff at the 52[SUP]nd[/SUP] DAC. Visit their booth #1732 to learn more.

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com

    Posted on

    Why is Intel going inside Altera for Servers?

    Why is Intel going inside Altera for Servers?
    by Eric Esteve on 06-02-2015 at 12:30 pm
    Categories: Foundries, FPGA, Intel Foundry

    You should be happy to listen that Intel will buy Altera FPGA challenger, if you expect always more power to be consumed in datacenter! In 2013 the power consumption linked with the Servers and Storage IC activity, plus the electricity consumed in the systems cooling these high performance chips has reached 91 BILLION KWh (or the equivalent of 34 500MW power plant, or $9.1 Billion electricity bill). Could we see stabilization or even decrease of this power consumption in the near future, due to Moore’s law or whatever else? No way! At first because the amount of data exchanged (and stored) in the cloud is growing by 60% per year. This is the natural evolution linked with the smartphone explosion and with our common behavior evolution: we want to capture image and sound (store it), share it by sending it through the cloud, see TV, series or movies when moving, and so on.

    Why linking the Intel/Altera deal with power consumption increases in the datacenters? As a matter of fact, Intel has a lion’s share in datacenter servers, based on x86 architecture. We know that this CISC architecture has been initially designed for performance, at a time (1990’s) where the need for compute power in PC and servers was crucial. In the datacenter, the needs for ever higher compute power is asserted along with the need for certain level of flexibility in order to quickly adapt an installed system to protocol evolution or new features. On top of this need for lack flexibility it has been shown that x86 architecture is not well tailored to run search engine algorithms. In the x86 case, the only option is to write software. Designers have tried to improve efficiency by using GPU –better than x86, but not optimum. A team with Microsoft have used FPGA instead, and reported 95% improvement compared with x86. Not surprising as FPGA design offer a much better flexibility than x86.

    Which was surprising was the way Wall Street has reacted to this news. Some people who clearly didn’t understood anything to high tech, in particular to the difference between software design, FPGA development and ASIC technology, thought that FPGA was the panacea for search engine algorithm development in datacenters. Not only they thought it, but they wrote it (search for: “What Intel’s Buyout Of Altera Means For The FPGA Industry”, a superb example of writing about a topic that the author absolutely don’t understand). And Wall Street has decided that Intel should buy Altera to create a synergy, shipping $2,000 FPGA consuming 50 to 100W along with their $500 server chips!

    The problem is simple: the same algorithm running on a $2,000 FPGA (consuming several dozens of Watts) will run, probably faster, on a $20 ASIC consuming 5 to 10 Watt! I agree that Intel will be happier to sold $2,000 part than $20 ASIC, but is it enough to build a strategy? By the way, if you don’t trust me, just think to the secure networking chips designed by Broadcom (Netlogic), able to screen networking frames on the fly and detect viruses, the virus database being updated daily (thanks to Flash Memory).
    So, is Intel buying Altera a good deal? Altera is part of the top 20 semi vendors, selling certain new products with 80% GPM, enjoying a strong customer base in Networking, Industrial, Automotive, Consumer and more, so Intel will most probably get benefit from this investment (when the interest rate is close to zero, almost any acquisition is most valuable than leaving the money at bank!). Should Intel/Altera develop synergic solution for datacenter? Not only I don’t think so,… but I hope not, at least for the planet!

    From Eric Esteve from IPNEST