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A Comprehensive Power Optimization Solution

A Comprehensive Power Optimization Solution
by Pawan Fangaria on 04-20-2015 at 7:00 am
Categories: EDA

In an electronic world driven by smaller devices packed with larger functions, power becomes a critical factor to manage. With power consumption leading to heat dissipation issues, reliability of the device can be affected, if not controlled or the device not cooled. Moreover, for mobile devices such as smartphones or tablets that run on battery, low power consumption is essential. For a holistic solution to the power problem, it is important that this is addressed at the source, i.e. the design stage. For SoCs with robust power optimized designs, comprehensive EDA tools are needed that can accurately measure and estimate power requirements, reduce power by utilizing various techniques, and verify the power at every stage of the design starting from RTL to the physical netlist. The RTL stage coming early enough in the design process and being detailed enough; it is the sweet spot that provides the largest avenue for power reduction and optimization.

Atrenta’sSpyGlass Powerprovides a complete solution for power optimization that analyzes and reduces power, verifies the original RTL against the new modified RTL, and ensures the design is compliant with the power intent, post-synthesis and post-layout. The power reduction is done by utilizing several approaches including power exploration at the SoC architecture level, manually fixing critical blocks with tool guidance, and automatic power optimization of non-critical blocks.


Figure 1: Power optimization flow

The SpyGlass Power optimization flow works interactively between power estimation, reduction and verification. The power estimation can be done with user specified inputs without vectors, or with simulation/emulation data in VCD, FSDB, or SAIF files. Different modes can be used such as average, cycle-based, or hybrid, depending on the requirement; for example, in cases of memories, cycle-accurate monitors are applied by default, even in average mode. For predictable accuracy, calibration is done against a reference netlist, and a correlation toolbox is used for models of capacitance, clock tree, and so on. The beauty of the SpyGlass Power solution is that with physical-aware power estimation, it can even skip the calibration and correlation step, while still producing the same level of accuracy by leveraging timing and physical optimization engines. This is a solution that will be introduced soon in SpyGlass Power, providing enhanced local fidelity and allowing trade-off analysis between different physical prototypes.

Along with power estimation, SpyGlass Power also performs power profiling and provides power efficiency metrics that include information such as ‘Clock Gating Ratio’, ‘Intrinsic Clock Gating Efficiency’, ‘Incremental Clock Gating Efficiency’, and ‘Register Output Activity Density’. Designers can analyze this data and make informed decisions to either accept particular clock gating and register structure, or modify them manually to increase power efficiency.


Figure 2: Power Explorer

Within the tool, there is a versatile Power Explorer,which is a rich GUI that works as a central cockpit for top-down power methodology and efficient power reporting, analysis, and suggested next steps for improvement. The master view with hierarchical instances contains information about design objects such as registers, combinational logic, power profile numbers, annotations, and so on. The report can be easily customized as required and presented in different matrix forms. Similarly the slave or secondary views contain information about registers, memories, clocks, micro-architectures, and opportunities for power saving.

SpyGlass Power uses formal sequential analysis techniques to identify ‘Enables’ beyond synthesis tools for sequential power reduction. While introducing registers for Enables, it leverages SpyGlass CDC to keep the design CDC-safe. Similarly memory power reduction is achieved by using techniques such as ‘redundant access removal’ and automatic activation of ‘light sleep mode’.


Figure 3: Activity Trigger Detection

There is a very effective and useful technique called ‘Activity Trigger Detection’ that is used to identify events that can up-surge or down-surge activities and turn parts of the design ON or OFF. The signals that are root causes of such changes are identified with a combination of statistical, structural, and formal approaches, and the events can be combined to gate a particular block or even power-gate it.


Figure 4: Examples of Power Guidance rules

SpyGlass Power provides power guidance for micro-architectural improvements such as ‘FIFO optimization’, ‘counter gating’, ‘glitch detection and removal’, and so on. It works with or without vectors. ‘Power lint’ can be used to improve RTL without vectors. With vectors, the power guidance also provides information about specific modifications with their expected power gains.

As part of power verification, SpyGlass Power has an independent Signoff Verification Solution that supports UPF 2.0/2.1 with a single tool for RTL, post-synthesis netlist, and post-layout netlist verification. The power intent browser cleanly represents power at every block or IP level without design clutter and with cross-probing features. The non-instrumented RTL is verified with power intent “lint” checks and power intent consistency checks. On instrumented RTL or netlist designs where low power elements such as isolation cells or level shifters are inserted, the checks also flag if the implementation is improper. The signoff power verification on post-synthesis netlist ensures correct implementation of power elements, while on post-layout netlist the tool also ensures all supply connections are correct via ERC (Electrical Rule Checks).

SpyGlass Power also has a powerful debug environment with several features such as power annotation on schematics, click on port to see isolation, retention or level-shifting strategy, and cross-links between violation messages, power intent browser, schematics, design files, etc. Additionally, some functional checks can be done through formal power verification based on design functionality and power intent.

SpyGlass Power has seamless integration of all these technologies within the SpyGlass platform and provides a powerful comprehensive solution for power estimation, analysis, optimization and verification. This solution for power optimization and verification has been adopted by many leading semiconductor companies.

A very detailed description with several examples about SpyGlass Power solutionwas presented in a webinarby Guillaume Boillet, Sr. Technical Marketing Manager at Atrenta. The webinar can be attended on-line after a one-step free registration on the Atrenta website here.

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Networking at 52nd DAC in SFO

Networking at 52nd DAC in SFO
by Daniel Payne on 04-19-2015 at 7:00 pm
Categories: EDA, General

Yes, the 52nd DAC(Design Automation Conference) is a technical conference plus exhibition with wonderful keynote speakers and agenda, however there is a certain serendipity that occurs by just meeting people, face to face at the many networking opportunities. The best way to kick off your DAC experience is by attending the Sunday night event called the Welcome Reception, it’s held at the Intercontinental Hotel in the Grand Ballroom BC from 5:30PM to 7:00PM. You are likely to see most of the bloggers from SemiWiki present, along with Wally Rhines, the CEO from Mentor Graphics and Tom Quan, Director of TSMC. Not only seeing people like this from our industry, but actually approach them, introduce yourself, start a conversation and even exchange business cards.

I’ve always found this Welcome Reception to be an energizing start for the next 72 hours of non-stop meetings, discussions and blogging about all things EDA, semiconductor and IP. It’s a time to reconnect with former co-workers, get introduced to new people, ask about industry trends, see how their business is going, find out about what is new, and share any rumors that spread throughout DAC like lightning.


Intercontinental Hotel, nearby Moscone Center

Immediately following the Welcome Reception there is typically a Gary Smith presentation, held in a nearby room of the same hotel. Gary is an analyst that covers the EDA space, and he also sells research reports over at Gary Smith EDA. You cannot miss Gary, because he will be wearing his trademark white sport coat.

Related – Gary Smith at DAC

Each evening throughout the week you’ll have more opportunities for networking at DAC like:

  • Monday, 6PM to 7PM on the exhibit floor, Cocktails & Conversations Reception
  • Tuesday, 4:30PM to 6PM at the Designer and IP Track Poster Session on the exhibit floor
  • Tuesday, 6PM to 7PM on the exhibit floor, Cocktails & Conversations Reception
  • Wednesday, 6PM to 7PM on the Esplanade Foyer, Reception
  • Thursday, 5:30PM to 6:30PM on the Esplanade Foyer, Reception

As a blogger I typically get invited to a dinner by Mentor on Monday night and Synopsys on Tuesday night. If you love loud music then plan on attending the Denali/Cadence party on Tuesday night, but make sure that you sign up first then pick up your ticket at the Cadence booth #3515.

Enjoy your experience at DAC this year by attending the technical conference, exhibits, keynote presentations and most of all get connected with some more people by networking this year.

Related blogs about DAC:

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Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design

Rockchip Bets on Arteris FlexNoC Interconnect IP to Leapfrog SoC Design
by Majeed Ahmad on 04-19-2015 at 9:00 am
Categories: Arteris, EDA, Mobile

China was a virgin territory for Arteris Inc. before July 19, 2012 when Fuzhou Rockchip Electronics announced that it has licensed the Arteris FlexNoC network-on-chip (NoC)-based interconnect IP technology for its multicore SoCs for budget Android tablets. Rockchip mostly targets the tablet and set-top box (STB) markets in China and Taiwan with high-end processors at a lower price point.

Rockchip, one of the largest chipmakers in China, quickly set the precedent for efficient SoC development and soon a number of chipmakers in China followed suit by licensing Arteris’ FlexNoC interconnect IP technology. The chipmakers in China that have now licensed Arteris’ interconnect IP for SoC development include high-flyers such as HiSilicon, Spreadtrum, Leadcore, RDA Microelectronics, Allwinner and Nufront.

Earlier this month, the Fuzhou, China-based Rockchip renewed ties with Arteris by licensing the FlexNoC fabric IP for its RK Series of SoC devices. The FlexNoC interconnect fabric will serve as the backbone communications IP for Rockchip applications processors. Arteris’ FlexNoC IP will provide the interconnect glue between graphics processing units (GPUs), on-chip peripherals and other subsystems of the SoC device.


Rockchip’s RK3288 is known to have cost US$40 per chip

The on-chip quality-of-service features of FlexNoC guarantees high bandwidth availability for initiators such as GPU and low latency for communications such as the CPU-to-memory. One of the key advantages of FlexNoC interconnect IP in large SoC development is the minimization of routing congestion, which in turn, reduces timing convergence issues and accelerates time-to-market. It’s important to note that Rockchip, in its early going, used to develop one SoC device in a year. Now, since adopting Arteris NoC IP, Rockchip managers boast doing as many as six SoC designs in a year.

In 2012, Rockchip’s IC Design Manager Li Shiqin acknowledged that his company chose Arteris’ FlexNoC technology instead of older interconnect technologies like buses and crossbars because it allowed Rockchip to simultaneously meet design frequency, power, memory efficiency and QoS requirements. Fast forward to April 2015, Li is now IC Design Director at Rockchip and says that FlexNoC interconnect technology brings Rockchip SoCs both differentiation and time-to-market benefits. “Our extensive use of Arteris FlexNoC interconnect IP has enabled us to increase the number of complex SoC designs we can implement in a year with the same amount of resources.”

Beyond faster turnaround time, IP products like the Arteris FlexNoC fabric come with another substantial benefit for China’s SoC houses like Rockchip. China’s large SoC makers like Rockchip are mostly using CPU cores from ARM and graphics cores from either ARM or Imagination Technologies. So being able to choose from the best of the cutting-edge IP products provides them with an effective venue for differentiating their SoCs from competitor products.


Rockchip was first in China to embrace Arteris interconnect IP for SoC design

Take Rockchip’s RK3288 processor, for instance, which Acooo has used in its OneBoard PRO+ with a backlit mechanical keyboard housed in an aluminum case. The keyboard—designed to be used both as an Android system and a normal keyboard for your PC or Mac—comes with a power adapter and cable, a PC-line connect cable with DVI connector on one side and HDMI plus USB on the other side, an HDMI cable, and a DIY accessory tool box. The RK3288 SoC uses quad ARM Cortex-A17 processors and a powerful ARM Mali-T764 GPU. It is known to have cost around $40 per chip.

Rockchip’s RK3288 application processor has also powered two sub-$150 Chromebooks from Haier and Hisense and a Chrome stick from Asus called Chromebit that implements a set-top Chrome computer in an HDMI dongle. These design wins have established the RK3288 SoC as one of the fastest ARM processors in tablet and notebook computers.


Rockchip’s RK3288 is powering the Asus Chromebit dongle

In retrospect, China’s SoC underdogs came to adopt the network-on-chip technology for digitally packetizing information between IP blocks within an SoC die just a couple of years after silicon behemoths like Qualcomm, Samsung and TI. So according to the sequential steps for new technology adoption, as explained in Geoffrey Moore’s “Crossing the Chasm” business bestseller, the companies like Rockchip could be considered early adopters of the crucial network-on-chip technology in SoC designs.

That helps to understand the transformation of China chipmakers from SoC design wannabe’s to mainstream silicon players. The fabless chip firms in China have been working relentlessly for over a decade to earn an identity. However, after they began to bet aggressively on new IP products like the FlexNoC interconnect fabric, they started to win design breakthroughs they have been longing for since the early 2000s.


RK3288 board

Take Rockchip’s SoC journey as testament to how vital investing in semiconductor IP can be for a chipmaker’s technology evolution. The chipmaker from Fuzhou, who first licensed Arteris FlexNoC interconnect IP in summer 2012, had been largely known as a budget SoC supplier for tablets. Last year, it signed a strategic deal with Intel that will allow it access to x86 CPU core IP as well as to Intel’s 3G baseband technology that the world’s largest silicon vendor had acquired after buying Infineon’s wireless unit.

In other words, Rockchip is going to make a leap from the tablet to the smartphone SoC market. That premise also became evident when ARM announced its next-generation Cortex-A72 processor core for smartphones in February this year. Rockchip was among the three licensees that ARM disclosed at the time of announcement of its 64-bit CPU core platform.

According to DigiTimes, Rockchip has showcased smartphones and tablets using Intel processors at the Hong Kong Electronics Fair that was held on April 13 through 16, 2015. Rockchip seems set for exciting times as its bets in licensing world-class IP clearly distinguish it in its quest to develop world-class SoC devices.

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Moore’s Law is dead, long live Moore’s Law – part 3

Moore’s Law is dead, long live Moore’s Law – part 3
by Scotten Jones on 04-19-2015 at 4:00 am
Categories: TechInsights

In the second installment of this series we reviewed the cost drivers that have enabled the semiconductor industry to continue to cost reduce the cost per transistor year after year. In the next three installments we will discuss the product specific issues beginning with this installment discussing DRAM.
Continue reading “Moore’s Law is dead, long live Moore’s Law – part 3”

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Moore’s Law is dead, long live Moore’s Law – part 2

Moore’s Law is dead, long live Moore’s Law – part 2
by Scotten Jones on 04-19-2015 at 12:00 am
Categories: Foundries, TechInsights

In the first installment of this series on Moore’s law we examined what Moore’s law is and presented some data on how it has affected the industry. In this installment we will discuss the manufacturing cost reduction strategies that have made Moore’s law possible.

Manufacturing Cost Drivers
The manufacturing cost of a semiconductor is made up of wafer fabrication, wafer sort, packaging and class test.

Packaging has seen a move from expensive ceramic packages to plastic packages, packaging has moved offshore to low labor cost locations, new smaller and lower cost packages have been introduced such as QFNs and recently gold wire bonding wore has been replaced with copper wire bonds.

For wafer sort and class test, probably the biggest cost reduction has been the move to parallel test where up to hundreds of parts are now tested at the same time.

The single biggest drive of semiconductor cost reductions has been the cost of wafer fabrication where four major factors have driven down cost.

Wafer fabrication cost

Wafer size
The first big driver of wafer fabrication cost reductions has been wafer size transitions. In 1960 wafer sizes were split between 0.75 and 1.0 inch diameter wafers with 0.75” ramping down and 1.0” ramping up. Over the subsequent decades wafer sizes have transitioned all the way to 300mm (~12”) with 450mm (~18” in development). Table 1. Illustrates wafer size transitions.

[TABLE] align=”center” border=”1″
|-
| style=”width: 109px” | Wafer size
| style=”width: 126px” | Year introduced to production
| style=”width: 114px” | Wafer area (cm2)
| style=”width: 101px” | Wafer area increase
| style=”width: 101px” | Years since last new wafer size.
|-
| style=”width: 109px” | 1.5”
| style=”width: 126px” | 1963
| style=”width: 114px” | 11.4
| style=”width: 101px” | 1.44
| style=”width: 101px” | NA
|-
| style=”width: 109px” | 2.0”
| style=”width: 126px” | 1966
| style=”width: 114px” | 20.3
| style=”width: 101px” | 1.78
| style=”width: 101px” | 3
|-
| style=”width: 109px” | 3.0”
| style=”width: 126px” | 1970
| style=”width: 114px” | 45.6
| style=”width: 101px” | 2.25
| style=”width: 101px” | 4
|-
| style=”width: 109px” | 100mm
| style=”width: 126px” | 1974
| style=”width: 114px” | 78.5
| style=”width: 101px” | 1.72
| style=”width: 101px” | 4
|-
| style=”width: 109px” | 125mm
| style=”width: 126px” | 1981
| style=”width: 114px” | 123
| style=”width: 101px” | 1.56
| style=”width: 101px” | 7
|-
| style=”width: 109px” | 150mm
| style=”width: 126px” | 1984
| style=”width: 114px” | 177
| style=”width: 101px” | 1.44
| style=”width: 101px” | 3
|-
| style=”width: 109px” | 200mm
| style=”width: 126px” | 1988
| style=”width: 114px” | 314
| style=”width: 101px” | 1.78
| style=”width: 101px” | 4
|-
| style=”width: 109px” | 300mm
| style=”width: 126px” | 1998
| style=”width: 114px” | 707
| style=”width: 101px” | 2.25
| style=”width: 101px” | 10
|-
| style=”width: 109px” | 450mm
| style=”width: 126px” | 2022
| style=”width: 114px” | 1,590
| style=”width: 101px” | 2.25
| style=”width: 101px” | 24
|-

Table 1. Wafer size transitions.

Wafer size transitions require new larger more expensive equipment increasing depreciation, facility and maintenance costs. Consumable usage increases and wafers get more expensive. Indirect labor per wafer typically stays relatively flat and direct labor per wafer has actually gone down due to increasing automation. The net result is that the cost per unit area of processed wafer typically goes down, for example table 2 presents a comparison of 300mm costs versus 200mm costs for an identical logic process.

[TABLE] align=”center” border=”1″
|-
| style=”width: 139px” | Wafer size
| style=”width: 192px” | $/wafer
| style=”width: 150px” | $/cm2
|-
| style=”width: 139px” | 200mm
| style=”width: 192px” | $1,203.17
| style=”width: 150px” | $3.83
|-
| style=”width: 139px” | 300mm
| style=”width: 192px” | $1,936.11
| style=”width: 150px” | $2.74
|-

Table 2. 300mm versus 200mm logic process cost comparison. Source, IC Knowledge.

The key assumptions are:

  • Material: $/cm[SUP]2[/SUP] the same for both sizes (currently approximately true although not at the introduction of a new wafer size).
  • Direct Labor (DL) and Indirect Labor (IDL) productivity equal (300mm is actually better for DL).
  • Equipment cost: 1.25x (assumes no technology improvements).
  • Throughput: 0.52 expose, 0.62 implant and metrology, 1.0x others. Assumes no throughput enhancements that would increase the equipment price.
  • Footprint: actual change.
  • Maintenance factor: same for both.
  • Consumables and utilities: 2.25x (actually has generally been less than this).

The net result is a 28% reduction in cost per unit area. The problem is that as we can see from table 1. the time between wafer size transitions has lengthened dramatically from 3 to 4 years in the past to 10 years for 200mm to 300mm and over 20 years to get from 300mm to 450mm. the net result is that wafer size transitions are no longer a significant contributor to yearly reductions in wafer cost.

Yield
In the early days of the semiconductor industry yields were low and improved slowly. In recent years mature yields are typically in the ninety percentage plus range and the time to achieve mature yields has compressed to around six months. There are of course exceptions; there were reports of yield problems for TSMC at 130nm. At 28nm yield struggles at most foundries gave TSMC a clear early lead and Intel has had well publicized yield issues at 14nm.

The bottom line is that modern yields are so high and time to yield is so fast that further improvement in costs due to faster yield improvement aren’t really possible and yield improvement is no longer a driver of year to year cost improvement.

OEE
In 1995 Sematech introduce OEE to the industry. OEE is basically the percentage of the capacity of a tool that is actually achieved. OEE which stands for Overall Equipment Effectiveness accounts for down time both scheduled and unscheduled, idle time due to no work or no operator, yield loss, speed (tool running slower than normal), set up, qualification lots and engineering wafers. It is basically how many good sellable wafers a tool produces per hour divided by the tool capacity in wafers per hour.

When Sematech went out and surveyed the industry in 1995 they found the industry wide OEE was only averaging 30%. A major program to improve OEE was then undertaken and by 2003 a new Sematech study found OEE had improved to 40%.

Generally speaking OEE follows these principles:

  • OEE is better for newer equipment designed to produce smaller linewidths because of the work the equipment manufacturers continue to put into improving equipment performance.
  • OEE is lower for high mix fabs due set up time for change overs and qualification runs and higher for low mix fabs.
  • OEE is better for larger fabs due to the ability to better match equipment capacity.

In general from lower to higher OEE we can rank fabs as follow: high mix logic fabs (foundry), low mix logic, single process large DRAM fabs, single process massive NAND fabs.

OEE today ranges from around 50% to over 70%. It should be noted here that due to cycle time reasons it is not desirable to drive OEE to 100% and some of the largest NAND fabs are approaching the “optimal OEE”. OEE is therefore becoming less of a year to year cost reduction driver.

Linewidth shrinks
The largest and most consistent driver of cost reductions has been linewidth shrinks. Linewidth shrinks have historically increased wafer cost but provided a larger increase in transistors per unit area and therefore reduced cost per transistor.

In 1974 Dennard, et.al. of IBM disclosed the concept of MOSFET scaling. Basically you take an existing linewidth, for example 250nm and you multiply it by a scaling factor resulting in a linewidth of 180nm. By shrinking from 250nm to 180nm you increase the transistors per unit area and the transistor performance simultaneously as long as you scale everything correctly. Table 3 summarizes constant electric field scaling from 250nm to 180nm.

[TABLE] align=”center” border=”1″
|-
| rowspan=”2″ style=”width: 162px” | Parameter
| rowspan=”2″ style=”width: 60px” | Scaling factor
| colspan=”3″ style=”width: 342px” | Devices
|-
| style=”width: 108px” | Before
| style=”width: 114px” | Calculation
| style=”width: 120px” | After
|-
| style=”width: 162px” | Gate length (Lg)
| style=”width: 60px” | 1/k
| style=”width: 108px” | 250nm
| style=”width: 114px” | 250/1.4
| style=”width: 120px” | 180nm
|-
| style=”width: 162px” | Operating voltage
| style=”width: 60px” | 1/k
| style=”width: 108px” | 1.8 volts
| style=”width: 114px” | 1.8/1.4
| style=”width: 120px” | 1.3 volts
|-
| style=”width: 162px” | Packaging density
| style=”width: 60px” | K[SUP]2[/SUP]
| style=”width: 108px” | 1x
| style=”width: 114px” | 1.4[SUP]2[/SUP]
| style=”width: 120px” | 2x
|-
| style=”width: 162px” | Power consumption
| style=”width: 60px” | 1/k[SUP]2[/SUP]
| style=”width: 108px” | 1x
| style=”width: 114px” | 1/1.4[SUP]2[/SUP]
| style=”width: 120px” | 0.5x
|-
| style=”width: 162px” | DC power density
| style=”width: 60px” | 1
| style=”width: 108px” | 1
| style=”width: 114px” | NA
| style=”width: 120px” | 1
|-
| style=”width: 162px” | Circuit delay
| style=”width: 60px” | 1/k
| style=”width: 108px” | 1
| style=”width: 114px” | 1/1.4
| style=”width: 120px” | 0.7
|-
| style=”width: 162px” | Power delay product
| style=”width: 60px” | 1/k[SUP]3[/SUP]
| style=”width: 108px” | 1
| style=”width: 114px” | 1/1.4[SUP]3[/SUP]
| style=”width: 120px” | 0.4
|-
| style=”width: 162px” | Functional throughput
| style=”width: 60px” | K[SUP]3[/SUP]
| style=”width: 108px” | 1
| style=”width: 114px” | 1.4[SUP]3[/SUP]
| style=”width: 120px” | 2.7
|-

Table 3. Constant electric field scaling.

From table 3. we can see that packing density (transistors per unit area increased by 2x, power consumption was cut in half, circuit delay was decreased by 30% and functional throughput went up by 2.7x.

In order to accomplish constant electric field scaling gate oxide thickness also has to scale to maintain good electrostatic control over the gate. Unfortunately at the 90nm logic node gate oxides became so thin that further reductions in thickness resulted in too much leakage. This will be discussed further in the section on logic devices but basically mobility enhancement through strain was used until high-k gate oxide was introduced.

Figure 1. illustrates the linewidths for the market leaders in four main segments. Plotted on figure 1 are Intel MPU and TSMC SOC minimum metal pitches, Samsung DRAM bit line pitch and Samsung NAND polysilicon pitch.

Figure 1. Linewidth trends for Samsung DRAM, TSMC SOC, Intel MPU and Samsung NAND. Source, IC Knowledge.

As you can see from figure 1. all four segments have continued to scale down linewidths. The problem is that as pitch drops below approximately 80 nanometers single patterning with immersion scanners can no longer print the required patterns and multipatterning is required.

Multipatterning
There are two main approaches to multipatterning:

Litho-etch splits patterns up into multiple masks where a mask is applied and etched into the wafer and then additional masks and etches are performed. Table 4. Summarizes various litho-etch techniques.

[TABLE] align=”center” border=”1″
|-
| style=”width: 127px” | Technique
| style=”width: 127px” | Abbreviation
| style=”width: 127px” | Pitch
| style=”width: 127px” | Masks
|-
| style=”width: 127px” | Litho-etch – Litho-etch
| style=”width: 127px” | LE2
| style=”width: 127px” | ~60nm
| style=”width: 127px” | 2
|-
| style=”width: 127px” | Litho-etch – Litho-etch – Litho-etch
| style=”width: 127px” | LE3
| style=”width: 127px” | ~50nm
| style=”width: 127px” | 3
|-
| style=”width: 127px” | Litho-etch – Litho-etch – Litho-etch – Litho-etch
| style=”width: 127px” | LE4
| style=”width: 127px” | ~40nm
| style=”width: 127px” | 4
|-

Table 4. Litho-etch multipatterning options. Source, IC Knowledge Strategic Cost Model.

The second technique is Self-Aligned Multipatterning. The self-aligned techniques can double, quadruple or octuple the pitch but they create ovals around a mandrel and require cut masks to create lines. Depending on the required pitch, large number of cut masks may be required. Self-aligned multipatterning is also primarily useful for line-space pairs and not as useful for 2D patterns. Table 5. Summarizes self-aligned multipatterning.

[TABLE] align=”center” border=”1″
|-
| style=”width: 127px” | Technique
| style=”width: 127px” | Abbreviation
| style=”width: 127px” | Pitch
| style=”width: 127px” | Masks
|-
| style=”width: 127px” | Self-Aligned Double Patterning
| style=”width: 127px” | SADP
| style=”width: 127px” | 40nm
| style=”width: 127px” | 3 for 40nm
|-
| style=”width: 127px” | Self-Aligned Quadruple Patterning
| style=”width: 127px” | SAQP
| style=”width: 127px” | 20nm
| style=”width: 127px” | 6 for 20nm
|-
| style=”width: 127px” | Self-Aligned Octuple Patterning
| style=”width: 127px” | SAOP
| style=”width: 127px” | 10nm
| style=”width: 127px” | 10 for 10nm
|-

Table 5. Self-aligned multipatterning options. Source, IC Knowledge Strategic Cost Model.

As we can see from tables 4 and 5 multipattering enables much smaller pitches than the 80nm single exposure limit but at the cost of more masks and other additional patterning. There are also edge placement concerns issues that may limit the ability to achieve some of the smallest pitches.

The bottom line of all this is that as we move further into the era of multipatterning cost per wafer is going up faster than it has historically increased slowing the rate of cost reduction. As we will see in the next three installments there are also structural issues that will ultimately stop our ability to continue to scale at all.

In the next three installments we will examine the specific issues and status of DRAM, Logic and NAND.

Also read:
Moore’s Law is dead, long live Moore’s Law – part 1
Moore’s Law is dead, long live Moore’s Law – part 3
Moore’s Law is dead, long live Moore’s Law – part 4
Moore’s Law is dead, long live Moore’s Law – part 5

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Silvaco: TCAD to Signoff in Vertical Markets

Silvaco: TCAD to Signoff in Vertical Markets
by admin on 04-18-2015 at 8:00 pm
Categories: EDA

Recently, I talked about meeting with Dave Dutton the CEO of Silvaco. Mainly we were talking about the recent acquisition of Invarian but he also brought me up to date on Silvaco and how he is bringing their disparate product lines into a more focused strategy.

See also Silvaco Swallows Invarian

Silvaco would be the first to admit that they have not done a great job of marketing themselves and their product lines. In fact people are often surprised how significant they are:

  • 30 years old, no debt, no VCs, funded entirely by cash flow
  • >400 customers worldwide
  • around 200 employees with a global footprint
  • development centers in Santa Clara CA, Cambridge UK, Hsinchu TW and Yokohama JP
  • only providrer delivering a complete TCAD, 3D RC extraction, SPICE modeling, SPICE simulation, custom IC design and verification flow
  • #1 supplier for flat-panel display (FPD) with almost all manufacturers, both TFT and OLED
  • #1 supplier of solutions for radiation and soft-error reliability
  • #2 TCAD supplier overall, with customers for for power, optical, radiation/reliability, and CMOS markets
  • #4 supplier for full AMS/power IC flow

As a private company they do not reveal their detailed financials. But they will say they are financially strong (cash reserves are 30% revenue) and profitable. Given 200 employees…well, you do the math. They plan to double revenue in the next 3 years by 2018.

They are also in their second year of collaboration with Sematech working on 16nm FinFET TCAD and TSVs, parasitic analysis of 10nm FinFET/SRAM and impact of strain/stress on FinFET performance.


The matrix above shows how their various product capabilities fit together to serve specific markets. In most markets they have a tool portfolio that allows a company to leverage their TCAD capabilities up to SPICE and then go up further to the design and verification level, with everything tied tightly together. This gives them a “TCAD to Signoff” capability.

The key vertical markets that Silvaco brings technology to address are:

  • display: this market is primarily in Asia where all the displays for TVs, computers and phones are manufactured. Almost everyone in the market uses Silvaco for this
  • power (design of processes and circuits for high-voltage switching)
  • optical: this is a pure TCAD play
  • radiation and soft-error analysis: recently declassified Silvaco technology previously restricted to the military is now available for the commercial market
  • CMOS and advanced CMOS: TCAD for process and device development, analog, standard cell and memory cell design

See also If You Plan to put Electronics in Space or Avionics You Must See This Webinar

The market that gets all the glory in semiconductor design is, of course, digital design in leading edge processes, especially for the very high volume mobile market. It is easy to assume that this is the entire market for semiconductors and for tools to design them, but nothing could be further from the truth. Even TSMC does nearly 30% of their volume in non standard designs such as power, flash and MEMS, and if you throw in analog design done in non-leading-edge processes (such as 90um or 130um) it is an even bigger percentage. Silvaco doesn’t really “do” leading edge digital design (no synthesis, place & route and so on) but for all these other designs, including leading edge analog, they have a huge range of technologies to bring to bear.

The different verticals are actually addressed using different key technologies, sometimes special variants of them, combined in different ways. Those key technologies are:

  • TCAD: technology CAD, with a single engine for 1D, 2D and 3D with process, device and stress simulation
  • SPICE modeling and simulation: leading supplier of high-voltage and TFT models, statistical yield analysis
  • custom layout and extraction:highest accuracy capacitance extraction for TFT, analog, SRAM and FinFET. Full flow including layout, schematic, physical verification, extraction and more. Wide range of PDKs available to support many foundries, primarily for analog, mixed-signal, RF including PCells
  • EM/IR: (electro-migration, current/resistance drop analysis) including thermal analysis and reliability flow

Now, also, with the acquisition of Invarian, users of the Silvaco flow have all the data required to enhance their analysis capabilities with Invar, and thereby get the most critical insight on reliability that is required for successful designs.

Silvaco’s website is here.

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Have We Hit the Power Floor?

Have We Hit the Power Floor?
by Brian Fuller on 04-18-2015 at 7:00 am
Categories: EDA

As we celebrate the 50[SUP]th[/SUP] anniversary of the publication of Moore’s Law in Electronics Magazine (April 19, 1965), the industry finds itself in an increasingly costly global effort to keep transistor scaling on track. “Is Moore’s Law dead?” is a common question these days.

But practically speaking the doubling of transistor density every 18 months or so has been pushed off the front pages in the past decade by the crucial need to manage power.

Joel Hruska, writing in Extremetech, notes:

“One of the most striking characteristics of current semiconductor research is how completely the search for lower-power devices has subsumed the old clock speed obsession. 0W has become the new 1GHz. Performance, the old God of Computing is now merely an efficient means to achieve the lowest possible minimal power usage.”

In recent years, our industry has made enormous strides in power management, breathing longer battery life into smaller and smaller devices. But we’re starting to hear whispers of a question that echoes the one surrounding Moore’s Law: Are we approaching a power floor?

That’s one reason events like the annual Electronic Design Process Symposium (EDPS)—being held April 23-24—have become so critical to nurturing a thoughtful conversation about the future of low-power design.

“EDPS is a excellent opportunity for engineers to glean insight from industry experts on the latest techniques to design to increasingly stringent power budgets, consider emerging materials, and develop design flows that optimize implementation and verification for low-power systems,” said Arpana Dey, technical marketing director for standards at Cadence who serves as the 2015 EDPS chair.

The two-day event is being held at the Monterey Beach Resort in Monterey, Calif., and it will be day two that will offer a day-long deep dive into the most pressing engineering concerns surrounding low-power design.

Jim Kardach, director of integrated products at high frequency power conversion startup FinSix, will keynote first thing Friday morning on “Low Power Design, Standards and Evolution.” Kardach’s keynote will be followed by a series of presentations on “Low Power Technologies and Ecosystems,” a session chaired by Naresh Sehgal, senior program manager for Intel’s Imaging and Camera Group.

The Friday afternoon keynote features University of California San Diego computer science and engineering professor Andrew Kahng, speaking on “EDA/ESL Low Power Design Trends, ISTR/CAD and Tools.”

The low-power focus wraps up Friday afternoon with a panel session that I’ll moderate featuring Kahng, Kardach, Bernard Murphy from Atrenta, Steve Carlson from Cadence, Parasad Subramaniam from eSilicon , and Pat Sheridan from Synopsys. We’ll explore how much lower we can push power or whether we’ve hit the practical floor, especially for IoT designs.

Day one features a keynote from Tom Dillinger, Oracle CAD technology manager, which examines two of today’s key materials choices: fully-depleted silicon-on-insulator (FD-SOI) versus FinFETs. After Dillinger sets the stage, he’ll moderate a panel on the topic featuring Kelvin Low, senior director of foundry marketing with Samsung; Boris Murmann, associate professor of electrical engineering at Stanford; Marco Brambilla, director of engineering with Synapse Design; and Jamei Schaeffer, product line manager with GlobalFoundries.

The afternoon lineup on day one includes a variety of presentations in two sessions, one focusing on multi-die challenges and applications (chaired by EDA 2 ASIC President Herb Reiter), the second on hybrid virtual platforms (chaired by well-known industry analyst Gary Smith).

Here’s a link to the complete EDPS program and a link to the registration page. I look forward to seeing you there!

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Successful Venture of an Indian Global VIP Company

Successful Venture of an Indian Global VIP Company
by Pawan Fangaria on 04-17-2015 at 10:00 am
Categories: IP, SmartDV

It’s rare that we find a truly Indian-based company operating globally in the semiconductor space. Although the ‘gold rush’ towards IP development in the last decade initiated many IP start-ups in India, today we rarely find Indian IP company names which are shining in the global arena. The story of services companies is different, but a true product company is rare in India. A great product company needs real fundamental expertise to develop products and an inspirational leadership to strategise and execute in all aspects that can benefit customers across the world.

Although I already had a very good impression of SmartDV Technologies, headquartered in Bangalore, my actual insight about the breadth and depth of this company came into light when I read their last press releaseabout their new VIPs and subsequently had a few interactions with Harish Poojary, VP of worldwide sales and business development at SmartDV.

SmartDV was started in Bangalore, India in 2008 by a few highly talented and experienced individuals in complex ASIC design and verification domain. That was the right time when IP integration into large complex SoCs had picked up momentum. Deepak Kumar Tala, the Founder & CEO of the company had a great vision to grab this opportunity to automate verification through the use of VIP (Verification IP) and save enormous time spent in verifying complex SoCs. SmartDV management team feels proud of remaining ahead of the game by delivering a VIP for a protocol as soon as its final specification is released or even before that; a great strategy to help customers hitting the bull’s-eye during a smallwindow of opportunity in the SoC market.

SmartDV has a large portfolio of over 75 high-quality standard and custom protocol VIP products that work well with coverage driven verification flow. Each VIP comes with complete compliance test suite, comprehensive functional coverage model, and a rich set of customization and protocol checks to speed up the verification of designs. SmartDV VIPs are two to four times faster to compile and simulate compared to those offered by the competition. The test cases, coverage models and sequence libraries delivered with the VIP can be easily modified according to the customer environment to speed up the verification of SOCs at the customer end. The VIP portfolio is available in UVM, SystemVerilog, VMM, OVM, VERA, Verilog, Specman e, SystemC, or any other non-standard native environment of customer choice. No wrappers are added, thus enhancing the performance and simplifying debugging. The portfolio includes MIPI, Networking and SoC, Automotive and Serial Bus, and Storage VIPs, Memory models and Design IPs. Look at their product portfolio at their website here.

Above is an example of their recently released Networking and SoC VIP. The AMBA5 CHI VIP provides a smart and easy way to verify the ARM AMBA5 CHI component of an SoC. The AMBA5 CHI VIP is fully compliant with standard AMBA5 CHI specification and is supported natively in SV, UVM, OVM, VMM, Verilog, VERA, SystemC, Specman E, and any other language of customer choice. Similarly there are other VIPs, Design IPs, and memory models such as DDR4 and LPDDR4 that are conceived to be better than those available in the market.

What makes SmartDV so successful? Well, it’s the overall strategy, execution and operational excellence. However a couple of key points that emanate and significantly contribute in the success of SmartDV are – i) SmartDV’s own language and compiler technology that automated VIP development thereby enabling faster VIP development, ii) an automated development flow from specification to final product including documentation, and iii) a highly talented and experienced team that produces high quality products. The net result is “high quality products in short time with a smaller team size” said Deepak Kumar Tala. In fact, there were occasions when use of SmartDV VIPs exposed bugs in already taped-out chips; those bugs had passed the tape-out with VIPs supplied by other vendors.

As the engineering team continued developing their portfolio of IP products, business grew over the years without any marketing/sales efforts. In January 2014, SmartDV opened its office in San Diego, CA (USA)under the leadership of Harish Poojary. The strategy was to reach out to customers with better support, develop long term partnership, and profit from broader market opportunities. Today SmartDV has 80+ customers worldwide. They have plans to further expand in Japan and Taiwan. They are also working on automating memory models and simulation acceleration of VIP’s development.

SmartDV’s customers include top semiconductor companies in wireless, automotive, storage, memory and networking domains. Many of them have taped-out chips using SmartDV VIPs and are very impressed with the results.

SmartDV is exhibiting in DAC 2015. Visit their booth #514 to see the latest and greatest from this company.

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Coventor, Lego and IoT in Denmark

Coventor, Lego and IoT in Denmark
by Paul McLellan on 04-17-2015 at 7:00 am
Categories: Coventor, EDA

Coventor were in Copenhagen Denmark a few weeks ago at the Smart Systems Integration Conference to talk about MEMS and IoT entitled (take a deep breath) Towards a Lego Block Principle for Heterogonous Systems Design Including MEMS and Electronics—Choose and Put Together Fit. Since this seems to have become IoT week for me, without any deliberate plan, this seems very appropriate. After all, “Heterogonous Systems Design Including MEMS and Electronics” screams IoT. And also appropriate is to have the discussion in Copenhagen since Denmark is the home of Lego (in Billund, which is nowhwere near though). Also, Lego have to be one of the few companies that manufacture parts in semiconductor type volumes with a over a half-trillion bricks produced since the company’s founding in 1949. For some reason, Americans pluralize Lego to Legos even though the rest of the world appears not to (the other way around from mathematics which, in England at least, we abbreviate to maths while the US goes with math).

I was talking to someone yesterday, not at Coventor, who was telling me they had a lot of design technology for MEMS very early on and yet, even today, are not really in the market. I pointed out that history is littered with companies who entered some aspect of the MEMS market way too early and flamed out having run out of money. EDA is like that, more companies fail by being too early than too late.

Anyway, MEMS is clearly here now. It is now a multi-billion dollar industry and most of us have, in our pockets, accelerometers, gyroscopes and more inside our phones. Our cars know when they are crashing, our computers can detect they have been dropped, and many of us have a Fitbit band or something equivalent on our wrists (or sitting unused in a drawer at home). So what the somewhat confusing title, the discussion was about why MEMS is different. Why can’t we abstract design and do it in a manner similar to CMOS digital design? What is the equivalent of a transistor in MEMS? And if that approach is not going to work (after all, most digital designers rarely even see a transistor) can’t we at least have a Lego approach similar to how we assemble large SoCs out of blocks of pre-designed IP?

Of course, these days even analog CMOS designers don’t actually care that much about transistors, especially in the FinFET era. EDA tools with PDKs shield designers from such “details” and allow them to focus on functional blocks such as differential pairs, current mirrors, common-source, common-gate and common-drain circuits. So how hard can it be to have a standard MEMS flow?

This is not a new topic. Indeed, as Coventor’s panelist Gunar Lorenz pointed out on his blog entry, this was a topic he had discussed 15 years earlier with his PhD supervisor (and co-panelist) Richard Neul. So has Coventor solved the problem and convinced the MEMS design community that a library-based MEMS design flow is possible or even desirable? Not entirely. As a matter of fact there are MEMS designers who cherish and defend their freedom to draw about any idea which comes to mind in a layout editor without concern for restrictions imposed by a MEMS component library. To those of us with an EDA background this sounds just like the arguments we have had for decades: why can’t analog designers get with the program and automate their work…only even worse.

The introduction to the panel was given by Tobias Maier from Robert Bosch who emphasized the widely felt frustration about the lack of a standard design methodology for MEMS. The essence of the current MEMS design flow (or lack thereof) was nicely captured in a slide by Jörg Doblaski of XFAB, presented earlier in the conference:
Gunar isn’t exactly a neutral player in this discussion. Starting with his PhD at Robert Bosch and later as lead developer of Coventor’s Architect and MEMS+ software for MEMS design, he has tried to prove that a wide variety of MEMS designs can built up from a library of basic building blocks. No, there is not a single building block such as a transistor in MEMS. But yes, MEMS devices can be assembled from a set of building blocks such as plates, beams, comb drives, electrodes and anchors.

Any ally in the battle was Peter Merz from X-Fab. Foundries hate freehand layouts. Foundries have difficulties with checking designs rules on “freehand” layouts. It’s exceedingly difficult to set up automated DRC’s which in fact are written for MEMS building blocks. Hmm, this starts to sound like analog again!

But Coventor and X-Fab have been working together on all this, and along with Cadence have “conspired” to announce to create the world’s first MEMS-specific design automation enablement based on PDKs. As close to Lego as anyone has presently managed.

Gunar’s blog entry is on the Coventor website here.

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Don’t Miss Mentor Graphics U2U San Jose, April 21, 2015

Don’t Miss Mentor Graphics U2U San Jose, April 21, 2015
by Beth Martin on 04-16-2015 at 10:00 pm
Categories: EDA, Siemens EDA

Mentor Graphics’ User2User conference will be held next week on April 21[SUP]st[/SUP] at the San Jose DoubleTree Hotel. This one-day, free conference is the perfect opportunity to learn, network, and share with other Mentor Graphics users.

The day starts off with back-to-back keynotes that examine different aspects of the hot topic of the Internet of Things. Wally Rhines Chairman & CEO, Mentor Graphics will address the pressing issue of Secure Silicon and how it is necessary to enable the Internet of Things. Karim Arabi, VP of Engineering, Qualcomm, will then explore the market trends and technologies driving the Internet of Things. Daniel Nenni recently discussed their keynotes here.

There’s a big new addition to User2User this year: the first-ever Emulation track, which includes an overview session from Mentor, and customer presentations from Altera, ARM, Marvell, and Soft Machines on their use of the Veloce Emulation platform. So if you’re a Veloce user, make sure you check out these sessions.

There is, of course, a free lunch at noon. You have the choice to also attend a special lunch session in the Silicon Test & Yield Analysis track. While you nourish your body, Broadcom presenter Kamlesh Pandey will feed your mind with his story of how they reduced ASIC test costs using Mentor’s new EDT test point insertion technology. Other Test presentations cover the use of IJTAG (IEEE 1687) at Cisco, finding memory failures at Broadcom, and what to do with failed EDT chain patterns at Microsoft.

I’ve written previously about IJTAG, a newly ratified standard for IP integration, access, and control that should be sweeping the nation any time now. I look forward to seeing how Cisco actually adopted and validated IJTAG and what benefits they saw.

The Broadcom presentation should be a big draw because in it, Amar Guettaf, the Technical Director of the Operations Group at Broadcom, talks about how to find the root cause of memory failures. He introduces a new bitmapping flow that apparently has dramatically simplified the MBIST bitmapping process and reduced the ATE development cycle. The last Test track presentation of the day is from Jeff Hung, Senior DFT engineer at Microsoft. He shares how they solved a situation in which scan patterns were working on ATE, but EDT chain patterns were consistently failing. All the Test track presentations are described here. Because the Test group at Mentor is full of really nice people who like to have fun, they are also offering some special prizes for their audience that you can win through a drawing.

After lunch, a panel of key executives from eSilicon, GLOBALFOUNDRIES, Mentor Graphics, TSMC, and STMicroelectronics will discuss “The Changing Foundry Landscape: Trends and Challenges.” Moderated by Semiwiki’s own Daniel Nenni, this panel of experts will discuss SoC trends, challenges, and new applications that will drive future generations of semiconductor design and manufacturing.

Along with the keynotes and industry panel, the day is packed with a full agenda of 9 major session tracks, led by top industry customers and Mentor’s top technologists. The tracks cover everything from AMS Verification (described eloquently by Dan Nenni in this blog), Calibre, Emulation, and IC Design Implementation, to PCB, Silicon Test Solutions, Thermal Simulation and Measurement and Verification.

Other activities in this full day include:

Usability Lab
Interactive sessions let you give Mentor direct feedback on product improvements.

Demo Booths
Mentor Technical staff will be available outside the session rooms to answer all of your questions.

Networking
This is your chance to network with your peers on future technology and strategy. See the snapshot to the right for an idea of what the happy hour is usually like after a Mentor U2U.

You can download the full User2User agenda hereand register for FREE here.