SemiWiki – Page 740 – The Open Forum for Semiconductor Professionals

June 2, 2015

The State of Desktops, Notebooks and Tablets

The State of Desktops, Notebooks and Tablets
by Daniel Payne on 06-02-2015 at 10:00 am
Categories: General, Mobile

The personal computing market started out back in the late 1970’s, with IBM being a relative late-comer in 1981, however over many decades we’ve seen the unit volumes steadily increasing each year driving demand of semiconductors of all types. IC Insights is a research company that follows the personal computer market and they define this market as having several categories:

Standard PCs (desktops and notebooks)
Tablets (i.e. iPad)
Internet/Cloud-computing systems (i.e. Chromebook)

I’ve been a notebook user for the past 15 years so it’s been a long time since I owned a desktop, although I have three sons that use custom-built desktops for gaming with high-end graphics cards. Our household also has four notebooks, two iPads, a Nexus 7 tablet, and Chinese-brand tablet. We own no cloud-based systems.

Observations from the newest IC Insights report include:

Tablets took off in 2010 with the iPad
Tablet sales became greater than notebooks in 2013
Tablet growth slowed suddenly in 2014
Large-screen phones like my Samsung Note 4 slowed tablet growth even more in 2015
The overall PC market will decline in 2015
Desktop and Notebooks peaked in 2012 at $345M

I agree that the utility of a 5.7″ display on my smart phone makes it easier for me to carry around everywhere, all day, decreasing my need to use a tablet or notebook device to review updates on LinkedIn, Twitter or Strava.

IC Insights now predicts a CAGR of just 2.1% for PC unit shipments from 2013 to 2018, where total PC shipments will reach 578 million in 2018. Tablets are expect to make up a healthy 45% of total systems sold in 2018, down from the previous forecast of 57%. It’s startling for me to read how quickly our world economy responds to technology trends and to witness the first decline in total PC shipments this year.

I’ve played with the Internet-centric Chromebooks from Google and Samsung while shopping at my local BestBuy store, but have never been impressed enough to actually buy one, especially in light how they compare against a more fully-featured laptop at a slightly higher price point. When my youngest daughter started college we thought about buying a Chromebook, but instead opted for a Samsung laptop priced at just $75 more.

For the full report details visit IC Insights and request their IC Market Drivers 2015 report, priced at $3,390 to an individual or $6,490 for a multi-user corporate license.

June 1, 2015

Ultra-Low Power Non-Volatile Memory Solutions for the Smart Connected Universe

Ultra-Low Power Non-Volatile Memory Solutions for the Smart Connected Universe
by Tom Simon on 06-01-2015 at 6:00 pm
Categories: IoT, IP, Sidense

DAC is a great place to gather information about products and technologies. However it can be difficult to chase down the information you need because you may need to cover a lot of ground to hear or talk to the people with the right knowledge. Fortunately there are a few places you can go to learn about a number of products at one place. A really good example of this is the Open Innovation Platform Theatre that is hosted by TSMC. Throughout this year’s DAC they will have speakers from their ecosystem partners giving short presentations on important topics.

One such presentation will be given by Sidense CTO Wlodek Kurjanowicz on the topic of Ultra-Low Power Non-Volatile Memory Solutions for the Smart Connected Universe. Sidense sees the combined market segments of mobile, IoT, medical, automotive and the cloud infrastructure needed to support them as a key areas for product development. Low power requirements are prevalent within this category. Durable non-volatile memory is needed for many purposes, including security codes, calibration trim information storage, device ID’s, secure boot code storage, etc. Having the ability to use standard CMOS processes and minimize power consumption are important success factors.

Sidense will also be presenting at the Chip Estimate booth on the more general topic of Memory Requirements in the Smart Connected Universe. As is usually the case I’m sure there will be a video of this presentation produced by Chip Estimate for viewing later. There are already videos concerning Sidense available at Chip Estimate. A lot of useful information about Sidense and their offerings can be found on that page, including recent additions to their process availability matrix.

However seeing the presentation in person and having the opportunity to speak directly with their technical experts is invaluable. Webinars and video conference calls are convenient and useful, but meeting people face to face can never really be replaced. Hopefully you can leave DAC with your questions answered and much more confident in a vendor’s ability to deliver critical elements for your projects.

In the case of Sidense, it is their IP that get incorporated into the finished product design. Understanding their foundry qualification process, design methodology, as well as interface & programming options by having them explained first hand would be hard to pass up if you are looking for a non volatile memory solution.

The TSMC OIP presentation will be offered on Monday 6/8 at 11:30 AM, Tuesday 6/9 at 3:15PM and Wednesday 6/10 at 2:00PM in booth #1933. The Chip Estimate presentation will be offered on Tuesday 6/9 at 2:30PM and Wednesday 6/10 at 1:30PM at booth #2433. For info on both presentations there is a link here.

June 1, 2015June 14, 2019

Aldec packs 6 UltraScale parts on HES-7

Aldec packs 6 UltraScale parts on HES-7
by Don Dingee on 06-01-2015 at 12:00 pm
Categories: Aldec, EDA, FPGA

A few months ago, when the Xilinx UltraScale VU440 FPGA began shipping, one of the immediate claims was a quad-FPGA-based prototyping board touted as “Godzilla’s Butcher on Steroids”. That was a refreshing and creative PR approach, frankly. I’m always careful with less creative terms like “world’s biggest” or “world’s fastest”, because they can overstate a snapshot – such a claim can easily dissipate tomorrow. I prefer a term like “industry first” since it recognizes that.

If the news of four UltraScale parts on a board was big back then, Aldec’s announcement of six UltraScale VU440 parts on a single board is bigger. This is a major upgrade to the Aldec HES-7 12000 platform, supplanting the Xilinx Virtex-7 devices on it. In the previous configuration, four boards each with six Virtex-7 parts offered up to 288M gates.

This new UltraScale frontier for HES-7, coming in 3Q15, puts together four boards each with six UltraScale VU440s for a capacity of up to 633M gates. I do expect others to try to match the sheer capacity of this FPGA-based prototype offering soon, but for now, Aldec leads with an industry first.

Matching the rest of the Aldec HES-7 offering will be more challenging for its competitors. Aldec’s high speed backplane supports the interconnect needed to keep UltraScale parts running at their potential. Their HES-DVM automated partitioning capability leverages SCE-MI to help connect the physical FPGA hardware to software simulation features for more complete verification. Aldec offers a range of off-the-shelf daughtercards for HES-7, including a Xilinx Zynq-based board, along with support for FMC modules. They also offer custom design services for daughtercards, aiding in incorporating exact copies of hardware, crucial in safety-critical and DO-254 validation.

UltraScale parts introduce another aspect where Aldec has an industry leading solution: clock domain crossings (CDCs). The clock resources in UltraScale architecture have been completely redesigned. The good news is the design flexibility and ease of synthesis closure has been greatly increased. At the same time, the odds of CDCs occurring have also increased. Without mitigation, CDCs can cause unpredictable effects such as metastability and data incoherence. Aldec ALINT-PRO-CDC is geared to comprehensively find CDCs, examine synchronizer constructs, and flag issues for designers. This tool is handy for both FPGA designers and SoC teams using FPGA-based prototyping, since CDCs play no favorites – especially when doing manual partitioning.

In other words, Aldec is not just gluing constantly bigger parts on boards and calling it a day. They are assembling a complete set of capability for FPGA-based prototyping, from design to simulation to debug to verification to compliance, enabling more FPGA and SoC designers to get more done quickly and reliably. There is more of this story in the press release:

Aldec HES-7 with Xilinx Virtex UltraScale Devices Enables True FPGA-based Verification

For those attending DAC 52 in fabulous San Francisco with exhibits starting June 8, Aldec will be offering eight technical sessions on a range of topics. Session 1 focuses on FPGA-based prototyping and the scalability UltraScale devices bring to HES-7 Ultra. Registration for these sessions is free to DAC exhibit attendees but first-come, first-served with limited seating, simply follow the online form linked above to reserve a spot.

June 1, 2015

The Trojan Horse Was Free Too

The Trojan Horse Was Free Too
by Paul McLellan on 06-01-2015 at 7:00 am
Categories: IP, Kilopass Technology

Timeo Danaos et dona ferentes. I fear the Greeks especially when bearing gifts. In Virgil’s Aeneid these words are spoken by the Trojan priest Laocoön warning about the wooden horse that the Greeks have offered Troy. But to no avail, Laocoön is slain by serpents and the Trojans bring the horse inside the walls of Troy. Since the horse was full of Greek soldiers this turned out to be, shall we say, sub-optimal.

The free eFuse cell from foundries can be sub-optimal too. Is it a just a gift or a Trojan horse. While it is going too far to fear the foundries when they are bearing gifts of free IP, in the case of eFuses they do come with their own set of problems hidden inside. This is especially so as we get down to small process geometries. At 16nm and below the eFuse cell is getting so large that it threatens to dominate the chip in designs that require large NVMs. A much more practical choice is to use an antifuse approach. With lower power and higher speed, and with 1/300th of the area, what’s not to like?

When you start to take security into account, and many NVMs are used for holding serial numbers, encryption keys and the like, then antifuse becomes even more attractive. eFuse bits can be read out by looking at the bit cells to see if the fuse is blown or not. Antifuse stands up to even the most vigorous and destructive attempts to read out the programmed value, not just to commercial standards but military too.

One more big advantage is that the antifuse-based NVMs do not require special power supply voltages and so can be programmed after packaging, whereas eFuse-based memories normally have to be programmed on the wafer before they are packaged. Programming after packaging can make supply chain management a lot easier since there are many applications where the code to be programmed is not known until late in the manufacturing cycle.

If Orange is the New Black then Antifuse is the new Fuse. Kilopass will be on three booths at DAC next week showing various aspects of their antifuse NVM technology and why it is the NVM bitcell for the future.

Tney will presentAntifuse Memory: The New NVM Foundation IP in the ChipEstimate booth (#2433) on:

Monday, June 8, at 1:30 p.m.
Tuesday, June 9, at 11:30 a.m.
Wednesday, June 10, at 2:30 p.m.

They will demonstrate in the ICScape Booth (#1602) how ICScape’s design tools have contributed to Kilopass’ development of a wide range of NVM IP’s ultra low-power and high-performance features, fast access speed, megabits of capacity and more than 10 years of data retention.

In the TSMC Booth (#1933), Kilopass will showcase its NVM IP’s availability on all TSMC process nodes from 180nm to 20nm and offer a look at how antifuse technology is the future NVM foundation IP, replacing eFuse below 16nm. Their sessions are scheduled for:

Monday, June 8, at 2:15 p.m.
Tuesday, June 9, at 4:45 p.m.
Wednesday, June 10, at 10:15 a.m.

May 31, 2015June 14, 2019

Will those IO pad rings pass foundry muster?

Will those IO pad rings pass foundry muster?
by Beth Martin on 05-31-2015 at 10:00 pm
Categories: EDA, Siemens EDA

I was talking recently to Dina Medhat, a senior technical marketing engineer at Mentor, about, of all things, IO rings. It has not occurred to me that verifying that your IO rings comply with foundry rules presents new challenges.

IO ring checking isn’t new, nor is it unique to advanced IC process nodes. However, the same forces of complexity and physics are in play in all aspects of IC design, requiring careful consideration when planning IO pad rings. Medhat says there is a distinct need for a robust, automated flow to do IO ring checking. She told me about some of these challenge and what she’s been doing to create an automated LEF/DEF-based IO ring checking flow that is flexible and can target different foundries.

Consider that designs typically include IP from multiple vendors, and each vendor has its own set of rules. One important goal of pad cell placement is good electrostatic discharge (ESD) protection when co-locating dissimilar types of cells, such as digital logic, analog cells, processor cores, IO power pads, IO ground pads, termination cells, and so on. Evaluating the design against the many different IP rules, and more especially the rule interactions, depends on automated checking. The remaining question for design teams is how to set up such a flow.

First, says Medhat, let’s look at what the foundries provide—a design rule manual (DRM) with guidelines for pad cell placement that guarantee the required ESD protection when using a given library. Designs must follow these rules when digital, analog, core input, and output (IO) power and ground pads are placed in an IO ring. Common rules that you see in DRMs include:

Cell types that can be used in an IO ring
Minimum number of a specified power cell per IO ring section and given power domain
Maximum spacing between two power cells for a given power pair in a power domain
Maximum distance from the IO ring section termination to every power cell
Maximum distance from IO to closest power cells
Maximum continuous IO ring section of filler without any interruption (breaker or dummy ESD cells)
Cells that must be present at least once per corresponding power domain section
Constraints for multi-rows implementation

The obvious question is “How can I make sure that my design is safe and that I applied all these rules correctly?” A more subtle question is “Are the rule constraints for these cells the same for all IPs and all foundries, or are they cell- and foundry-specific? If they are different, how do I handle this complexity in an automated flow?”

Of course, constraints are different from one foundry to another, as well as from one technology node to another, and one IP supplier to another. Complying with all of these rules is extremely important, but it’s not easy, and it’s not something you want to do manually. Designers need an automated solution to ensure compliance and improve ESD protection in their designs, but it must also be flexible enough to handle all the details and variations without overwhelming the design team with rule coding, says Medhat.

As with most IC design technologies these days, the ‘ecosystem’ code word applies. The EDA vendors must work with their customers to establish an automated framework to verify compliance with the foundry’s IO placement rules. Medhat has recently spent a fair amount time demonstrating the practicality of this approach using Calibre PERC on real customer designs.

“The input are LEF/DEF files, and all the common rules are already coded in our IO Ring Checker framework,” says Medhat. “Users define their unique constraints using the constraints interface (input form), which is part of the framework, then point to their LEF/DEF database. Executing the IO Ring Checker framework generates two outputs: a violations text report and a violations database, both of which can be loaded into a results viewer like Calibre RVE to debug violations graphically.”

The IO Ring Checker is pretty new, which is why Medhat is presenting results at the DAC Work-In-Progress session on Wednesday evening, June 10, from 6:00-7:00 pm. Look for “LEF/DEF IO Ring Check Automation” (86.65).

Are any of you are incorporating automated techniques for IO ring checking? If so, what techniques are you using, and what are your challenges, results, best practices?

May 31, 2015

NVIDIA and Qualcomm Talk about High Level Synthesis, Samsung on Low Power for Mobile

NVIDIA and Qualcomm Talk about High Level Synthesis, Samsung on Low Power for Mobile
by Daniel Payne on 05-31-2015 at 4:00 pm
Categories: EDA

Since 1978 I’ve seen many trends in the semiconductor design world: transistor-level IC design, gate-level design, RTL coding, High Level Synthesis (HLS) and IP re-use. We’ve witnessed the growth in design productivity enabling chips starting with just thousands of transistor all the way up to billions of transistors by using newer design paradigms and more advanced process nodes, like 14 nm FinFET in production now. One EDA company focused on HLS and low power design has an interesting story to tell at the upcoming DAC conference and exhibit in June by inviting NVIDIA, Qualcomm and Samsung to talk about their hands-on experiences. Calypto is the company, and I’ve just chatted with Mark Milligan to get a preview of what’s to come at DAC.

FinFET transistors have been all the rage ever since Intel started talking about tri-gate a few years back, and since then we’ve seen foundries like TSMC, Samsung and GLOBALFOUNDRIES all provide FinFET processes to designers. Leakage power is reduced in FinFET technologies, but on the flip-side there’s an increase in dynamic power that needs to be dealt with during design. On the EDA methodology side you can consider using a tool like PowerPro from Calypto to:

Support multiple use case scenarios in creating low-power RTL
Exploring RTL alternatives for low-power
Guided or automated optimization using formal equivalency proofs
Get quick and early RTL power analysis at both block and chip levels

Samsung is my favorite smartphone company and I love the long battery life on my Galaxy Note 4 device and large 5.7″ display. You’ll want to hear how Samsung engineers used a power optimization flow that included formal verification with SLEC pro, and had lint, CDC and autocheck compliance.

Qualcomm has been using both high-level synthesis and high-level verification (HLV) on their image processing IP. Engineers are now using a standardized HLS/HLV design and verification flow. Chips used for smartphone applications have been successfully designed with this new methodology.

NVIDIA is a well-known leader in all things related to graphics chips. They first evaluated then adopted HLS and HLV for their TEGRA mobile processors. Come and find out how they moved from a traditional RTL flow to an HLS/HLV flow to accelerate both the design and verification processes.

There are also a couple of tutorials that you can sign up for at DAC that can answer your detailed questions about what the learning curve is like when using C and SystemC as a design language:

The second tutorial on building the iDCT (Inverse Discrete Cosine Transform) will walk you through algorithm coding practices, optimization steps, and how to achieve the best QoR. You should attend this tutorial if you’ve never used an HLS approach before, and be sure to ask lots of questions to get clarification.

Summary
RTL coding had its place in history, and now is the time to consider moving up to HLS and HLV to accelerate both design and verification of your next SoC. DAC is an incredible place to learn about these technologies, and find out how they would fit into your flows.

May 31, 2015

Atmel Tightens Automotive Focus with Three New Cortex-M7 MCUs

Atmel Tightens Automotive Focus with Three New Cortex-M7 MCUs
by Majeed Ahmad on 05-31-2015 at 11:30 am
Categories: Arm, EDA, IoT, IP

Atmel Corp., a lead partner for the ARM Cortex-M7 processor launch in October 2014, has unveiled three new M7-based microcontrollers with a unique memory architecture and advanced connectivity features for the connected car market.

According to the company spokesman, E70, V71 and V70 chips are the industry’s highest performing Cortex-M microcontrollers with six-stage dual-issue pipeline delivering 1500 CoreMarks at 300MHz. Moreover, V70 and V71 microcontrollers are the only automotive-qualified ARM Cortex-M7 MCUs with Audio Video Bridging (AVB) over Ethernet and Media LB peripheral support.

Cortex-M7: Bridging the gap between MPUs and MCUs

Atmel is among the first suppliers to introduce the ARM Cortex-M7-based MCUs. The ARM Cortex-M7 core combines performance and simplicity and further pushes the performance envelope for embedded devices. Atmel’s new MCU devices are aimed to take the connected car design to the next performance level with high-speed connectivity, high-density on-chip memory, and a solid ecosystem of design engineering tools.

Atmel’s Memory Play

Atmel has memory technology in its DNA, and that seems apparent in the design footprint of E70, V70 and V71 microcontrollers. The San Jose, California–based chipmaker is offering a flexible memory system that is optimized for performance, determinism and low latency.

Jacko Wilbrink, Senior Marketing Director at Atmel, said that the company’s Cortex-M7-based MCUs leverage Atmel’s advanced peripherals and flexible SRAM architecture for higher performance applications while keeping the Cortex-M class ease-of-use. He added that the large on-chip SRAM on SAM E70/V70/V71 chips is critical for connected car and IoT product designers since it allows them to run the multiple communication stacks and applications on the same MCU without adding external memory.

On-chip DMA and low-latency access SRAM architecture

Avoiding the external memories reduces the PCB footprint, lowers the BOM cost and eliminates the complexity of high-speed PCB design when pushing the performance to a maximum. Next, Tim Grai, another senior manager at Atmel, pointed out another critical take from Cortex-M7 designs: The tightly coupled memory (TCM) interface. It provides the low-latency memory that the processor can use without the unpredictability that is a feature of cache memories.

Grai says that the most vital memory feature is not the memory itself but how the TCM interface to the M7 is utilized. “The available RAM is configurable to be used as system RAM or tightly-coupled instruction and data memory to the core, where it provides deterministic zero-wait state access,” Grai added. “The arrangement of SRAM allows for multiple concurrent accesses.”

Cortex-M7 a DSP Winner

According to Will Strauss, President & Principal Analyst at Forward Concepts, ARM has had considerable success with its Cortex-M4 power-efficient 32-bit processor chip family. “However, realizing that it lacked the math ability to do more sophisticated DSP functions, ARM has introduced the Cortex-M7, its newest and most powerful member of the Cortex-M family.”

Strauss adds that the M7 provides 32-bit floating point DSP capability as well as faster execution times. With the greater clock speed, floating point and twice the DSP power of the M4, the M7 is even more attractive for applications requiring high-performance audio and even video accompanying traditional automotive and control applications.

Atmel’s Grai added an interesting dimension to the DSP story in Cortex-M7 processor fabric. He pointed out that true DSPs don’t do control and logical functions well and generally lack the breadth of peripherals available on MCUs. “The attraction of the M7 is that it does both—DSP functions and control functions—hence it can be classified as a digital signal controller (DSC).”

Grai: Improvement in DSP performance is a key M7 highlight

Grai quoted the example of Atmel V70 and V71 microcontrollers used to connect end-nodes like infotainment audio amplifiers to the emerging Ethernet AVB network. In an audio amplifier, you receive a specific audio format that has to be converted, filtered, modulated to match the requirement for each specific speaker in the car. So you need Ethernet and DSP capabilities at the same time.

Grai says that the audio amplifier in infotainment applications is a good example of DSC: a mix of MCU capabilities and peripherals plus DSP capability for audio processing. Atmel is targeting the V70 and V71 chips as a bridge between large application processors and Ethernet.

Most of the time, the main processor does not integrate Ethernet AVB, as the infotainment connectivity is based on Ethernet standard. Here, the V71 microcontroller brings this feature to the main processor. “Large SoCs, which usually don’t have Ethernet interface, have slow start-up time and high power requirements,” Grai said. “Atmel’s V7x MCUs allow fast network start-up and facilitate power moding.”

About SAM E70, V70 and V71

Atmel’s three new MCU devices are aimed at multiple aspects of in-vehicle infotainment connectivity and telematics control.

The SAM E70 building blocks

SAM E70: The microcontroller series features Dual CAN-FD, 10/100 Ethernet MAC with IEEE1588 real-time stamping, and AVB support. It’s aimed at automotive industry’s movement toward controller area network (CAN) message-based protocols holistically across the cabin, eliminating isolation and wire redundancy, and have them all bridged centrally with the CAN interface.

SAM V70: It’s designed for MediaLB connectivity and leverages advanced audio processing, multi-port memory architecture and Cortex-M7 DSP capabilities. For the media-oriented systems transport (MOST) architecture, old modules are not redesigned. So Atmel offers a MOST solution that is done over Media Local Bus (MediaLB) and is supported by the V70 series.

SAM V71: The MCU series ports a complete automotive Ethernet AVB stack for in-vehicle infotainment connectivity, audio amplifiers, telematics and head control units. It mirrors the SAM V70 series features as well as combines Ethernet-AVB and MediaLB connectivity stacks.

Changing Trends at the Top of Semicon Space

Changing Trends at the Top of Semicon Space
by Pawan Fangaria on 05-31-2015 at 5:00 am
Categories: EDA, Foundries

As we have moved down from a CAGR of ~9% over last three decades to a CAGR of ~5% in the current decade, it’s time to check the realities. It can be definitely argued that a 5% of CAGR over a solid base of ~$378 billion should be considered good enough. In my view that’s the sign of maturity in the semiconductor market. At the same time we are seeing certain upcoming businesses like IoT that touches upon several other businesses such as automotive, medical, home etc. These businesses can bring new life to semiconductor industry, but who could be the winners? Generally speaking it’s the maturity cycle of an industry when new players emerge either to take on the existing businesses or come up with new products and technologies to change the scenarios. Also mergers and acquisitions take place between existing players. We are seeing all of these happening in the semiconductor space these days.

I reviewed IC Insights’ report of top20 semiconductor suppliers according to their sales numbers in 1Q 2015. This report shows some interesting data that indicates the changes we may see in the top rankings of semiconductor companies in the near future.

In the report there are 7 companies in US, 3 in Taiwan, 2 in South Korea, 4 in Japan, 3 in Europe and 1 in Singapore. The group of top20 companies includes pure-play foundries, fabless companies and IDMs. We have seen their 2014 results earlier, but the changes between 1Q2014 and 1Q2015 as mentioned in the 1Q2015/1Q2014 column of the table reveal a lot about changing trends.

The average sales of top20 companies increased by 9% compared to 6% for the overall semiconductor industry. What is interesting is that out of 7 US companies, sales for 6 companies increased by less than 7%, only GlobalFoundries had a sales increase by 21%. Intel was flat at 0%. On the other hand, 5 companies outside US showed more than 20% increase in sales; these are TSMC at 44%, SK Hynix at 25%, Avago at 24%, Sony at 26%, and Sharp at 62%.

The Japan-based Sharp had a dramatic entry into top20 list of semiconductor companies with a whopping 62% sales increase, riding on its success in the CMOS image sensor market. The other non-US company that entered the top20 list is Taiwan-based pure-play foundry UMC. Who were pushed out of the top20 list? They are US-based companies NVidia and AMD. It’s also interesting to note that Taiwan-based Media Tek has entered the list of top10 ranks.

My other investigation into the data shows that the 7 US companies accounted for $116909 million sales in 2014, i.e. 45% of total top20 companies’ sales, whereas the sales in 1Q 2015 were $27492 million, i.e. less than 43% of total top20 companies’ sales in 1Q 2015.

On the other hand, if I add up the numbers of 3 Taiwan-based and 2 South Korea-based companies, they account for $90454 million, i.e. 35% of total top20 in 2014, and $23643 million, i.e. ~37% of total top20 in 1Q 2015.

Clearly sales trend is pointing upwards for the east-Asia companies and downward for US companies. Well, there are mergers also happening which will definitely change equations in the top20 leaders of the semiconductor industry. NXP along with Freescale will push Europe into top10. ST is just out of top10 as per 1Q 2015 data. Similarly there are other equations that can change the top10 and top20 rankings for companies.

It will be interesting to watch the top20 list through 2015 and 2016. Read the IC Insights’ report here.

Also read “30+ Years of Semiconductors – The base matters!” to check the semiconductor sales trend over last 30 years, and “Look who is Leading the World Semiconductor Business” to check the 2014 list against that of 2013.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

May 30, 2015

Semiconductor Acquisitions will Fuel Innovation!

Semiconductor Acquisitions will Fuel Innovation!
by Daniel Nenni on 05-30-2015 at 7:00 am
Categories: EDA, eSilicon, Foundries, IP

Has the semiconductor world gone acquisition crazy? It certainly seems that way with the more than $60B in M&A activity which may now include Altera. We are probably getting close to the 80/20 rule where 80% of the semiconductor revenue is being generated by 20% of the companies. Not far off from where we were at 25 years ago when the fabless semiconductor transformation began. It really is deja vu all over again.

Some say the winners in all of this are the investors and the losers are the thousands of semiconductor professionals that will lose their jobs due to the consolidation. I say we are all winners because of the changes we are starting to see in design enablement that will spawn a new generation of fabless semiconductor companies. The most recent change that interests me the most is the application of big data and portals to semiconductor design and manufacturing by the ASIC companies. Think Uber for semiconductor design.

Let’s face it, in order to usher in the next generation of fabless semiconductor companies we will have to make it cheap and easy to go from RTL to a finished chip from anywhere in the world. In the early days of the ASIC business model in Silicon Valley you could literally go from a design on a cocktail napkin to a finished chip. Things are a bit more complicated now since we rely on third party IP and have to squeeze every watt of power possible out of our designs. There is also the problem of getting a design through a foundry with a minimal amount of time and money.

Fortunately that is what today’s ASIC companies do for a living. The ASIC business is very competitive and margin centric so not only do they have to get it right the first time, they also have to optimize the hell out of the chip so that it will sell millions of units to get the appropriate ASIC ROI. After delivering many millions of chips to a broad spectrum of applications, the level of internal automation at an ASIC company is like nothing you have ever seen, absolutely.

And now ASIC companies are opening up this level of automation with big data attached to the world through online portals. It really is exciting, especially for the thousands of semiconductor entrepreneurs that will be affected by the megamergers of late and the tidal wave of IoT designs that are coming our way.

Synopsys Software Integrity: Find All the Bugs

Synopsys Software Integrity: Find All the Bugs
by Paul McLellan on 05-29-2015 at 9:30 am
Categories: EDA, Synopsys

A couple of days ago Synopsys announced that they were acquiring Quotium’s product Seeker. This is an interactive application security testing (IAST) product. Synopsys are acquiring the product and the R&D team, not the whole of Quotium. The Seeker solution is a pioneering solution for IAST that helps businesses find high-risk security weaknesses while fostering collaboration between development and security teams. The Seeker solution exposes vulnerable code and ties it directly to business impact and exploitation scenarios, providing a clear explanation of risks.

It is just over a year since Synopsys first moved into the software quality and security space with their acquisition of Coverity. They recently renamed this group in Synopsys to be the software integrity group.

Subsequently they acquired Codenomicon, a Finnish company well-known and highly respected in the global software security world with a focus on software embedded in chips and devices. They are also famous for having independently discovered the infamous Heartbleed bug last year while improving a feature in their tools.

At one level you can argue that Synopsys’ EDA product line has very little to do with software security and quality. Even though some companies show up as customers for both product lines, typically the teams designing SoCs and the teams creating the software to run on them are separate. Not just separate engineers, but separate purchasing arrangements, separate environments, separate budgets. There are also lots of companies (think banks, for example) who create a lot of software but don’t do chip design at all.

Software quality and security is a growing market since software is getting into more and more life-critical and security-critical areas. If your smartphone crashes it is annoying. If your ABS braking system crashes then maybe you do too. And if your heart pacemaker crashes then no good will come of it.

On the security side you have to have been living under a log for the last couple of years not to realize how important security is. It is clear that security requires a multi-layered approach involving both hardware and software so those separate groups are perhaps not so separate. It still seems to be hard to get companies to invest heavily in security but the stakes are very high. Target’s well-known security breach cost it hundreds of millions of dollars. The penetration actually happened through an air-conditioning system, not the first place that springs to mind.

I think the really big possibility for Synopsys is not just that these are attractive fast-growing markets. I think that there is a real possibility of using some of the techniques that we use for semiconductor design to strengthen software design. Semiconductor design is very different from software of course, we don’t get to run more than one or two versions of a design through a fab/foundry since it costs millions of dollars to do so. But if you look at it from a risk point of view they are not so different. An undetected error in either case can have a huge business impact, much greater than the cost of doing the design in the first place.

Two areas that seem to offer a lot of synergy are:

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simulation and software testing are similar. You can never do enough, you can waste a lot of time if you don’t have a good test strategy, you never can be sure when you are done, you need to manage big farms and big suites of tests

formal techniques prove useful properties. For example, in the hardware world we can prove that nobody can access the encryption keys except in a special security mode. But that is just the sort of thing we want to do in software too, prove that it is impossible for a user to get kernel access to some security feature for example

There is no solid guarantee that these synergies will prove to be enough to drive Synopsys’ software integrity business to a much higher level than would happen if it was run completely independently. But as the cost of getting things wrong goes up, then the value of being as sure as possible that all problems have been found goes up too. The investment that companies will be prepared to make to ensure software integrity will go up too.