Mentor Graphics’ User2User conference will be held next week on April 21[SUP]st[/SUP] at the San Jose DoubleTree Hotel. This one-day, free conference is the perfect opportunity to learn, network, and share with other Mentor Graphics users.
The day starts off with back-to-back keynotes that examine different aspects of the hot topic of the Internet of Things. Wally Rhines Chairman & CEO, Mentor Graphics will address the pressing issue of Secure Silicon and how it is necessary to enable the Internet of Things. Karim Arabi, VP of Engineering, Qualcomm, will then explore the market trends and technologies driving the Internet of Things. Daniel Nenni recently discussed their keynotes here.
There’s a big new addition to User2User this year: the first-ever Emulation track, which includes an overview session from Mentor, and customer presentations from Altera, ARM, Marvell, and Soft Machines on their use of the Veloce Emulation platform. So if you’re a Veloce user, make sure you check out these sessions.
There is, of course, a free lunch at noon. You have the choice to also attend a special lunch session in the Silicon Test & Yield Analysis track. While you nourish your body, Broadcom presenter Kamlesh Pandey will feed your mind with his story of how they reduced ASIC test costs using Mentor’s new EDT test point insertion technology. Other Test presentations cover the use of IJTAG (IEEE 1687) at Cisco, finding memory failures at Broadcom, and what to do with failed EDT chain patterns at Microsoft.
I’ve written previously about IJTAG, a newly ratified standard for IP integration, access, and control that should be sweeping the nation any time now. I look forward to seeing how Cisco actually adopted and validated IJTAG and what benefits they saw.
The Broadcom presentation should be a big draw because in it, Amar Guettaf, the Technical Director of the Operations Group at Broadcom, talks about how to find the root cause of memory failures. He introduces a new bitmapping flow that apparently has dramatically simplified the MBIST bitmapping process and reduced the ATE development cycle. The last Test track presentation of the day is from Jeff Hung, Senior DFT engineer at Microsoft. He shares how they solved a situation in which scan patterns were working on ATE, but EDT chain patterns were consistently failing. All the Test track presentations are described here. Because the Test group at Mentor is full of really nice people who like to have fun, they are also offering some special prizes for their audience that you can win through a drawing.
After lunch, a panel of key executives from eSilicon, GLOBALFOUNDRIES, Mentor Graphics, TSMC, and STMicroelectronics will discuss “The Changing Foundry Landscape: Trends and Challenges.” Moderated by Semiwiki’s own Daniel Nenni, this panel of experts will discuss SoC trends, challenges, and new applications that will drive future generations of semiconductor design and manufacturing.
Along with the keynotes and industry panel, the day is packed with a full agenda of 9 major session tracks, led by top industry customers and Mentor’s top technologists. The tracks cover everything from AMS Verification (described eloquently by Dan Nenni in this blog), Calibre, Emulation, and IC Design Implementation, to PCB, Silicon Test Solutions, Thermal Simulation and Measurement and Verification.
Other activities in this full day include:
Interactive sessions let you give Mentor direct feedback on product improvements.
Mentor Technical staff will be available outside the session rooms to answer all of your questions.
This is your chance to network with your peers on future technology and strategy. See the snapshot to the right for an idea of what the happy hour is usually like after a Mentor U2U.