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How to Build an IoT Endpoint in Three Months

How to Build an IoT Endpoint in Three Months
by Tom Simon on 09-27-2015 at 7:00 am

It is often said that things go in big cycles. One example of this is the design and manufacturing products. People long ago used to build their own things. Think of villagers or settlers hundreds of years ago, if they needed something they would craft it themselves. Then came the industrial revolution and two things happened. One is that if you wanted something like furniture or tools you were better off buying them. The other was there was a loss of skills; people ‘forgot’ how to make things. This meant that the ability to create was concentrated in the hands of a few, and individuals had less control over what was available to them.

The maker movement has changed all that. The ability to design and build things has come full circle. Now if you want to design with 3D Printers and Arduino boards you can design a range of things, from simple everyday items to sophisticated appliances. In many ways the Internet of Things was started through this same pathway. People took low cost development systems and tools, added sensors, wireless and often servos to make a wide variety of useful things.

Semiconductor design has followed an analogous path. Early on design teams were small and they built chips that became the components of that era’s products. I remember calling on chip design companies in the late 90’s where it was literally three guys with a Sun workstation running layout software.

That era has ended and it seems that recently the only feasible way to design chips was at places like Nvidia, Intel, Freescale, Marvell, etc. They can apply design teams with hundreds of people to build their products. If you had an idea for a design and did not have the manpower, your idea went un-built.

However, things are changing again. The same market and technology forces that drove the maker movement, and pushed for standardization of building blocks, has spilled over into the internals of chip design. With the need for increased sophistication, the tools for building integrated platforms for IoT have been growing and maturing. We all know the formula by now: MCU, on board NVM, one or more radios, ultra low power, security, interfaces to sensors and a SW development environment to build user applications.

Differentiation is the key to success; product developers know they need to optimize their platform for their specific needs. ARM recently embarked on a project to test out the real world feasibility of having a small team build a custom IoT end point device in a fleeting 3 months. ARM used the TSMC Open Innovation Platform Forum in September to present their results.

ARM Engineering Director Tim Whitfield gave a comprehensive presentation on their experience. The challenge was to go from RTL to GDS in 3 months with 3 engineers. additionally, there were hard analog RF blocks that needed to be integrated. They went with the ARM mbedOS to make it easy to prototype. They also included standard interfaces like SPI and I2C for easy integration of external sensors.

ARM used their arsenal of building blocks which includes the Cortex M3, Artisan physical IP, mbedOS, Cordio BT4.2, ancillary security hardware and some TSMC IP as well. The radio was the most interesting part of the talk. A lot of things have to be done right to put a radio on the same die as digital. The Cordio radio is partitioned into a hard macro containing all the MS and RF circuitry. In the hard IP there is also real-time embedded firmware and an integrated power management unit (PMU) – critical for effective low power operation. It comes with a Verilog loop-back model for verification. The soft IP for the radio is AMBA-3 32-bit AHB compliant. It is interrupt driven and can operate in master & slave mode with fully asynchronous transmit and receive.

When adding the radio to the design, designers are given guidelines to avoid supply coupling in the bond wires. This is provided by adding 100pF decoupling per supply. They used CMOS process friendly MOM caps. They did receive some guidance from the radio team on how to prevent substrate coupling. They used a substrate guard ring with well-ties. Tim suggested that the guard ring could possibly be delivered as a macro in the future.

They discovered that if there was no cache that 80% of their power would be used for reading the flash and 20% used running application code. So they reduced the power overhead by using caching. Tim sees opportunity to further improve power performance with additional cache enhancements.

They already taped out in August, and are now waiting for silicon from TSMC in October. That, of course, will be the real test. Whatever lessons learned will be applied to improve the process for customers down the road.

This is certainly just a “little bit more” impressive than a maker getting their Arduino project working. Nonetheless, it is definitely a branch of the same tree. Enabling this kind of integration and customization democratizes product development and will in turn create new opportunities. I look forward to hearing how the first silicon performs.


5 uses of Bluetooth Smart Technology that you didn’t know!

5 uses of Bluetooth Smart Technology that you didn’t know!
by Daniel Nenni on 09-26-2015 at 7:00 am

Ever wondered why they named the most universal wireless technology Bluetooth? Apparently it was named after a 10[SUP]th[/SUP] century Danish King named Harald Blåtand whose nickname was Bluetooth because one of his teeth was blue. King Bluetooth’s claim to fame is that he helped peacefully unite Norway, Sweden, and Denmark. Since Bluetooth was created by Ericsson (a Swedish company) and it allows you to share voice, data, music, photos, and other warring factions amongst our mobile devices I get the naming convention, absolutely.

Bluetooth is awirelesstechnology standard for exchanging data over short distances (using short-wavelengthUHF radio wavesin theISM bandfrom 2.4 to 2.485 GHz[4]) from fixed and mobile devices, and buildingpersonal area networks(PANs). Invented by telecom vendorEricssonin 1994,[5] it was originally conceived as a wireless alternative toRS-232data cables. It can connect several devices, overcoming problems of synchronization (Bluetooth 101).

The latest version is called Bluetooth Smart which is an extension of the original Bluetooth brand focused on low power implementations. Think IoT and wearables where you want to go days, months, or even years on a single charge of a tiny battery.

Bluetooth Smart provides a very low power, low MIPs & low gate count platform for applications requiring Single Mode Bluetooth Low Energy (BLE), e.g. smartwatches, hearing aids, wearable sensors for medical /sports (heart rate, glucose, temperature), remote controls, toys, environment sensors, location beacons and many other machine–machine communications (CEVA RivieraWaves Bluetooth Platforms).

As you can imagine, Bluetooth Smart applications are exploding as are the presentations on Bluetooth. The latest and greatest one I have seen is from Dialog Semiconductor (they just acquired Atmel) presented on September 16[SUP]th,[/SUP] 2015 at Capital Markets Day in London. The presentation title is Personal Portable Connected and in 22 PDF pages it covers Bluetooth Smart: Market update, product update, and key takeaways.

*Spoiler alert* Here is the Bluetooth® Smart market size:

And here are the 5 uses of Bluetooth Smart Technology that you probably didn’t know compliments of CEVA:

1.) Nest Thermostat Gen 3 and Nest Protect Gen 2, the latest generation Thermostat and Protect devices from Nest both include Bluetooth Smart Connectivity in order to simplify maintenance and control of these devices to your smartphone:

2.) Salt Card, a a Keyless Entry Method for Smartphones. With the SALT card, which is in the shape of a credit card, users will no longer need to enter their pin or pass codes while within 10ft. of the card, as the device and card wirelessly sync thanks to Bluetooth Smart technology:

3.) Li-Ning Smart Trainers, Xiaomi’s smart trainers, designed by Sportswear brand Li Ning are available in China now. Bluetooth Smart chips are the solo of the trainer and send information to Xiaomi’s existing Mi Fit app on your smartphone, measure steps taken and calories:

Eizo ‘Foris’ Gaming Monitor, With the Bluetooth connectivity built into the monitor, gamers are able to use their mobile devices to adjust the colour, brightness, gamma and other settings, and to post a notification in the corner of the screen when a call or message arrives on their smartphone:

Olympus Air A01 Smartphone Lens, turns your smartphone into a mirrorless camera – uses Bluetooth to connect and control the lens directly from your iPhone or Android Smartphone:


Phablet Impact on PC Sales

Phablet Impact on PC Sales
by Daniel Payne on 09-25-2015 at 4:00 pm

Apple iPhone 6 and 6s users are recent converts to the latest growth trend in smart phones, large screens at 5.5″ in size and aiming even higher each year. I’ve owned a 5.5″ smart phone from Samsung for some 3 years now, so have immensely enjoyed the larger screen size to get my daily work done with: web browsing, LinkedIn reading, Google+ browsing, Tweeting, email, Facebook, messaging, writing notes, taking photos, sharing docs on Google Drive, etc. I’ve also owned two generations of the Apple iPad and that device allows me to attend an event like DAC and take notes all day long without having to charge the battery, typing away on the Logitech keyboard. I haven’t owned a desktop computer for about 10 years now, instead using a MacBook Pro laptop because of it’s portability and generous 17″ display.


Samsung Galaxy Note 4

The research company IC Insights just published an info-packed bulletin titled, “Large-Screen Smartphones Erode Total Personal Computing Unit Growth“. Starting in 2010 we saw tablet devices enter the market and drive new growth, and by 2013 the volume of tablets shipped was larger than notebooks. Something unexpected happened in 2014 because tablet growth slowed way down as the larger-sized smart phones became more popular. Take a look at the info-graphic for total personal computing unit growth from the year 2000 through 2018:

The trend in 2015 is that both PC and tablet IC sales are declining, with PC IC sales looking like a $57.7B market (-3%) from a $59.4B market in 2014 (+5%). IC sales for tablets could go down 5% this year to $16.6B. One segment seeing continued growth is ICs for Internet and cloud computing laptops like the Chromebook with an increase of 38% to $931M. Here’s the table showing the IC market for personal computing systems:

These numbers from IC Insights are confirmed by companies like Apple that have seen decreases in sales of the iPad and iPad Mini devices, so one way to counter that trend is to introduce new products like the larger iPad Pro with a 12.9″ display, available in November this year.


Apple iPad Pro

Apple was smart to add a keyboard and optional stylus for this device, as the keyboard makes this device a replacement for some notebooks and the stylus is great for graphic artists and anyone that loves handwriting or painting.

For the complete report, visit IC Insights.


Together At Last—Combining Netlist and Layout Data for Power-Aware Verification

Together At Last—Combining Netlist and Layout Data for Power-Aware Verification
by Beth Martin on 09-25-2015 at 12:00 pm

The market demanded that gadgets it loves become ever more conscious of their power consumption, and chip designers responded with an array of clever techniques to cut IC power use. Unsurprisingly, these new techniques added to the complexity of IC verification. When you’re verifying a design that has 100+ separate power domains, plus tightly packed digital and analog parts in the same substrate, proximity effects like noise, latchup, and parasitic effects require more than a basic on-off verification. Because the market also demands that these low-power devices actually work when you turn them on.

In most cases, traditional LVS methodology is simply not good enough to ensure circuit performance and reliability in these designs, because some design rule checks can’t be performed without adding layout features, and some errors are nearly impossible to debug.

I had a chance to talk to some of Mentor’s engineers who are developing ways to check these new design rules, such as deep n-well biasing, well implant, and extract parasitic effects for mixed-signal SOCs with multiple power domains, using a new approach and new algorithms. Sridhar Srinivasan is the technical lead for Calibre® PERC™, Frank Feng is a methodologist, and Yi-ting Lee is a foundry technical liaison. They presented a paper at the China Semiconductor Technology International Conference (CSTIC) about reliability verification, which you can read for yourself here.

Not surprisingly, power is a hard design problem to generalize. Even the “simplest” device, say, one with four power domains, has thousands of failure points. When you start increasing the number of domains, adding in use cases, varying voltages, etc., and trying to analyze how each power state affects the functionality of other parts that may be turning on or off themselves, it’s pretty easy to understand how power-aware verification gets really difficult really fast.

All three pointed out the need for verification tools that can combine and analyze the netlist and layout simultaneously both to understand power intent and identify a variety of power-related problems. In their work, the trio focuses on several proximity-related issues that can be power-domain-dependent:

  • Verifying parasitic junction diodes
  • Accuracy of deep n-well biasing voltages
  • Identification of devices with latchup risks
  • Situations leading to leakage current due to domain crossings

The rule checks that involve these proximity effects combine electrical rule checks and geometry-based DRC rule checks. To solve the verification challenge, they used a netlist-based infrastructure with a programmatic interface to the geometry database that was developed at Mentor Graphics. This technology is available as part of the Calibre® PERC™ product from Mentor Graphics. The inputs to the flow are a schematic netlist, and/or a GDSII/OASIS/LEFDEF layout, and a user-described rule set that includes power, ground, and IO setup. The setup includes the specification of the various power signals present in the system, specification of the known internal supplies, programmatic specification of derived internal supplies based on the circuit structure (like charge pump, level shifter, etc.), and design-dependent property propagation “stop” rules.

First, they said, the tool reads in the netlist representation of the design to construct the graph. Then the user-defined signal specifications are processed—the explicit signal definitions with net names are processed first, followed by the programmatic, structure-dependent specifications. All signal specifications are saved as properties and are propagated through the graph. Srinivasan says they included hierarchical APIs to control the propagation of these properties based on the design device types (PMOS, NMOS, RESISTANCE, etc.), including custom device types, and then let the user specify blocking conditions. After property propagation, the nets in the graph have the propagated data, and the user can then inspect the propagated properties and defined properties through a handy introspection API at each net.

With large and complex designs, runtime is an issue in every step of the flow, including verification. To reduce runtime, the properties can be collapsed. For example, instead of assigning unique properties to each power supply, you can group the power supplies by domains and voltage ranges and assign properties to each group. Srinivasan said that keeping the total number of properties below 64 provides a major performance advantage, as the properties can be encoded without the special data structure needed to create complex bit sets.

The trio performed reliability checks on real-world multiple-power-domain and mixed-signal designs using Calibre PERC in tandem with traditional LVS and DRC…If you’d like to learn more of the details, download the paper (free, but registration required).

As for the next phase? In the future, they said, the Calibre PERC tool will be able to handle device reduction, netlist transformation, and voltage transitions automatically with minimal user input, further improving usability. When it comes to the details, I’m not sure exactly what all that will mean, but I do know it signifies good things for designers struggling with complex power verification at advanced nodes.


A Brief History of FPGA Prototyping

A Brief History of FPGA Prototyping
by Paul McLellan on 09-25-2015 at 7:00 am

Verifying chip designs has always suffered from a two-pronged problem. The first problem is that actually building silicon is too expensive and too slow to use as a verification tool (when it happens, it is not a good thing and is called a “re-spin”). The second problem is that simulation is, and has always been, too slow.

When Xilinx and Altera produced field-programmable gate-arrays (FPGAs), which were reprogrammable, it didn’t take long for ASIC designers to realize that these could be a third prong to solve their verification problem. Much cheaper than building silicon but much faster than simulation.

There were no commercial solutions at first for FPGA prototyping. Everyone who wanted to do it had to buy FPGAs (or an FPGA-based board) and then cobble together a flow that worked. The biggest issue was probably that the types of designs for which this would be an interesting approach had more gates than the largest FPGAs, so the designs had to be partitioned. But partitioning a typical design meant that more signals needed to go between the various partitions then were actually available on the FPGAs, so the pins needed to be multiplexed. This is a problem that continually gets worse since, to a first approximation, the number of gates grows quadratically and the number of pins linearly meaning that there are thousands of gates per pin. So it was clearly not a straightforward approach, and it required a lot of knowledge about the design to get it ready, and a lot of knowledge about FPGAs and FPGA tool flows to actually get anything to work.

Like most things where lots of customers are making something difficult independently, some people saw an opportunity to create a commercial product to serve the whole market. I expect there were other companies lost in the mists of pre-internet days but one company survives from that era to the present day.

In 1987 Hardi Electronics was formed in Sweden. In 2000, they created an FPGA prototyping system called HAPS. As described by Hardi:HAPS is a modular, high performance and high capacity FPGA-based system for ASIC prototyping. HAPS comprises multi-FPGA motherboards and standard or custom-made daughter boards which can be combined in a wide variety of ways in order to quickly assemble ASIC prototyping systems. Rapid assembly is facilitated by the availability of many standard daughter boards including video processing, memory and interfaces to Ethernet, USB, PCI Express and ARM core modules. Customers prefer the time-to-market advantage of using an off-the-shelf prototyping solution, which can save months in the critical verification phase.

In 2007 Synplicity acquired Hardi Electronics for $24M. At the time, Synplicity was one of two companies that competed in the merchant FPGA synthesis market, competing with the free (or nearly free) solutions provided by the FPGA vendors, Mentor being the other. But Synplicity was not long as an independent company and Synopsys acquired them in 2008 for $227M. HAPS has been through several generations, the most recent of which, HAPS-80, was announced just last week.

In the meantime, Cadence also decided to create an FPGA prototyping solution. The first generation, imaginatively named Rapid Prototyping Platform, came out in 2011. By the second generation it had a real name. In 2014 Cadence announced their second generation of the product called Protium.

In 2003, another company, S2C, was founded in Silicon Valley to address the FPGA prototyping market. They have grown and have several hundred systems installed. Developing and manufacturing is in China and Taiwan respectively.

So that is the scene today. About half the market is still people putting together their own prototyping systems and there are three suppliers with off-the-shelf product portfolios: Synopsys, Cadence and S2C. All the solutions consist of two parts. There is a hardware component, which consists of the range of boards and connectors. And there is a software component which takes the design, partitions it, handles the multiplexed signal connectivity between the arrays, creates the bitstreams to program them, and provides access and visibility to debug the design.

FPGA prototyping can be used by chip designers to give them a way to run huge amounts of verification vectors, often including booting an operating system and bringing up drivers. It can also be used by software designers who need something on which to run their software before silicon is available. Even when silicon is available, the FPGA prototyping system often provides a better environment for debugging the code.


Samsung to cut Semi Capex 20% due to over capacity

Samsung to cut Semi Capex 20% due to over capacity
by Robert Maire on 09-24-2015 at 4:00 pm

Article confirms market fears…
An article in the Korea Times cites sources that say Samsung will cut Semi Capex by 20% due to current oversupply and weak pricing. This is obviously a huge negative as Capex for 2016 will certainly be down significantly from 2015 given these cuts which follow on cuts by Intel and others. We can only assume that Micron and SK Hynix will also cut spending on DRAM as they are also acting more rationally then they have in the past.

This will force further capitulation…
Semiconductor Bulls have been saying that 2016 capex is in good shape and that Samsung will keep Capex flat. Those analysts who have remained too bullish for too long are going to have to back pedal and capitulate and start to take numbers down.

How long a drop in spend???
We would expect that Samsungs spending cut will remain in effect throughout 2016 as it will take a while to sop up the excess capacity in the market. It is also clear that 3D NAND and foundry will not make up for the drop in DRAM spend as DRAM has been spending at a much higher than normal rate for a while now.

We have been very clear that this wouldn’t last forever and sooner or later things would come back to the industry’s normal cyclical behavior. We continue to maintain that while the cyclicality is not as severe it is still none the less a cyclical industry……though many in the industry have developed amnesia given the length of the upturn.

Micron & SK Hynix likely to follow…
With everybody in DRAM behaving better its logical to assume that both SK Hynix and Micron will also cut back their spend. We would assume that Micron, which is naturally a cheapskate when it comes to capex, will easily slow spending. We do expect an uptick in spending related to Xpoint memory but not likely to make up for a drop in DRAM. SK Hynix is not in the financial shape of Samsung and thus is less able to tilt against the winds of declining DRAM pricing and over supply.

Stocks will see further downside…
We had suggested a $60 downside to LRCX which has fallen off the proverbial cliff in the last week. Given the momentum it may push through $60 and all bets would then be off. This is a far cry from $80+ the stock had reached but you live by the sword of memory, you die by the sword of memory…….

A small cap stock that has high Samsung exposure is Mattson which could easily face another near death experience if Samsung cuts spending significantly as Mattson is a marginal supplier and less of a core supplier and thus on the edge. We had suggested a $2 downside and again, we could break though that as well.

KLAC is the least impacted…

Of the large semi equipment companies KLAC will be the least impacted as they have the lowest exposure to memory and higher exposure to logic and foundry which seems to be at or near a bottom. KLAC recently said that business had seemed to be at the high end of very lowered expectations.

We remain underweight the group…

We have been very clear that we were not at the bottom for the stocks and we are likely still not there yet but we are getting closer. Q3 reports could be one of the last nails in the coffin that puts the stocks on the bottom of their cyclical range in valuation. We don’t see a lot of support for the group or near term catalysts to turn things around. News flow will remain negative in the near term

Robert Maire
Semiconductor Advisors LLC


Electromigration Analysis and FinFET Self-Heating

Electromigration Analysis and FinFET Self-Heating
by Tom Dillinger on 09-24-2015 at 12:00 pm

FinFET processes provide power, performance, and area benefits over planar technologies. Yet, a vexing problem aggravated by FinFET’s is the greater local device current density, which translates to an increased concern for signal and power rail metal electromigration reliability failures. There is a critical secondary effect, as well – the thermal profile of the FinFET influences the temperature of the metal interconnect neighborhood, which accelerates the EM failure rate probability.

At the recent TSMC OIP symposium, Ansys/Apache provided exceptional insights into the issue, and how their toolset assists designers with EM analysis at advanced nodes.

The “Self-heating effect”
Self-heating refers to the thermal energy originating at a current-carrying element. The local temperature rise depends upon the thermal dissipation path(s) away from the element. The model for thermal conduction uses an electrical equivalent – heat flows through a “thermal resistance”, which is characteristic of the materials surrounding the source.

FinFET self-heating has unique thermal resistances from the device channel. Unlike planar (non-SOI) devices, the thermal path through the substrate is constrained by the poor thermal conductivity of the dielectric at the base of the fin. As a result, a significant percentage of the device self-heat energy flows vertically and laterally to the MEOL metallization, with a delta_T increase in the metals.

Note: FinFET self-heat dissipation also has an adverse impact on instrinsic device reliability mechanisms, such as bias temperature instability (BTI) and hot carrier injection (HCI). A subsequent article will review TSMC OIP presentations on FinFET “device aging” models and self-heat acceleration.

In addition to heat transfer from FinFET devices, there is a temperature increase in interconnects due to wire self-heating – namely, the resistive losses in the metal. There is also heat transfer from the resistive dissipation in neighboring interconnects.

The EM induced failure rates – i.e., the “mean time to fail” probability – due to the average current density in a metal wire is typically represented by Black’s equation:

(For more background on EM, please see the semiwiki article:
https://www.semiwiki.com/forum/content/1085-ic-custom-ip-blocks-electromigration-em-ir-drop-effects.html )

Note the exponential dependence on temperature in this model. The delta_T in a wire above the local die temperature due to heat transfer and resistive self-heating requires a sophisticated thermal resistance model and power dissipation analysis, which Ansys has developed and qualified with TSMC.

Ansys flow for enhanced EM analysis
Ansys is an industry leader in electromigration analysis (RedHawk, Totem), and in thermal modeling and analysis of the chip-package-system environment (RedHawk, Sentinel-TI, Icepak). The on-chip extraction features of this toolset have been enhanced to support multi-patterning decomposition “color aware” metal biasing of TSMC’s advanced FinFET nodes. To address the requirements for delta_T in electromigration analysis, new tool capabilities have been added, and a new flow qualified.

The key new feature is the characterization of the interconnect temperature to include the thermal sources mentioned earlier. Starting with the (tile-based) Chip Thermal Model without self-heat, a new solution for the interconnect temperature with device and wire self-heat contributions is derived using the chip-package thermal analysis tools.

There are a number of different methods used to determine an electromigration-based chip reliability estimate. The most direct approach is:

  • assume a max allowable increase in interconnect (or via) resistance over a product lifetime due to EM (e.g., x%)
  • measure the average current density on test wafers which results in that delta_R – this is an accelerated stress test applied to various interconnect structures
  • using Black’s equation, adjust the measured J_average current density limit from the stress test to the product environment

For example, when deriving the J_average limit, assume the MEOL wire temperature is equal to Tj_max plus a small delta_T due to the wire’s intrinsic J_rms self-heating – e.g., 105 degrees C. + 5 degrees delta. The J_average limit may actually be a set of tables using the interconnect width and length. Electromigration current density limits are a function of the metallurgy of the materials – e.g., metal grain size versus width – and are greatly reduced for short length segments (below the “Blech length”).

  • calculate the thermal resistances between devices and wires for the delta_T characterization
  • using the Ansys flow, calculate the detailed wire temperatures
  • if the wire J_average and temperature are below the process reliability limits, assume the interconnects do not contribute significantly to the reliability MTTF; else, highlight these as electromigration “hot spots” which need addressing

Ansys has enhanced their tools and flows to address a key reliability issue in FinFET technologies – the potential for significant delta_T on interconnects/vias due to thermal coupling, and the resulting acceleration of electromigration reliability failures.

This is a good example of the benefits of the “early” EDA vendor partnership with TSMC that Cliff Hou highlighted during his OIP keynote presentation.

-chipguy

Also read: Four Takeaways from the TSMC OIP 2015


SEMI SMC: Atoms Still Don’t Scale

SEMI SMC: Atoms Still Don’t Scale
by Paul McLellan on 09-24-2015 at 7:00 am

Last Tuesday was the SEMI’s annual Strategic Materials Conference (SMC). The opening keynotes were given by Gary Patton, the CTO of GlobalFoundries, and Mark Thirsk, Managing Partner of Linx Consulting. This year it was held in the Computer History Museum (which always makes the commute interesting since you have to fight with a zillion people going to the Googleplex along the same road).

Gary made something explicit that I sort of half-knew. Prior to 90nm, pretty much all the advances in semiconductor process came from scaling. Then we were down to gate oxide just 3 atoms thick and we needed to switch to materials and other sorts of innovation: strained silicon, High K metal gate, FinFET and more.


As we innovated in materials we spread our attention all over the periodic table, from a dozen elements in the 1980s (H, B, N, O, F, Al, P, Cl, Ar ,As ,Sb, and most of all Si) to about 60, half the table. Who even knew what Hafnium was before it became important in high K dielectrics?
There will be lots of innovation needed in devices in the future (gate-all-round, carbon nanotubes, III-V devices…) but there is a more urgent problem that our interconnect is running into the wall. The interconnect itself is protected by so many liners and caps that there is very little actual interconnect left and so the resistance is too high. There is lots of innovation going on in this area:

One materials challenge is that supply is often very concentrated in just one or two suppliers. For instance, one thing that several people commented on during SMC was availability of neon (Ne). The price has gone up 10X. It turns out that it all comes from eastern Ukraine, which you can’t have failed to notice is not the most stable part of the world right now. Plus, semiconductor just doesn’t move the needle that much. When we switched to copper interconnect the non-specialsit copper suppliers rubbed their hands with glee, before they discovered that annual consumption might be the same as the electrical wiring of a large building.

Mark pointed out that one result of this is that there is a lot of M&A (and spinouts of specialty divisions) in the materials industry. It is also important to remember that almost 3/4 of all 300mm capacity is in Asia (as of 2015). As a result there are also a large number of new suppliers entering in Asia, especially in China with its desire to become more self-sufficient in semiconductor manufacturing and the surrounding ecosystems. China is investing $160B over 10 years, with loans to supply-chain participants growing in importance.

So near-term trends that Mark and Gary both pointed out for devices and, especially, interconnect:

  • High-mobility channel InGaAs n-channel and Ge p-channel FinFETs
  • CVD Co improves Cu wetting and extends Cu gap fill (cobalt is a thin conformal layer that repairs discontinuities)
  • 5nm Ru:TaN liner followed by ECD copper (plated films have larger grain size)

But each of these conceals dozens of smaller innovations needed to make the simple-sounding one-sentence summary work in an high-volume fab. For example, cobalt in the metalization requires materials and chemicals from a number of different specialized suppliers:

  • PVD targets
  • CVD precursors
  • Electro/electroless plating chemistries
  • CMP slurries for Co
  • Co recess processes – Dry/Wet chemistry approaches
  • Co compatible cleans (wets)

In summary, here is a couple of decades of material innovation, and the future innovation that is being developed, summarized in a single diagram:

But looming ahead is perhaps the biggest barrier of all. We are atomic level deposition and processes. But atoms still don’t scale. That is something no amount of innovation is going to change.


Why Sidense OTP is Like the Armored Car of NVM

Why Sidense OTP is Like the Armored Car of NVM
by Tom Simon on 09-23-2015 at 4:00 pm

I have written about Sidense before, but last week at the TSMC Open Innovation Platform Forum, I had a chance to hear a talk by, and have lunch with Betina Hold Director of R&D at Sidense. Here is what I learned.

Sidense has been focusing on the growing market in what they like to call the smart connected universe. It is best to think of this as the union of mobile, IoT, wearables, medical, industrial and automotive. Incidentally Automotive was a hot topic at the OIP Forum.

However, getting back to our main topic, all of these applications have a need for non-volatile memory (NVM). In many cases the need is for secure and reliable storage for device ID’s, security codes, trim information and a variety of other write-few, read-many pieces of data. This can even extend to boot code.

This is a perfect application for one time programmable(OTP) NVM. Even if you need to make multiple writes, the NVM controller or system firmware can make it look like “few times programmable” (FTP) memory. OTP-NVM has several distinct advantages that make it a clear choice for chip design. The most obvious is that it requires no special masks nor any changes to the process at all. The Sidense 1-T solution uses the process and PDK designers are already using for their circuits.

Sidense has working silicon from 180nm down to 16 Fin FET. During her talk, Betina pointed out that the underlying OTP-NVP technology they use has actually improved with FinFET devices. They are seeing 100,000X difference between the read currents in 0 and 1 states with 16nm. Sidense is seeing that the leakage current in Fin FET devices has improved >10X relative to 28nm.

Sidense has been very successful at reducing the power requirements for its OTP. Typically, only the chip’s VDD is needed and no external or higher voltage supplies are required. The high read margins help reduce the power needs. Sidense also offers interfaces for sub-threshold operating voltages that are being targeted in new processes. This will further help reduce operating power.

The thing that Betina spoke about most passionately was how Sidense OTP NVM addresses security. She pointed out that their CTO Wlodek Kurjanowicz came from Chipworks, where he became very familiar with techniques used to reverse engineer circuits. Sidense works hard to ensure that data stored on their NVM-OTP cannot be hacked or compromised.

Hackers will go to great lengths to reverse engineer or even attempt to alter stored data and code. Sidense OTP NVM uses fully differential data storage, with complementary logic and bit cell structures to avoid any power signatures based on read values. Also, there are built in protections against tampering with clocks, operational voltage and even hacking attempts through lowering temperature.

The bit cells are also difficult to physically reverse engineer. There is no discernible physical difference between a 1 and a 0. Additionally, the hard IP routing for the OTP-NVM is designed to inhibit access if some of the metal is removed. All of this is very important because gaining physical access to connected devices that may have the ability to threaten larger secure systems is easier than ever. No longer can security depend on keeping hackers away from physical systems.

Even though I am very familiar with NVM-OTP, I learned a lot about the advantages of using them and how Sidense endeavors to ensure an extra level of security. For more information about Sidense, follow this link.


Krivi Specialty I/O Library Support UMC 28nm

Krivi Specialty I/O Library Support UMC 28nm
by Eric Esteve on 09-23-2015 at 12:00 pm

There is an industry consensus about 28nm, the technology node is here to stay, and to stay for very long. If we except 20nm node, which by opposition will have a very short lifetime, 28nm is the last node following the economic part of Moore’s law: designing on smaller technology allows building cheaper IC when you integrate the same functions, or to integrate two fold more gates at the same price. If a chip maker has deep enough pocket to afford huge development cost (R&D cost in the $80 to $100 million) he can target 16FF or even 10FF, the resulting IC will be faster and lower power but not necessarily cheaper than on 28nm, as we can see on below picture.

For a vast majority of the semiconductor industry targeting 28nm and above nodes it’s a very good news to know that the 28nm offer will be as large as possible, including UMC on top of TSMC and GlobalFoundries (Samsung focusing on a few customers asking for very large production volume). In this context, it’s important for potential UMC customer to rely on an offer as complete as possible, including specialty I/O pads. Krivi has announced the validation of IO pad library platform at UMC 28nm technology.

This IO platform supports wide variety of interface standards such as DDR, LVDS, and Memory card super combo IO libraries. We often write about SuperSpeed USB, PCI Express 3.0 or HDMI 2.0, these SerDes based protocol standards, essential to design SoC for consumer, networking or PC peripheral application. But to design a SoC you will also need to integrate these specialties I/Os and you expect these IO libraries to be proven in test silicon for their compliance to respective electrical standards, ESD and latch-up performance. Your boss may accept that the first release of the 16G PCIe 4.0 PHY fail to be 100% at spec… but certainly not if you SoC prototype don’t work due to a failing LVDS I/O.

According with Sivaramakrishnan Subramanian, Co-founder and Senior Principal engineer at Krivi: “Our specialty IO platform gives great flexibility to SoC and IP companies using UMC 28nm technologies to pick off-the-shelf IO pads that match or exceed best power, performance and area in industry”. If you don’t know Krivi Semiconductor, you most probably know ARM Ltd. The team in charge of the DDR3 PHY design within ARM has spin off to create Krivi in 2013. The same team has designed a specialty I/O platform supporting:

  • Universal DDR IO pad library supports all popular DDR standards like DDR4, DDR3/3U/3L, LPDDR3, LPDDR2, HSTL class-I and RLDRAM-3 etc. This library works at a maximum speed of 2.667Gbps in HLP process technology and boasts of having industry’s smallest foot-print. This library is designed with an aggressive power target of receiving data at 1mW/Gbps.
  • LVDS and Sub-LVDS combo IO library have data input and output cells along with an in-built Bandgap voltage reference cell for biasing. This IO pad meets TIA/EIA-644-A and SMIA 1.0 Part 2: CCP2 Sub-LVDS standards while working at top speed of 2Gbps and 1.6Gbps respectively.
  • Memory card I/O pad supports interface signaling ranging from 1.2V to 3.3V while using 1.8V gate oxide IO devices. This bi-directional I/O pad supports eMMC and UHS-I SD card standards.
  • SLVS, SubLVDS and SD UHS-II combo IO pad library is designed to meet JESD8-13, SMIA 1.0 Part 2: CCP2, and UHS-II SD card association standards with a top speed of 1.56Gbps.

Large semi or IP companies have moved IP design resources to India in early 2000’s and we can clearly identify start-up issued from these chip or IP makers, especially in the mixed-signal area, like Cosmic Circuits (acquired by Cadence in 2012), Silabtech (spin-off of OMAP PHY design team from TI) or Krivi, in charge of DDRn PHY IP with ARM. These design teams have the same level of experience and excellence than their counterpart working with the well-known IP vendors, and UMC choice make sense, according with Shih-Chin Lin:

“UMC has built a strong library, IP and design support environment for customers designing into our high volume production 28nm technology,” said Shih-Chin Lin, senior director of UMC’s IP & Design Support division at UMC. “With the addition of the IO Alcor platform from Krivi, our mutual customers now have access to a valuable resource that will allow them to seamlessly integrate a wide variety of high speed memory IO into their SoC design.”