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Can the Likes of iPhone 6s Bring New Disruptions?

Can the Likes of iPhone 6s Bring New Disruptions?
by Pawan Fangaria on 09-30-2015 at 12:00 pm

In more than 30 years of semiconductors, we have seen many technology-induced disruptions in our ecosystem, be it healthcare, consumer, mobile, aerospace, or any other field for that matter. To name a few are portable healthcare devices at much lower prices, video conferencing over internet that reduced the need of physical travel, smartphones that have made many businesses much efficient, and so on. One thing is for sure, all these developments have happened because of newer and newer semiconductor technologies being infused in the equipment that are core to these applications.

Applehad a record breaking sale of more than 13 million iPhone 6s and 6s Plus in the first 3 days of their availability, not without reason. Of course Apple has a ‘built over the years’ fan club, but the key ingredient in iPhone 6s and 6s Plus is a bunch of new technologies including 3D Touch, camera with 4K video recording, unique storage solution, low power and high performance CPU and GPU powered by FinFET technology from TSMC 16nmand Samsung 14nm, and so on. I will talk more about these later in the context where such technologies vis-à-vis iPhone can disrupt some of the established markets; I’m already seeing one very good possibility.

A couple of months ago I was reviewing a comedy movie ‘Tangerine’ which was shot completely using an iPhone 5. It’s a nicely shot commercial movie with wide screen, saturated colors, intimately woven, level of details, etc. all at a meagre budget of slightly above a hundred thousand dollars. I just grabbed a scene from this cinematic movie to put it into context here.

Look at the clarity and quality of the picture, and the level of details captured! The writer and director of ‘Tangerine’, Sean Baker filmed this movie entirely using iPhone 5 in the vicinity of Hollywood at Los Angeles encompassing the magnificence of the city. The iPhone lens was fitted over with an adapter from Moondog Labsto achieve the kind of cinematic feel we see in this movie. The iPhone also had inexpensive app from Filmic Pro that helped in controlling focus, exposure, white balance, and so on. Well it’s not only for low-budget that iPhone was used but also for better quality, ease of setup and handling, familiarity with iPhone, and so on. Baker was frustrated with standard-definition videos normally used in low-budget films.

So, what’s the key here? Definitely camera quality and other technologies related to camera. But it’s more than that, the video recording, image processing, graphics, and not to mention performance and latency in capturing all activities. Imagine Baker wants to make an animated movie, or a movie with high graphic content and gaming. The GPU along with CPU is equally important.

This is where I see iPhone 6s and 6s Plus much advanced in supporting more of such filming in the movie making industry. It provides 4K video recording, the best-in-class high performance low latency storage solution, FinFET enabled GPU for high performance graphics processing and gaming at much lower power, and higher CPU performance to assist the high performance GPU in validating the right API calls for setting up the frames. Does that sound like these phones can be used in the main stream movie production? Let’s park this thought here and see some of the initial performance benchmarks AnandTech has performed on the iPhone 6s and 6s Plus.

The storage controller uses a hybrid SLC/TLC NAND solution where any write goes through a large SLC cache before being committed to TLC NAND. There are many other benchmarks including games, graphics processing, and battery life which can be seen at AnandTech website here. Clearly iPhone 6s and 6s Plus stand apart from the rest. It’s the power of FinFET, newer NAND, state-of-the-art storage controller and other semiconductor technologies that have enabled such developments; of course Apple has mastery in hardware as well as software.

Coming back to the kind of disruptions we can see in the film industry and elsewhere. I checked Moondog and Filmic are already organizing contests for movie making by using their inexpensive app and other technologies along with iPhones. Imagine these kinds of contests evolving into a commercial movie contest across the world, something like an “Oscar on iPhone” :). Definitely, other than USA, there are many regions on the Globe which needs awareness about such low-budget good-quality move making option. More awareness can bring disruption in movie making industry bringing up hidden talent in acting. The talent will not have to wait to enter Hollywood or Bollywood to show it on the screen. Moreover, Bollywood movies in India can be targeted to be developed on low-budget using iPhones, absolutely. Use the money needed elsewhere!

Are there any other thoughts on disruptions which can be brought up by such cutting-edge semiconductor technologies? Expert Drones?

Pawan Kumar Fangaria
Founder & President at www.fangarias.com


Samsung Device Solutions Has a New Home

Samsung Device Solutions Has a New Home
by Paul McLellan on 09-30-2015 at 7:00 am

Last week it was the formal opening of Samsung’s new office building in North San Jose. They have brought together all of semiconductor device solutions in a huge new office building. The building can hold 2000 people. Samsung Device Solutions consists of:

  • memory
  • system LSI
  • LED
  • display

Dr OH Kwan, the CEO of Samsung Electronics, gave some of the history. Samsung first came to Silicon Valley in 1983 over 30 years ago. Just to put the technology of that era into perspective, the state-of-the-art was an IBM PC-XT with 128K of DRAM (yes, kilobytes) and a 10MB disk drive. I believe it was the first personal computer that came with a hard disk, not just floppy drives. The cost was $5,000, about 10 times the cost of one of the Samsung Galaxies that seemed to be everywhere, and nowhere near the power or capacity.

The new building is ten stories high with 1.1 million square feet. It is shaped with a large atrium open to the sky and even a couple of the levels are designed to allow employees to be outside. There is even a putting green. Somehow Samsung had arranged for perfect weather. The building is mirrored and the bright blue sky and the white clouds made for a photogenic scene.

The building was constructed in just two years. There was Mike Rossi a special adviser to Governor Jerry Brown, and not just the current mayor of San Jose, Sam Ricardo, but the previous mayor, Chuck Reed, on whose watch the building was started. I was pleased that the politicians resisted the temptation to talk at excessive length. Finally, there was a performance by the dance/music group Eclipse.

Following that, the Samsung employees went off to the cafeteria, which is in a separate building, and the press was divided into groups and given a tour of the building. Our tour guide was Kelvin Low, who runs foundry marketing. He moved into the building a couple of weeks ago and can just about find his way around the building now. His office is on the top (10th) floor and since it is the highest building anywhere near the views are dramatic in all directions.

We got a quick tour of some of the engineering areas. The previous week at the flash memory summit Samsung had just announced a 16TB solid-state disk drive, the world’s largest. The progress since Samsung arrived here when 10MB was the state of the art is amazing, an increase in capacity of over a million times and probably around the same price. Isn’t Moore’s Law wonderful, I’m not quite sure how the world is going to look now that it is slowing down or stopping, and we won’t ever get a million-fold increase for the same price.

One of the advantages of having a single large office building is that accidental meetings are much more likely to happen than when spread around a multi-building campus. The interior of the building has also been designed to make such fortuitous meetings still more likely, with various open areas, coffee rooms, a gym, the two levels open to the outside and so on.

In other Samsung news, that took a bit of the shine of the new building, there were reports that Samsung were cutting capex by 20% due to overcapacity. This is not entirely unexpected since Samsung is the biggest DRAM supplier which is often a sort of canary in the coalmine, signaling weakness early.


Semiconductor Inventories Under Control

Semiconductor Inventories Under Control
by Bill Jewell on 09-29-2015 at 7:00 pm

The semiconductor market is currently in a slow growth period. After 10% growth in 2014, the market is expected to only show low single-digit growth in 2015. Our own forecast at Semiconductor Intelligence is 1.5%. In several previous market slowdowns, inventories in the channel have climbed as some companies were slow to adjust their inventories to match lower demand levels.

The chart below shows total inventory as a percentage of quarterly revenue for five of the top six semiconductor companies. Samsung is not included since it does not disclose inventory data for its semiconductor business. Most of the companies show no significant change in the inventory ratio over the last six quarters. The exceptions are Intel and Qualcomm. Intel’s ratio went from 29% in 2Q 2014 to 37% in 2Q 2015. This is primarily due to lower revenues, with Intel’s 2Q 2015 revenue down 5% from a year ago. Qualcomm’s ratio climbed from 24% in 2Q 2014 to 41% in 2Q 2015. Qualcomm’s 2Q 2015 IC revenue was down 22% from a year ago due to increased competition for its smartphone chipsets.


Are inventories at electronics companies getting out of alignment with revenues? The chart below illustrates total inventories as a percentage of quarterly revenues for key electronics companies. The companies are six of the top eight purchasers of semiconductors, according to Gartner. The other two are Dell, which is now private, and Huawei, which does not disclose inventory data. The inventory to revenue ratio varies significantly from company to company, with Apple averaging about 4% and Sony ranging from 30% to 50%. These differences are due to factors such as number of product lines (relatively few for Apple, numerous for Sony) and supply chain strategy. Some companies (such as Sony, Samsung and Lenovo) tend to build inventory in the third quarter in anticipation of stronger fourth quarter sales. None of the companies show any significant change in their inventory ratio for 2Q 2015 compared to a year ago.

The links in the semiconductor supply chain which usually show the largest variation in inventories are distributors and electronic manufacturing services (EMS). The chart below displays the ratio of total inventories to quarterly revenues over the last fifteen years for major distributors and EMS companies. The two largest semiconductor distributors, Avnet and Arrow Electronics, are used for the distributor ratio. Each company has over $20 billion in annual revenues. The EMS companies are Jabil, Sanmina, Flextronics and Celestica. Hon Hai (Foxconn) is the largest EMS company, but it does not disclose inventory data for its EMS business.


When the Internet bubble burst in 2001 the semiconductor market plunged 32%, following strong 37% growth in 2000. Distributors’ inventory ratio peaked at over 80% from the low 60% range in 1999. The distributors did not reduce their inventories quickly enough to match the decline in revenues. Since 2001, the distributors have done a better job of managing inventories. For the last eight years their inventory ratio has held at close to 40%.

The EMS companies were caught by surprise by the semiconductor downturn. Most of these companies did not become significant factors in electronics manufacturing until the 1990s and did not experience the previous double-digit semiconductor market downturn in 1985. Their combined inventory ratio ballooned to over 70% from below 50% in 1999. Flextronics, the largest EMS company at the time, saw its ratio double from 44% in 2Q 1999 to 87% in 1Q 2001. The EMS companies reduced the ratio to 39% in 4Q 2004. As the semiconductor market slowed from 28% growth in 2004 to single digit growth in 2005 to 2007, the ratio jumped to 55% in 1Q 2007. Since 2007 the ratio has been fairly steady, even through the 2008-2009 semiconductor downturn. In the last few years the ratio has risen slightly from about 50% in 2011 to 57% in 2Q 2015. This latest increase in the ratio is likely due to deliberate plans to run higher levels of inventory following conservative inventory levels in 2010 and 2011.

Semiconductor inventories appear to be under control throughout the semiconductor device supply chain. Thus companies are making adjustments for the slowdown in the semiconductor market. Companies walk a fine line between carrying too much inventory – which can become a major burden when demand falls off – and too little inventory – which can lead to missed sales when the market is growing. The improved inventory management is largely due to better inventory management systems and better communications between semiconductor suppliers and the buyers of their products: electronics companies, EMS companies and distributors.


Indian Railways and SoCs

Indian Railways and SoCs
by Sivakumar P R on 09-29-2015 at 4:00 pm

Last week I woke up late as usual and decided to flip through the news paper on Coffee to enjoy the lazy Sunday morning, but I ended up reading a sad news about a train accident. Everyday virtually we hear about minimum one accident. Indian Railways, wow, what a reliable transportation system we have built. It clearly indicates we have to learn how to plan meticulously before jumping into execution.

I was not really surprised when Harry Foster at DVCon mentioned “Average number of Chip respins in India is more than any other countries, though we are the best in adopting latest verification methodologies”. In my imagination, Indian railways which has been built over the legacy British railways system reflects the structure and complexity of an SoC which is built using legacy chips and IPs. Although our SoCs don’t crash like our Indian railways, still we need to improve our project planning and execution to achieve First-Time-Pass.

‘First Time Silicon Pass’ pretty much depends on how you plan the whole project execution, especially the RTL verification. So as a verification consultant I would like to explain the project planning from a verification perspective.

Team – Are they skilled enough to do their job?
Build the team with right resources and train them on the technologies and methodologies which are relevant to the project. Also implement a process to identify their readiness with respect to spec understanding and skills. Everyone doesn’t need to know everything. Experienced engineers will implement TB infrastructure and mid level engineers will write only Testcases and coverage models and junior engineers will monitor and automate the regression. For example mid level and junior engineers must be skilled enough to use EDA tools to debug the simulation failures.

Project manager/TB Architect – Have they understood the methodology properly and perfected their approach?
In my consultancy experience what I have identified is that most of the project managers are traditional verification folks who have limited understanding of latest methodologies like constrained random verification. So they end up mixing traditional approaches with latest methodologies. I have seen them using UVM/OVM with traditional test plans. There is a huge difference between test plan and Vplan. In UVM/OVM, we do not think about test cases while creating the Vplan. Similarly sometimes experienced verification engineers who are new to SystemVerilog end up writing lot of directed test cases by narrowing the constraint range to specific conditions.

TB Architect – Has he considered his customer?
Architect the test bench infrastructure in such a way that it can be reusable with any technology at any level [IP/Chip/SoC verification on Simulation/Formal/Emulation]. Also your VIP should be able to accommodate the spec and design changes at any time in the future. Always try to simplify the user interface, aiming towards making your VIP as a push button type [ON & OFF] verification component. Write necessary scripts to automate the regression and report generation.

Finally I would say, ‘Make it simple’. That’s what your customer wants. He does not want to go through thousand pages of your user manual just to understand how to use your VIP. Most importantly, he doesn’t want to miss the tape out debugging and fixing your VIP functional bugs. So you need to be creative enough to invent a methodology/flow too to verify your VIP, as a competent Project Manager.


EUV – So late to the party it may already be over!

EUV – So late to the party it may already be over!
by Robert Maire on 09-29-2015 at 12:00 pm

Stocks in the semiconductor equipment space continue to fall only this time along with the broad market. We had recently pointed out that LRCX was the last to fall among the large cap companies in the space but now the question becomes when have they fallen enough to say its over, and which stocks have more to fall……

ASML stock always at a premium…
We have always had an issue with the apparent premium that the stock of ASML trades at. Although it clearly deserves a premium due to its margins and market dominance the premium it commands versus its US peers was well beyond just those factors. It seem obvious that there is clearly a “scarcity” premium of European investors looking for large cap technology companies that keep ASML at a much higher than industry average due to a lot of money chasing too few stocks with few alternatives. As alternative European technology companies such as Nokia and Ericsson have fallen so has ASML gained. We see a similar issue propelling some Asian technology companies to well above US equivalent valuations, such as Hermes. (US semi equipment company management has always had a bit of P/E envy over this valuation differential….)

How Much of a Premium?Not worth a Double…
ASML seems to command more than double the valuation of similarly situated US companies such as AMAT, LRCX & KLAC. ASML trades at a forward P/E of about 18 versus 9 for LRCX, 10.5 for AMAT and 11.7 for KLAC. On a price to trailing twelve months sales ASML trades at 5.3 versus 1.9 for LRCX, 1.8 for AMAT and 2.7 for KLAC. Obviously all these ratios will change as earnings are likely to drop for everyone in the industry along with a slowing of revenue as the downturn takes hold.

ASML has the potential to fall further than US counterparts…
Even if we presume a deserved quality premium versus US counterparts and a European stock premium there is still likely excess air in the valuation of ASML shares that could come out if we continue to see a capitulation of the sector and compression of valuations. At this point one could argue that European stocks deserve a discount rather than a premium.

A Pair trade with the US?
If I were a US shareholder the obvious question is why should I continue to hold ASML at such lofty valuations when I can buy similar US companies at half the price. I could further argue that a pair trade short ASML and long a US counterpart might not be such a bad way to hedge the market in the near term volatility given the valuation differential.

ASML fundamentals no better than anyone else… maybe worse?
There hasn’t been a whole lot of news in a relatively long time about the progress of EUV. The last thing we heard was an alleged 15 unit order over the span of several years purported to be from Intel. But that was before Intel stretched out its technology cadence from 2 years to 3 years and has continued to lower its capex, so the true value of that order is likely a lot less than the initial investor reaction.

Nor have we heard about anyone about to put EUV into production or production throughput getting to high volume manufacturing levels. In fact we continue to hear a “buzz” in the industry that other chipmakers, in addition to Intel, have process flows for 7nm that work just fine without EUV barring some major breakthrough we could very well see 7nm start out without EUV (or very much of it). ASML’s expectation that they will get some process steps or get in on the end of 10nm is starting to feel shaky.

The near term memory spending concerns at chip makers such as Samsung certainly impact ASML at least as much as its US counterparts. These concerns continue to echo in the stocks. ASML has significant exposure here in its current scanner offerings.

Memory may never go EUV…
Given that current memory technology line widths are well behind logic and foundry we would be hard pressed to find a memory maker that has EUV anywhere in its plans in the near term let alone long term plans. Given the spending patterns this suggests that EUV is shut out of at least half the market spenders.

So where is the EUV upside?

EUV is a very, very daunting task and we admire that ASML has continued to stick with it but you have to wonder. EUV has been in the works for such a long time, it goes all the way back to Bell Labs (remember them??) The question is will there be a payback??

Back in 2001 when the industry was running .25 micron (250nm for you newbies…) and Intel just announced .13 micron plans it was thought that EUV would start at about .07 micron (70nm) and perhaps EUV could be pushed as far as .03 micron (30nm) and if we were really lucky perhaps even stretched to .007 micron (7nm).

Fast forward almost 15 years and here we are wondering if EUV will even get introduced for the 7nm node….
The reality is there likely aren’t all that many nodes left in the semiconductor technology path after 7nm to try to recover the huge expense of developing EUV before we likely move on to some new non traditional technology to try continue Moore’s Law which may or may not require the same litho tools.
In the end , EUV could still be a losing bet even after the industry has doubled down several times…..

The figure above is a copy of the original Wall Street Journal article from 2001 about the advent of EUV. We found this ancient yellowed copy in our archives. (Yes, I am a pack rat who has files going back to our involvement in the IPO of ASML 20 years ago in 1995). Here is a link to a more legible copy of the article: Wall Street Journal 2001 EUV article

We dug the article up when we read this past weekends article in the Sunday NY Times about Moore’s Law slowing which also talked about lithography issues:Sunday 9/27 NY Times article about lithography & Moore’s Law slowing

Robert Maire
Semiconductor Advisors LLC


The Rosetta Stone of…Actually, the Real One

The Rosetta Stone of…Actually, the Real One
by Paul McLellan on 09-29-2015 at 7:00 am

Last week I wrote about the British Museum Algorithm in the context of simulation corners for variability. You walk everywhere. And if you don’t walk to just the right place, you miss something. Just like visiting the British Museum. Today I’m going totally off-topic to talk about something that really is in the British Museum, namely the Rosetta Stone. You are unlikely to miss it since there will almost certainly be dozens of Chinese and Japanese tourists crowding around it (you can see some of them reflected in the glass in my picture below). It is the most visited object in the whole museum. If you go in the main entrance to the museum, the Rosetta Stone is in the Egyptian Sculpture gallery to the left, the first thing you come to through the door.

I think that it is one of the more interesting artifacts in the museum. These days even Google thinks that the Rosetta Stone is a company that supplies language learning and the real Rosetta Stone has to content itself with second place in its search listings.

There is a reason that the language learning is named after the Rosetta Stone and also a reason that the phrase is used for something that is the essential key to a topic. The stone is apparently made of granidiorite (I’d never heard of it either) and it is carved with a decree from 196BC. What made it unique, at least when it was first discovered, was that it had the decree in three different languages: Egyptian hieroglyphics (not then deciphered), Demotic script (another script that was indecipherable at the time), and Ancient Greek. The stone is damaged and incomplete, so lots of the texts, especially the hieroglyphics at the top, are missing.

Ancient greek was well-known but Egyptian hieroglyphics were not really understood. The Rosetta Stone, with essentially a long hieroglyphic passage with an accompanying Greek translation, suddenly made a lot clear. I say suddenly, but it actually took more like 20 years before hieroglyphics started to be decoded.

The stone was presumably displayed in a temple but was then used as building material in a fort in Rashid/Rosetta. It was discovered there during the Napoleonic expedition to Egypt in 1799. But the French didn’t get to keep it for long since they were defeated by the British in 1801. It was taken to the British Museum (nobody really knows quite how) and has been on display there since 1802, except during the world wars to keep it safe from bombing.

There have been demands for the return of the Rosetta Stone to Egypt. I think that was most unlikely to happen anyway (the Elgin Marbles have been demanded by Greece for much longer), but given what has just happened to the buildings in Palmyra it is clear it will remain in London, probably forever.

If you are feeling you need more of a connection between this blog and the semiconductor industry, then see also The Rosetta Stone of Lithography.

The British Museum is on Great Russell Street in London. It is not that easy to find since it is midway between several tube (subway) stations and not straight along a street from any of them: Tottenham Court Road, Holborn (pronounced hoe-burn), Goodge Street and Russell Square. An additional wrinkle is that the Central Line (red) part of Tottenham Court Road station is closed until the end of the year to build the connection to CrossRail and trains don’t stop there. British Museum website is here.

And if you are not museumed-out after the British Museum, don’t miss nearby Sir John Soane’s Museum at 13 Lincoln’s Inn Fields. It is as small and quirky as the British Museum is large and comprehensive. The museum website is here.

Semiwiki: we visit the world’s museums so you don’t have to. Actually, the British Museum should be on your bucket list, so you do have to.


3 Essential Rules for IoT Businesses

3 Essential Rules for IoT Businesses
by Rushi Gajjar on 09-28-2015 at 4:00 pm

There are multiple opinions on from different sources which make the world so obsessed with the IoT. But really, Internet of things is far bigger than anyone realizes. Some people tell that it’s the term given to the connected things and it’s just about providing IPv6 to any “thing” that is available in the vicinity.

“Total Number of internet connected devices reached 8.7 billion in 2012” – X source

“The growing network of connected objects referred to as the “Internet of Things” is estimated to be in the billions by 2020.” – Y Source

“The Internet of Things (IoT) is one of the fastest growing areas of tech – covering everything from consumer wearable devices to high-tech industrial systems.” – Z Source

“IoT is completely a disruptive technology according to analysis.” – Z’ Source

Be it the massive infrastructures, be it your pillow, be it your home, or be it your clothes, it’s not about connecting the sensor to the multiple Arduinos and RaspberryPis and connecting it to the internet, It’s about building the ecosystem. It’s not about connecting relay to the Internet to control the appliances, but It’s about the intelligent architecture that very well suits the need of the users, may it be using artificial neural networks or may it be using the multiple algorithms for enhancing the user experience. Honchos are building the Skytranand that is the kind of solutions the world really wants. “Air” is built with the same vision and philosophy. We are here to deliver the extra mile!

When developers are talking about delivering an extra mile to enhance the human living experience, they’re still not thinking big enough to justify the needs of the world. It’s not a lack of creativity; it’s a lack of scrutiny. Future is always within our vision, and you don’t need to visualize or build what’s already there.

“A solitary fantasy can transform a million realities” – Maya Angelou


3 essential rules for IoT Businesses

Here is my take! There may be many rules for the successful IoT business, but I would like to encompass these three as the essentials to build the successful IoT product. It’s about M2M and IoT (It took me long to understand difference between M2M and IoT, and if you don’t know, Here is a good article) therefore it’s all on us, to understand where it’s leading to.

Rule 1: Data

It’s just not about delivering the product, It’s about leveraging the data which is created from millions of end nodes. Obviously, we would require powerful data storage capability and tremendous remote processing power to understand the sheer amount of collected data and to build the intelligence in the system for better predictions and controls.

Rule 2: Security and Robustness
Who likes it when connectivity becomes unstable? Nobody enjoys the interrupted signals and improper codecs. Thus the connection protocol aspect of IoT is incredibly critical to give users that seamless, “always on and interacting” feel — what’s the point of always having technology with you if it isn’t going to be always connected? Consumer devices in particular – from fitness trackers to home appliances – are generating more granular information. And when that information is about people or their health, it’s more sensitive.

Rule 3: User Interface/Experience
Similar to the previous point, nobody enjoys the broken user experience. Be it developers or the product end users, they need a flawless system to hack and play around with minimal hassles.
“IoT is not the ‘Thing’ that gains the Internet, It’s that the Internet gains from the Thing.” – Patrick Isacson

Accessories
There is an idea of many developers who are working for IoT, to build an ecosystem(SDKs) for the developers to build on their own platform. It may take many skills with many skill resources to design and deliver a successful IoT platform that is both scalable and extensible to be versatile. According to the Reuters “The IoT Platform Companies Database 2015“, there are 250+ platforms available to start development on IoT so there are 180+ startups, 45+ SMEs, and 25+ MNCs which offers such platforms. This is really alarming! Who will connect these all platform to make the “ONE internet of things”? This is really needed to leverage the data mining and to provide better analytics. “ONE Internet of things” not only can make businesses more efficient but makes the businesses ready for future!

Why do I call it an accessory? Because, this is currently “announced” as an add-on to almost every internet of things product sold! It is treated as an accessory! As the Internet of things is said so abstract and developers and designers are busy creating their own hardware and software platforms with different open/proprietary protocols, and shouting that their platform having cool X-Y-Z features is too much obsession for the people. This will ignite developers to start talking about the Web of Things! Similarly to what the Web (Application Layer) is to the Internet (Network Layer), the Web of Things provides an Application Layer that simplifies the creation of Internet of Things applications. Web of Things reuses existing and popular Web standards. But I am still concerned at the common/cross-platforms solutions on which multiple devices can communicate. It is an open discussion, though!

Security

As everyone started turning to Internet of things and as everybody is talking about the IoT, the term “Security in Internet of Things” has become too popular to discuss on every IoT tech geek’s breakfast table. Some devices fall short of enough stack in the tiny microcontrollers used as an actuator end-point, or some devices are just about being low power without any security engines running. As users become more reliant on smart devices and wearables, an increasing amount of sensitive data is being accessed through these devices and transferred among them. The developers must strengthen the defenses by taking clues from the smartphone developers and industry. But it is not easy as to just talking about the security. There’s much more work needed for low power and low memory embedded devices.

Product development—at least for products that anyone expects to be successful—has always been iterative, incremental, and collaborative.

Now, it’s upon us being the builders, the innovators, the creators or the end user to bring the IoT to a stage where all work on a unified platform. It’s a big task to create “ONE internet of things” but filled with too many opportunities for everyone around us to change the world we see today!

Thanks in advance for your Likes and Shares. It would be great to have your added thoughts on this.

Rushi Gajjar


Prototyping the Future of Semiconductors!

Prototyping the Future of Semiconductors!
by Daniel Nenni on 09-28-2015 at 12:00 pm

With major semiconductor mergers and acquisitions running rampant in 2015 (more than double the M&A activity in 2014), the question is where will we go from here? There are many different ways to slice this but for this blog let’s talk about the thousands of semiconductor professionals that will be changing jobs as a result of this M&A hyper activity and the recent reduction in forces (QCOM just riffed 18%).

(Click for larger image)

I see two things happening here:
[LIST=1]

  • Semiconductor people will join system houses as they ramp up internal IC development. Apple is the best example of a systems house becoming a major fabless semiconductor player (vertical integration) and now everyone wants to be like Apple, right?
  • Semiconductor entrepreneurs will start new fabless companies. The problem here is capital but of course that has always been a problem and as the saying goes “Where there’s a will, there’s a way.”

    One of the things I do during my day job is help emerging technology companies get funding. Some of it is from angels, banks, or other traditional sources. Sometimes customers or partners make investments and of course there are always crowd funding sites (Gofundme, Kickstarter, etc…). Unfortunately a slide deck will not always get you funding for a chip project, you really need working silicon but of course that is a chicken/egg kind of thing.

    You may have noticed we have been writing about FPGA prototyping quite a bit lately and of course there is a reason for that. Paul McLellan even did a “Brief History of FPGA Prototyping” blog last week. You can also check out a new video from S2C on Prorotyping the Future or you can get the white paper FPGA Prototyping Primer.

    Bottom line: You can easily do architectural exploration, block design, system integration, and embedded software development for a proof of concept design to raise money for your project. Using FPGA prototyping you can also get it right the first time which is critical for emerging technology companies, absolutely.

    FPGA Prototyping: The next best thing to silicon!

    Speaking of FPGA prototyping, S2C just released their new rapid prototyping solution “Quad Kintex UltraScale Prodigy™ FPGA prototyping Logic Module Addresses Designs with Massive Parallel DSP Algorithms.” This is the latest addition to S2C’s Prodigy Logic Module family aimed at large DSP algorithm development and is ideal for applications such as voice processing, graphics imaging, military, instrumentation, disk controllers, and digital mobile.

    “Designers that must deal with a huge number of DSP calculations now have a highly reliable and fast solution that can help them achieve their stringent time-to-market goals,” commented Toshio Nakama, CEO of S2C. “An added benefit is that our Quad KU115 Prodigy Logic Module is thoroughly integrated into our Prodigy Complete Prototyping Platform giving users access to a vast array of prototyping tools and our expansive library of 80+ daughter cards to quickly build their prototyping targets.”

    You can download the Quad KU115 Prodigy™ Logic Module datasheet HERE.

    With over 200 customers, S2C’s focus is on SoC/ASIC development to reduce the SoC design cycle. Our highly qualified engineering team and customer-centric sales force understands our users’ SoC development needs. S2C systems have been deployed by leaders in consumer electronics, communications, computing, image processing, data storage, research, defense, education, automotive, medical, design services, and silicon IP. S2C is headquartered in San Jose, CA with offices and distributors around the globe including the UK, Israel, China, Taiwan, Korea, and Japan. For more information, visit www.s2cinc.com.


  • Xilinx Skips 10nm

    Xilinx Skips 10nm
    by Paul McLellan on 09-28-2015 at 7:00 am

    At TSMC’s OIP Symposium recently, Xilinx announced that they would not be building products at the 10nm node. I say “announced” since I was hearing it for the first time, but maybe I just missed it before. Xilinx would go straight from the 16FF+ arrays that they have announced but not started shipping, and to the 7FF process that TSMC currently have scheduled for risk production in Q1 of 2017. TSMC already have yielding SRAM in 7nm and stated that everything is currently on-track.

    See also TSMC OIP: What To Do With 20,000 Wafers Per Day although I screwed up the math and it is really over 50,000

    I think that there are two reasons for doing this. The first is that TSMC is pumping out nodes very fast. Risk production for 10FF is Q4 of 2015 (which starts inext week) and so there are only 6 quarters between 10FF and 7FF if all the schedules hold. I think that makes it hard for Xilinx to get two whole families designed with some of the design work going on in parallel. It costs about $1B to create a whole family of FPGAs in a node. On the business side of things, 10nm would be a short-lived node. The leading edge customers would move to 7nm as soon as it was available so the amount of production business to generate the revenue to pay for it all and make a profit might well be too limited.

    I contacted Xilinx to try and they pretty much confirmed my guess:The simple reason is that our development timelines & product cadence lined up better with 7nm introduction. TSMC has a very competitive process technology and world class foundry services and their timeline for their 7nm introduction lines up well with our needs and plans.

    There have been rumors that Intel might skip 10nm too, although the recent rumors are that they will tape out a new 10nm core M processor early next year. I don’t know lf anything much that Intel has said about 7nm, either from a technology or a timing point of view.

    See also Intel to Skip 10nm to Stay Ahead of TSMC and Samsung?
    See also Intel 10nm delay confirmed by Tick Tock arrhythmia leak-“The Missing Tick”

    That brings up the second big reason. All processes with the same number are not the same. TSMC’s 16FF process has the same metal stack (BEOL) as their 20nm process. It is their first FinFET process and so presumably they didn’t want to change too many things at once. Interestingly, Intel made the same decision the other way around at 22nm, where they had their first FinFET process (they call it TriGate) but kept the metal pitch at 80nm so it could still be single patterned. The two derivative TSMC 16nm processes, 16FF+ and 16FFC, have the same design rules and so the same 20nm metal. This limits the amount of scaling from 20nm to 16nm. There is a big difference in speed and power but not so much in density.

    See also Scotten Jones’s tables in Who Will Lead at 10nm?

    At 10nm Intel has a gate pitch of 55nm and a metal 1 pitch of 38nm (multiplied together gives 2101nm[SUP]2[/SUP] although I get 2090nm[SUP]2[/SUP]). TSMC at 10nm has a gate pitch of 70nm and a metal 1 pitch of 46nm, for an area of 3220nm[SUP]2[/SUP]. But perhaps more tellingly, Intel’s 14nm has a gate pitch of 70nm (same as TSMC’s 10nm) and a metal 1 pitch of 52nm, only a little looser than TSMC’s 10nm pitch of 46nm. So another reason Xilinx might skip 10nm is that it would not look good against Altera’s products in 14nm.

    TSMC say that 10nm is about 50% smaller than their 16nm processes. TSMC said that 7FF will be 45% of the area of 10FF. Without any information to go on, it is still clear that Intel’s 7nm will be higher density than TSMC’s. The TSMC 7nm process will probably close to the Intel 10nm process. This is not necessarily a criticism of anyone. Intel is totally focused on bringing out server microprocessors and can read the riot act to all their designers as to how restrictive their methodology has to be and the designers have to suck it up. TSMC has to accept a much wider range of designs from a broad group of customers that they do not control in the same way.

    [TABLE] style=”width: 400px”
    |-
    | Intel: you will do designs this way
    Intel designers: but…
    Intel: you will
    Intel designers: OK

    | TSMC: you will do designs this way
    Apple engineers: no we won’t
    TSMC: OK

    |-

    One wrinkle in all of this is also the Intel acquisition of Altera, Xilinx’s primary competitor. They seem to have been struggling to tape-out their designs in Intel’s 14nm process. If Intel is serious about using FPGAs in the datacenter, especially if they want to put the arrays on the same substrate as the processor, then they will need to get Altera’s fabric into 10nm and then 7nm hot on the heels of the server processors themselves. Xilinx’s worst nightmare would be if they produced a family of arrays in TSMC 10nm (only slightly better than Intel 14nm) and Altera got a family out in Intel’s 7nm which is a generation ahead.

    So, Xilinx skipping 10nm and Altera being acquired by Intel with an opaque roadmap makes for an interesting spectator sport.


    Nine Cost Considerations to Keep IP Relevant

    Nine Cost Considerations to Keep IP Relevant
    by Pawan Fangaria on 09-27-2015 at 12:00 pm

    It’s about 15 years the concept of IP development and its usage took place. In the recent past the semiconductor industry witnessed start of a large number of IP companies across the globe. However, according to Gary Smith’s presentation before the start of 52[SUP]nd[/SUP] DAC, IP business is expected to remain stagnant for next 5 years. There are reasons to believe into Gary’s thesis. A bird’s eye view shows an IP sitting at the heart of an SoC or subsystem. This is significant reason for a system company to assess an IP fully before utilizing it; also assess the IP provider’s quality and other business practices. At the tip of the iceberg it appears very simple to buy an IP and use it in your SoC design as required. However there are significant implications of using an IP from business as well as technical perspective; not all system companies have bought into the idea of using 3[SUP]rd[/SUP] party IP, barring some standard and common IP blocks from reputed suppliers. The standardization of IP blocks that go into most of the SoCs reduces cost for the overall value-chain of developing SoCs; however it can commoditize the stuff to an extent that it can start impacting the differentiated value of SoCs. Moreover, there are serious technical implications that need to be considered before using IP. There has been a significant change in the modern SoC ecosystem where the system companies are experiencing increasing need of customizing IP before their use in SoCs.


    Considering it from a macroeconomic angle in a consolidating semiconductor industry, the IP-based business model of SoC design does provide a good proposition provided differentiated value is added into the SoC. However, it’s essential that the hidden costs in accomplishing some specific tasks to make this model successful are better understood. Often certain tasks are not performed adequately because of lack of understanding, and also because the associate costs not considered. This can leave an IP in a poor state, inside or outside of an SoC. The success or failure of an IP in a system depends upon how best these tasks are understood, invested-in, and performed by the IP provider as well as the system integrator. There are specific costs involved in doing these tasks which stand apart from the usual developmental cost involved in the normal course of IP development. These exclusive types of costs other than normal development are mentioned below along with what incurs those costs and their proper rationale.

    Cost of Differentiation – The differentiation in an IP has to be construed from the design level. The system companies are expecting differentiation in IP that fits into their designs so that they don’t have to design the same IP themselves as much as possible. A common form of differentiation can emanate from IP vendors for providing extended solutions such as interconnect along with the cores. It’s true that such differentiation can again be seen as common in an IP for different SoC vendors; however it can move the IP to a level up. IP providers such as ARM, Synopsys, Cadence and some others are providing subsystem level IP solutions. On the other side of the coin an IP provider can work in joint collaboration with an SoC vendor to design a completely differentiated IP. In this case the cost can be very high; in-sourcing of the complete IP team may be preferable for the SoC vendor. In other words, the IP team in-house with the SoC vendor can work at the sub-system level which allows the team to add enough differentiation, do trial layouts and optimize, and thus reduce risk and time-to-market.

    Power is becoming a prime criterion for differentiation, especially in the mobile and IoT market. An IP characterized for certain power parameters with a particular technology needs to be re-designed in most cases of newer technology; moreover the dynamic power profile may change significantly with the use-cases.

    Considering PPA (Power, Performance, and Area), an IP can be designed to have flexibility to scale between different factors such as power and performance according to the technology used.

    A new concept of IP abstraction is coming up where an IP is delivered at a higher level of abstraction which goes through High Level Synthesis at the SoC end. This provides scope of differentiating the IP and SoC in power consumption. Qualcommand Googlehave used this approach with Calypto(now Mentor) HLS solution where they deliver ‘C’ code which can be further optimized while integrating into SoC at system-level. A start-up Adapt IP provides option for delivery of IP at a high level of abstraction. In this scenario, the cost for IP vendor can decrease, but that gets added up in the SoC for the SoC vendor to account for differentiation and implementation. Moreover, this brings in a newer methodology for SoC architecture exploration and integration at the system-level and asks for fresh investment and learning. I will talk more about it in later sections.

    Cost of Customization – One may think customization as a part of differentiation, but actually they are distinct. Customization is a process which takes place during integration of an IP in an SoC. There is a separate section on integration in this article. In this section I am talking about the provisions which need to be made in the IP itself to make it customizable according to different environments; interconnect IP is a good example in this case. For example, ArterisFlexNoC can be configured and customized for interconnections on the chip that can provide best latency, least congestion, and optimize other aspects. Similarly power management can be another area where configuration can be added for power harvesting. So the question is how configurable your IP is so that it can be customized according to different environments? Configurability in your IP adds provisions in your IP to be customized in different environments. This increases the value of your IP to operate in a wider range of possibilities. More often than not an SoC vendor may need to ask an IP vendor to add specific customization in the IP so that it can exactly fit into the scheme of the SoC. This situation may get extrapolated to an extent that the IP gets transformed into a subsystem; proper evaluation of cost for such customization must be done.

    Another kind of customization can be for different market segments such as automotive segment which needs wide range of operating temperature and other environmental parameters.

    In certain market segments like IoT, where the standards can vary by a large extent, SoC vendors prefer adding custom IP in-house rather than buying from outside.

    Cost of Characterization – This is a big area where IP needs investment, specifically at advanced technology nodes where process can vary significantly between different foundries at the same node. It asks for the characterization of IP at every process variant. It depends how much pre-characterization can be done at the IP level; the SoC vendor might ask for special characterization at a specific node of choice for the SoC. A level of prudence can help here. An IP for GPU or mobile processing may need advanced nodes like 14nm FinFET and hence the characterization for process variants at those nodes will be needed. However, an IP for other applications which can stay at higher nodes may not need too many characterizations. But there may be other complications for specific applications. For example, an IP for automotive applications can stay at higher nodes (although moving down from 150nm and 90nm) such as 55nm, 40nm, or even 28nm for specific cases; however that will need characterization for a wide range of temperature and other PVT conditions.

    Within an IP the characterization can be at the fundamental unit level such as bit cell and at macro level. The fundamental unit level characterization may not change frequently, but macro level characterization may change according to the design. So, that kind of characterization needs to be planned appropriately.

    Cost of Acquisition – The cost of acquisition of IP is a very important aspect for SoC vendors. Large system companies have specific processes laid out for IP selection and procurement. They include items such as quality of the IP, ease of its integration, the IP vendor’s past record and ranking, vendor support throughout the SoC lifecycle, cost and RoI analysis as per single or multiple use of the IP, etc. It’s prudent to explicitly mention, specifically in single use, what kind of modifications and support elements such as error code revisions, defect fixes, configuration modifications, and so on are permitted. Also, the fees applicable for reusing and making variants of IP must be explicitly mentioned.

    The evaluation of an IP and its integration into SoC is co-ordinated with the associated EDA vendors, development partners, and design service providers along with the IP provider. It’s a costly affair and hence it’s required that the list of selected and qualified vendors is kept short. The emergence of eSilicon as an IP service provider is a step in the right direction for IP evaluation before its acquisition.

    An important aspect comes into picture when the IP needs some customization. In this event it’s important for both the IP provider and the SoC vendor to determine how the customized code will be maintained in future, whether the changes are generic enough to be merged into the main code branch. If not, then special support for that custom IP branch will be needed, asking for extra support resources borne by either the IP provider or the SoC vendor. So, here the question comes, how much is the support? Is it scalable and profitable for the IP provider to take it in her/his main stream? If not, then is it justified for the SoC vendor to acquire the commercial IP, customize it, and maintain it, or otherwise develop her/his own IP? If it is customization by the SoC vendor on top of the commercial IP, then the ownership rights must be clarified at the time of acquisition.

    The cost of acquisition can also be factored in on a long-run production basis where the IP provider is paid on the basis of royalty fees. This can be finalized on the basis of specific terms such as actual sales or shipments. For an IP provider as well as the SoC vendor a typical challenge appears when the fab does not see enough RoI in creating a slot for a particular IP; this needs right level of negotiation before embarking on the journey.

    I will park this part of the article at this stage as it has gone long. Stay tuned to read part – 2 of this article where I will mention about rest of the costs involved in using IP in modern SoC ecosystem. In the pursuit of increasing value of IP for SoCs to continue to have differentiated value, these costs must be understood well and accounted for in order to create a win-win situation between the IP provider and SoC vendor. This is required to maintain the IP industry at a healthy level and grow further from here.

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com