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Semiconductor Expert Forum

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Something Old, Something New…EDA and Verification

Something Old, Something New…EDA and Verification
by Ellie Burns on 10-04-2015 at 12:00 pm
Categories: EDA, Siemens EDA

When I got the opportunity to blog about verification, I thought, what new and interesting things should I talk about? Having started my EDA career in 1983, I often feel like one of the “oldies” in this business…remember when a hard drive required a static strap, held a whopping 33 MB, and was the size of a brick? Perhaps they should get someone who has just a few less EDA miles on them? However, thinking further on it, “we veterans” have experienced big changes in design and verification and the impact that tools and technology have had in creating new devices and exciting new markets that are changing the way we live. We have a lot to share.


That’s why I’m initiating a series of blogs to discuss valuable insights into the methodologies, tools, and flows we will need to move into the next generation of high technology. I’ll begin with several blogs about a trend I am seeing now—further reducing the power in designs in a world of increasing performance using a fairly complex interaction of HW and SW. After looking at the most important trends in low power, we’ll broaden our conversation to encompass other trends in verification.

We are seeing that how a typical ASIC or SoC low power design is done is starting to change dramatically. Current low power design and verification methodologies are breaking down, with some of the most successful leading semiconductor companies even losing business because they did not reduce power enough. The traditional implementation-focused low power methodologies are being strained because they ignore a whole phase of the verification process—those that exist at the RTL or above. And companies everywhere are feeling the pain.

We need new low power methodologies, we need new tools and flows, and we need low power techniques that make it easier to incorporate low power design and verification very early in the design cycle. Waiting until the entire SoC/ASIC is assembled and implemented is not the best way to optimize for power. We are now seeing SoCs going from 10 to 100 power domains, which introduces a whole new level of complexity in the design. How do you know that you have properly verified all of the states and interactions? Should you have a methodology that considers low power coverage now?

It’s neither feasible, nor prudent, to wait until the back end of the design flow to start paying attention to low power design techniques and their validation, as it is done presently. Too many interactions with lower power circuitry are missed, and it is too late to make design changes that either fix bugs introduced by low power cell insertions or optimize the balance between power, performance, and area. You need to move up in abstraction and have the tools that support there. You need to start thinking about power at the RTL or above.

First of all, we need to take full advantage of new capabilities in the Unified Power Formant (UPF) that allow you to begin power management at a higher level of abstraction. Up until now, the UPF has tended to be implementation-oriented. But describing power intent at this low-level of abstraction is inefficient, forcing power intent information to be managed across different stages of the design flow and across different implementations of a particular system.

EDA companies have been working diligently with the semiconductor industry to develop an enhanced and more useful standard that provides more capabilities. After all, you have to make sure that all of those things you’re doing to achieve lower power in your designs—like power gating, multi-voltage design, etc. —don’t screw everything up. Adding these to your design can essentially create a brand new design. So there are BIG differences between traditional simulation and low power simulation. You need to make sure you are using the best, and the appropriate, power aware tools and techniques in your entire verification flow—from simulation to formal to emulation.

As I implied, some of us may be old, but we “ain’t dead yet.” Our experience can help guide the industry toward a brave new technological world. In forthcoming blogs I’ll explore in more depth what’s changed in low power technology and what you need to look for in solutions you WILL need to stay nimble.
My next blog will look at what’s been happening in UPF to help facilitate the new wave of changes coming in low power solutions. We’ll delve into a new power-design methodology, called “successive refinement,” as used by ARM®, which integrates low power verification techniques starting from the IP block through SoC integration and implementation.

Subsequent blogs will talk about specific aspects of the successive refinement flow: things like issues with multi-clock domain designs when low power circuitry is introduced, what you should be looking for when debugging low power designs, the way you should approach low power coverage, and why you need emulation to for HW/SW co-simulation in a low power environment.

I would also like to hear your stories about your successes—and stumbling blocks—in our constantly and rapidly evolving electronic landscape.

Until next time, if you want to read a good overview of low power challenges and solutions, check out the on-demand web seminar “New Low Power Verification Techniques” at:http://www.mentor.com/products/fv/multimedia/new-low-power-verification-techniques

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Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes

Leveraging Synopsys’ Lynx Design System for SoC Designs on Advanced Nodes
by Pawan Fangaria on 10-04-2015 at 7:00 am
Categories: EDA, Synopsys

There was a time when design goals were decided in the beginning, targeted on a particular technology node, design planning done for the same, and implementation done through point tools connected indesign flows customized according to the design. It’s no longer the case for modern SoC designs; there are multiple technology nodes to consider before planning for a design, a complete design system has to be in place with tools at all levels sharing design information as required, smart methodologies must be employed to gain best accuracy, and planning done at each stage for better QoR and faster design closure. While there is no relaxation in PPA (Power, Performance, and Area) optimization, in Synopsys’ terminology the design completion has to “shift-left” with fewer resources and shorter time.

With that notion in my mind, when I came across the webinar from Synopsyson their Lynx Design System which was used to implement a network design with 16 ARM®Cortex®-A53cores and ARM Corelink[SUP]TM[/SUP] CCN-502on Samsung14LPP process, I happily attended it. Although new capabilities of IC Compiler II and Lynx Design System were introduced during this year’s DAC, I was interested to know more about these in a real design environment.


The Lynx Design System is ready for advanced technology nodes with leading foundries such as TSMC, Samsung, GLOBALFOUNDRIES, UMC, etc. Technology plug-ins are available to help customers quickly setup desired technology nodes. The design case in this webinar used the technology plug-in for Samsung’s 14nm technology node and Synposys’comprehensive RTL-to-GDS design flow in conjunction with ARM standard cell libraries. The platform already is being used by 50+ companies. The IC Compiler II P&R system is equipped with a versatile infrastructure to support multi-corner, multi-hierarchy, multi-mode, multi-voltage, and multi-view design; and powerful new floor-plan, clock-tree, timing and optimization engines. It provides up to a 10x increase in productivity with 5x faster implementation and half the iterations, all with better QoR.


Lynx employs a plug-in architecture where a technology independent layer of global methodologies can be combined with a technology specific layer as per foundry process requirements. The customized flow provides significant productivity for designers.


The system provides a flexible, user-friendly, iterative, and productivity-oriented flow where designers can explore for better alternatives and tune the flow accordingly with the help of a Runtime Manager. The Design Tracker provides progress reports in different forms including tables, graphs, and bar charts with links to original data files for faster access and analysis. There can be multiple tables, plots or bar charts in a report. Also proper data security is maintained for authorized access of files and reports. Separate reports can be obtained for designers’ and managers’ needs where a designer can dig into design specific attributes whereas a manager can check the project status. A good demo on design tracking is available in the webinar.


The QoR Viewer in the Lynx Design System provides many built-in reports for designers to analyze and ensure the best QoR for a design.

By using Lynx Design System designers could create an energy efficient processor subsystem reference implementation in just four weeks of time.


Frequencies of 1.44 GHz at ssa/0.72v/40c process corner and 1.7 GHz at tt/0.8v/25c process corner were obtained against planned 1.5GHz. The Lynx Design System provided best efficiency by combining fast hierarchical synthesis at pre-route stage and flat P&R implementation down the stream. The hierarchical synthesis employed Synopsys Physical Guidance (SPG) technique in Design Compiler Graphicaland flat P&R implementation leveraged the best capacity, runtime and QoR provided by IC Compiler II. The combined hierarchical synthesis and flat P&R approach reduces the overall TAT by 40% in this case.

Interactive design planning at the top level coupled with intelligent techniques such as module placement optimization and timing optimization through effort indicators on fly-lines makes the design more productive down the flow. The implementation flows at both synthesis and P&R stages can be tuned for best QoR and runtime. The Design Tracker can be used to review design summary, synthesis, clock-tree synthesis and other reports at various stages in both hierarchical and hybrid flows.

Chad Gamble at Synopsys has explained the system in more detail with good demos during the presentation. After a small registration step, the webinar of ~40 minutes can be attended HERE.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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TSMC Award Recognizes Andes’ IoT Credentials

TSMC Award Recognizes Andes’ IoT Credentials
by Majeed Ahmad on 10-03-2015 at 7:00 am
Categories: Andes Technology, IP

The system-on-chip (SoC) movement is intrinsically linked to external IP products, and here, it’s not just fabless chipmakers who work closely with IP suppliers. Large foundries like TSMC also maintain close relationships with IP vendors to optimize their process nodes and libraries for processor cores and other design architectures that these IP firms provide.

Now if you look at the SoC landscape, while mobile markets provide the bulk of volumes, the Internet of Things (IoT) platform is clearly the next frontier. The testament of IoT’s growing clout is TSMC’s strategic focus on expanding its ecosystem to serve the IoT markets. Case in point: the world’s largest pure-play fab has built a close liaison with Andes Technology Corp., a supplier of low-power and low-cost embedded CPU cores also based in Hsinchu, Taiwan.


Andes wins TSMC’s 2015 Partner of the Year award for New IP

TSMC has presented Andes the 2015 Partner of the Year award for New IP during the company’s recent Open Integration Platform Ecosystem Forum. TSMC’s symposium is aimed at having its customers and ecosystem partners under the same roof and share with them new solutions for the prevalent design challenges.

The award, received by Emerson Hsiao, Senior VP of Andes Technology USA, underscores the three-way ecosystem between chipmakers, fabs and IP suppliers. Hsiao claims that Andes’ CPU cores have been shipped in over 700 million chips, and the majority of these chips have been fabricated at TSMC. The Hsinchu, Taiwan-based IP licensor, which houses its key CPU designers in Sunnyvale, California, also boasts 85 customers worldwide.


Hsiao: 700 million CPU sockets and counting

At the OIP symposium, Suk Lee, Senior Director of TSMC’s Design Infrastructure Marketing Division, acknowledged the crucial importance of power efficiency in the emerging IoT applications and subsequently the role of processor IP in power savings in the next-generation IoT chip design.

Andes offers a series of 32-bit processor cores labeled as N7, N8, N9, N10 and N13 and these IPs are targeted at IoT applications encompassing areas such as smart sensors, smart appliances, medical, touch panels and wireless charging.

Andes’ IoT Play

There are clear signs that IoT has started to disrupt the microcontroller segment where the growth now mostly depends on how MCU makers innovate and differentiate their chips for specific IoT markets. Here, Andes’ 32-bit processors and associated SoC platforms offer a viable alternative to other processor cores such as ARM and MIPS to better differentiate their products.

Second, given the fact that the IoT industry is still in an embryonic stage and most IoT products have low or medium level volumes, Andes’ low-cost structure goes a long way for the IoT-centric chip designs. Third, a smaller code size greatly helps in longer battery life that epitomizes the IoT value proposition.

Andes was founded in 2005 with the vision of hardware functionality specific to power saving needs of the new computing paradigm that would serve machine-to-machine (M2M)-like services. Since then the company has been making steady gains with its 32-bit processor cores in the emerging IoT markets like smart home and connected wearables.

Andes scored a major design win earlier this year when the SoC powerhouse MediaTek announced to license its N9 processor core. It’s worth noting that MediaTek has so far been exclusively working with ARM processor cores.


MediaTek licensing N9 core is a major endorsement for Andes

Andesis also exploring the diversified potential of IoT markets through the community platform Knect.me. The website showcases IP solutions, software stacks, and tools for SoC implementation for chipmakers, application developers and system houses. Next up, Andes is planning to create the “IoT League” to showcase products that have been developed through the Knect.me community.

Also read:

Andes: 32-bit MCUs Way to Go for IoT

A Brief History of Andes Technology

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What’s Testing Design Limits at ITC?

What’s Testing Design Limits at ITC?
by Beth Martin on 10-02-2015 at 12:00 pm
Categories: EDA, Siemens EDA

The 46[SUP]th[/SUP] IEEE International Test Conference (ITC) will be held the week of October 5, 2015 at the Disneyland Hotel Conference Center in Anaheim, California. ITC is where you will discover the latest ideas and learn about practical applications of test technologies.

As you take in panels, tutorials, presentations, and the exhibits, you might find that some common themes emerge as the folks in the world of test grapple with finding solutions to today’s biggest issues. I talked with Ron Press, Technical Marketing Director of Tessent Solutions at Mentor Graphics, and Vice General Chair of the ITC Steering Committee about the trends he sees that are testing the limits of test technologies.

According to Ron, “We see two growing trends that people are trying to resolve. The first issue is how to provide efficient test methodologies when dealing with giga-gate designs. The other issue is how to manage pattern-set sizes in these huge designs as well as supporting designs with additional patterns, such as cell-aware, in order to meet quality requirements.”

To address the deployment of giga-gate testing, Ron said, “Hierarchical test is beneficial for designs with 20 million gates and often viewed as required for designs over 40 million gates.” Divide and conquer has been the methodology employed for all phases of enormous chip design and design-for-test (DFT) now joins that practice. Using hierarchical test, the DFT features and test patterns are completed on individual blocks and then reused at the top level.

Teams bringing hierarchical test to bear on big designs are looking to achieve these goals:

  • Move up DFT insertion and pattern generation earlier in the design process
  • Reuse block-level patterns
  • Allow geographically-dispersed teams to work on individual blocks without needing the top-level design
  • Enable automatic test pattern generation (ATPG) to be performed on smaller workstations
  • Significantly reduce test time and ATPG run time

It is a myth that top-level pattern generation for the entire chip in one ATPG run is more efficient for test time versus testing blocks individually. Actually, hierarchical test is often 2-3x more efficient than top-level test. Annapurna Labs is presenting a conference paper on their hierarchical test methodology. Spreadtrum Communications and Mediatek will be discussing their successful use of hierarchical test techniques in the Mentor Graphics Theater.

Huge designs fuel the growth of scan pattern-set sizes. Ron said, “A new approach is necessary to greatly improve the ability to efficiently test designs with large pattern sets. This approach applies a new type of test point identification to embedded deterministic test (EDT). We have seen a 2x-4x reduction in test-pattern count using this new approach.”

With the growing use of cell-aware patterns, test teams see bigger demands on test time. That is why there is growing interest in the new EDT test point solution. For example, Intel is presenting a paper at the conference that relates their success in using EDT points for compact, cell-aware tests. In the Mentor Graphics Theater, Broadcom will be discussing real-life data on their experience using EDT points.

If you are heading to Disneyland for ITC, be sure to attend the hierarchical giga-gate testing and managing pattern-set size sessions. Drop by the Mentor Graphics Theater to hear real world applications of these solutions. And, introduce yourself to Ron Press. He is always happy to talk about test.

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Getting EDA Across the Chasm: 15 Rules Before and 5 After

Getting EDA Across the Chasm: 15 Rules Before and 5 After
by Paul McLellan on 10-02-2015 at 7:00 am
Categories: EDA, Solido

Crossing the Chasm by Geoffrey Moore (not that G. Moore!) is one of the most well known books on high technology marketing. When I worked at VaST, Mohr Davidow Ventures (MDV) invested in us and Moore (not Mohr), who was a partner there, spent an afternoon with us brainstorming what it would take for us to cross the chasm. Coincidentally, Crossing the Chasm is actually a similar, but more readable, version of an earlier book called Marketing High Technology by Bill Davidow (yes, the D of MDV) which is where the concept of the whole product was introduced. The key insight of both books is that while early adopter enthusiasts will do a lot themselves to compensate for missing pieces of the ecosystems, the mainstream will not. Having a whole product that is ready for the mainstream is really what it takes to get across the chasm.

Jim Hogan and EDAC have been running a series of discussions with founders of EDA startups on what it takes to cross the chasm. Kathryn Kranen (of Jasper, now part of Cadence), Ravi Subramanian (of BDA, now part of Mentor) and Amit Gupta of Solido (still independent). The next evening is in December but I don’t yet have a date. The guest will be John Lee, now a VP at ANSYS having been the founder and CEO of Gear before selling it to them.

I sat down last week with Jim and Amit to talk about what it takes to get over the chasm. Very few EDA companies cross the chasm to, say, $5-7M in revenue. It is fairly easy to get to $1M, everyone has some friends. But $5M to $10M to $20M is a hard progression to achieve. I should point out that Amit’s views are not just based on Solido. He was the founding CEO of Analog Design Automation (ADA) which was acquired by Synopsys in 2004.

I read somewhere that listicles are click-bait on the net, so here is a recipe listicle style:
[LIST=1]

  • Find out what the customer pain points are from technology enthusiasts
  • Validate customer pain points across many technology enthusiasts in many different companies. Don’t design a solution for only one company/enthusiast
  • Ensure that there is a large enough market if the product is successful. Avoid the “Intel only needs one copy” products.
  • Ensure that there is alignment between technology enthusiasts, company pain points, and what companies will pay for. Avoid science projects for technology enthusiasts (Intel doesn’t need any copies at all)
  • Figure out a business model to capture the value being delivered (floating licenses, site license, royalty…)
  • With 1-5 raise any investment needed to execute
  • Innovate to solve customer pain points with 10X differentiation from competition (especially big guys who can say they will have it next year if it is just 2-3X better)
  • Hire a product development team capable of delivering product with the customer in the loop
  • Develop minimum viable product
  • Iterate until successfully deployed minimum viable product with technology enthusiasts (early adopters) finding product-market fit
  • Establish needed partnerships with big EDA companies to integrate product into customer flows (Cadence Connections, Synopsys InSync, Mentor OpenDoor etc). This will also require customer references.
  • Survive any market downturns, there will probably be at least one period of weakness/trauma
  • Execute fast enough that competition doesn’t catch up, market window doesn’t pass (although being too early is often more of a problem), and you don’t run out of money
  • Fail fast on stuff that isn’t going to work out
  • Close first purchase orders. The only validation that counts.

    If and only if (aka iff for mathematicians) you successfully complete all these steps do you have a shot at crossing the chasm. Then you can read Geoffrey Moore’s next book Inside the Tornado (which uses Synopsys as one example). This is the point at which you throw gasoline on the fire. In my opinion, it is the critical decision point in an EDA company (and many other types): when do you ramp sales. Too early and you run out of money paying a sales force who cannot sell the immature product. Too late and…this never happens.

    Then you need to:
    [LIST=1]

  • Mature the whole product solution for deployment to a larger mainstream audience (proliferation)
  • Develop a sales recipe for short evaluations at high success rate. Aim for 90 days from discovery to close, not 9 months
  • Build out the company: engineering, AEs, marketing, sales, G&A
  • Deploy and support larger customer base
  • Grow

    Then in the third phase there is a very short list:
    [LIST=1]

  • Be acquired
  • IPO…this never happens, especially post Sarbanes-Oxley
  • Grow profitably, generating cash (Denali showed it can be done for many years before Cadence made them an offer they could not refuse)

    For the biggest picture of all, the whole company, there are also a few rules. First, never take more than $10M in investment ($5M is better) or it will be really hard to sell in a way that makes everyone whole (carve-out and cram-down are not good words). Patents are important, research shows $300-900K per patent in additional exit valuation over and above forward revenue multiple. But don’t do too many since they are expensive to file and expensive to maintain. Market the company too, not just the product. Sell the sizzle as well as the steak.

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    Top 10 Reasons to invest in Interactive Design Rule Checking tools

    Top 10 Reasons to invest in Interactive Design Rule Checking tools
    by Tom Dillinger on 10-01-2015 at 12:00 pm
    Categories: EDA, Siemens EDA

    One of the most energetic presentations at the recent TSMC OIP 2015 symposium was given by Tom Williams from Qualcomm, who shared his insights (and enthusiasm!) for Mentor’s Calibre RealTime interactive Design Rule Checking (iDRC) product.

    Paraphrasing Tom’s presentation (and with a tip of the hat to David Letterman), here is a list of the Top 10 reasons to invest in iDRC verification, with a tool such as RealTime.

    (10) Design rules have become incredibly complex – the days when the (majority of) rules could be memorized are long over. The rule descriptions are also very complex, necessitating visual feedback. Interactive DRC tools support the full DRC runset.

    Tom W. highlighted that the Design Rule Manual (DRM) for TSMC 16FF+ devotes 80 pages to the MEOL layers alone. 🙁

    (9) Using a connectivity-driven schematic model, layout “gen-from-source”, and parameterized layout cells (with abutment and merging support) does greatly assist layout designers. Yet, the rule complexity in #10 above suggests that correct-by-construction for cell/macro layout composition is extremely difficult to achieve – a fast verification method is still required.

    (8) Multi-patterning verification requires color assignment to be exercised, and (complex) cyclic errors to be highlighted. These decomposition algorithms are far beyond traditional width/spacing/enclosure checks, and demand automation.

    (7) The performance of iDRC tools provides fast turn-around time. It completely replaces the traditional interactive method – i.e., “pop up a ruler, measure, and compare to the DRM”.

    There is a caveat, to be sure, on the size of the layout macro that is suitable for iDRC. Tom W. indicated that the Calibre RealTime guideline is to work with a layout cell with less than 3 million shapes.

    (6) RealTime performance can be further enhanced by using the “Recipe Editor”, as shown in the figure. iDRC can be quickly configured to define a subset of rules and/or layers that will be presented to the checking engine.

    Tom W. provided the example of “density checks” as a rule subset that would typically be excluded from RealTime verification during initial layout composition.

    (5) The computational resource applied to iDRC – typically, a local workstation or a remote login server dedicated to interactive applications – alleviates the “server farm” from this resource demand. There’s no need to streamout, then submit, queue, dispatch, track, and write report files from batch DRC jobs, a workload which can otherwise be accommodated by interactive execution.

    (4) iDRC tools are readily integrated into all layout platforms. As illustrated in the figure, toolbars and menus for iDRC are an integral part of the layout cockpit (as is the Calibre error report and viewing feedback). There is no need to exit from the interactive layout session, a big boost in productivity.

    Tom W. is a big layout bindkey user — he has set up several bindkeys for common RealTime commands, as well.

    (3) To be sure, iDRC does not replace batch verification. However, it is the most productive means to quickly verify the layout updates made to address batch run errors. The consistency of runsets used for both batch and interactive checking enables fast clean-up iterations using iDRC.

    (2) Tom W. specifically highlighted that also iDRC enables a much quicker learning curve when starting layout design in a new process technology. The fast check, visualize, and fix loop helps the layout and circuit design team quickly explore initial cell/macro power rail and signal track template options.

    The emphasis on a short learning ramp is consistent with a major theme of the 2015 TSMC OIP symposium. Early adoption and partnership with TSMC on advanced nodes is more important than ever, especially when making PPA design trade-offs.

    and, finally, a very subjective advantage, but a critical one nonetheless:

    (1)Every layout engineer wants to be as productive as possible. Schedule milestones are always tight, both during initial design feasibility assessment and the tapeout crunch. The morale (and stress) of the layout team is typically shared across the entire design team.

    The enthusiasm that Tom W. displayed for iDRC with RealTime was infectious – you could tell the entire audience got a boost. Ensuring the design team can develop and maintain that high energy level throughout a project provides great benefits – this may seem somewhat intangible, but ultimately does affect the bottom line.

    And, as an aside, if your team utilizes layout contractors for assistance with the (peak) workload, you want to be sure that word gets around this close-knit community that you’re making the investments to maximize layout productivity – you definitely want it to be known that you’re a great place to work!

    If you haven’t looked at iDRC tools such as Calibre RealTime in a while, I would encourage you to do so – or, contact Tom W. and experience his ebullient recommendations directly. 🙂

    -chipguy

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    EDA By the Numbers, Phil Kaufman, Emerging Companies and More

    EDA By the Numbers, Phil Kaufman, Emerging Companies and More
    by Paul McLellan on 10-01-2015 at 7:00 am
    Categories: EDA, Events, IP

    The quarterly numbers are out from the EDAC Market Statistics Service (MSS) for Q2. The headline number is that revenue for the industry increased by 8.5% for Q2 to $1906.5M versus $1759.9M in Q2 last year. The four quarter moving average, that smooths out a lot of seasonality by comparing the most recent four quarters to the prior four quarters also increased by 8.5% (this is not an identity, the numbers are usually different). Just to emphasize, these are Q2 numbers and it is happenstance that this blog is going to occur on the first day of Q4.

    The graph above shows growth by category, 2015 on the left and 2014 on the right. All categories grew except PCB.

    Employment in the industry is up too. Companies that were tracked employed a record 32,806 professionals in Q2 2015, an increase of 4.9 percent compared to the 31,259 people employed in Q2 2014, and up 2.1 percent compared to Q1 2015.

    Wally Rhines in his position as the EDAC board sponsor for MSS said…The EDA Industry continues to show solid revenue growth in the second quarter, with double digit growth in semiconductor IP and services. CAE and IC physical design also reported solid growth. Geographically, all regions except Japan saw revenue increases, especially Asia/Pacific.


    Talking of Wally Rhines, he is also the recipient of this year’s Phil Kaufman award, which is jointly sponsored by EDAC and IEEE CEDA. I am assuming that you don’t need me to tell you that he is also the CEO of Mentor Graphics. The awards will be presented at the Phil Kaufman Award Dinner which will be held at the award presentation and dinner at 6:30 PM on November 12, 2015 at the 4th Street Summit in San Jose (address is 88 4th Street). You can register for the dinner here.

    Coming up later this month is the next EDAC Emerging Companies meeting. It will be at 6-9pm on Thursday October 29th at the SEMI headquarters (also the EDAC headquarters) at 3081 Zanker Road, San Jose. This is the first of a new series on legal issues and is titled Patents and Patent Litigation: Develop, Strengthen, and Protect Your Intellectual Property. The event will be cicked off by the mayor of San Jose, Sam Liccardo, and the director of the new Silicon Valley United States Patent Office, John Cabeca. Hands up if you didn’t know that there was a Silicon Valley USPTO. It will be a West Coast regional office, serving California, Nevada, Oregon, Washington, Arizona, Alaska and Hawaii and opens on October 16th, in San Jose City Hall.


    The panel session, on patents and patent litigation, will be moderated by Salumeh Loesch of Klarquist Sparkman, with panelists John Cabeca, who I just mentioned, Karna Nisewaner of Cadence, Robert Sahs of Fenwick & West and John Vandenburg, also of Klarquist Sparkman. The evening is free but space is limited and so you must register here.

    I was going to reference a previous blog I wrote about patent valuations, but it is actually going out tomorrow morning. In a discussion I had with Amit Gupta and Jim Hogan last week, Jim told me:Patents are important, research shows $300-900K per patent in additional exit valuation over and above forward revenue multiple.

    So that is another segue into the acquisitions that have been going on in the last few months, both in the EDA industry itself and also in the customer base.

    Mentor acquired Tanner EDA and also Calypto (where they were already a majority shareholder). The biggest acquisition for sometime was Synopsys acquiring Atrenta the evening before DAC. Synopsys also enriched their IP portfolio with a number of acquisitions of Bluetooth and security technology. In a sort of cross-border acquisition involving an EDA company and a company normally perceived as a customer, Intel acquired Docea Power.

    In the customer base, there have been acquisitions too. The change this year is not so much the number of acquisitions but the size of them. Intel acquired Altera (it hasn’t finally closed yet) for $16.7B.

    Avago acquired LSI Logic for $6.6B last year, and broke it up, selling the flash business to Seagate, and the networking business to Intel. Then they acquired PLX Technology and Emulex. Finally, the big one: earlier this year, Avago acquired Broadcom for $37B (again, still not closed). After it closes the merged company will keep the Broadcom name. It will have annual revenue of around $15B.

    The potential cloud on the horizon of all of this for EDA/IP is two fold. Firstly, in a merger the EDA budget for the merged company never goes up. Avago/Broadcom will have one of the largest IP portfolios (both IP in the patent sense and IP in the structures-on-silicon sense) which means it is likely to acquire less 3rd party interface IP from companies like Cadence and Synopsys. This probably won’t have an immediate affect, all the companies have EDA software and IP already, and designs in progress where they are not going to suddenly change the methodology, but as those contracts come up for renewal it is possible that the EDAC MSS will be reporting less rosy numbers next year and beyond.

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    Xilinx Beats Altera to the First FinFET FPGA!

    Xilinx Beats Altera to the First FinFET FPGA!
    by Daniel Nenni on 09-30-2015 at 10:00 pm
    Categories: FinFET, FPGA, Xilinx

    Why do I stalk the FPGA industry? Well, FPGAs are an important part of the fabless semiconductor ecosystem for two reasons: 1.) They enable very cost effective design starts which are the life’s blood of the semiconductor industry and 2.) FPGA prototyping allows designers to verify their designs before committing to silicon and gives software developers a head start with working programmable silicon. And if that isn’t enough, the battle between industry leaders Altera and Xilinx is Kardashian-like reality TV. Or, if you are into sports, it would be a UFC Championship Match inside the Octagon. In this scenario Xilinx would be Women’s Bantam Weight Champion Ronda Rousey! Oh yaaaaa…

    For me the FPGA fight really got interesting when Xilinx moved from UMC to TSMC at 28nm. I remember seeing an entire floor at UMC headquarters filled with Xilinx employees. Then disaster struck and Xilinx was late to the 40nm node. Next thing I know the 4[SUP]th[/SUP] floor was empty and Xilinx people were all up in TSMC’s business. Given the close relationship between Altera and TSMC it really was like adding a second wife to your marriage. The result of course was Altera divorcing TSMC and marrying Intel.

    In the FPGA business being first to the new process nodes directly translates into increased market share. Xilinx lost market share to Altera at 40nm but reclaimed quite a bit by beating Altera to 28nm. At 20nm Xilinx beat Altera by more than a year so even more market share will move to Xilinx in the coming quarters.

    And this just in:

    Lift-off! 16nm Zynq UltraScale+ MPSoC ships to customers
    From tapeout to “Hello World” in 2.5 months!


    The full specs are HERE. There is even a YouTube video:

    Of course Apple beat Xilinx to TSMC 16FF+ silicon by a few days but still that is very impressive, tape out to silicon in two and a half months. To be fair, Xilinx was already in production at TSMC 20nm which uses the same backend as TSMC 16FF+ so they did have an advantage over Altera who moved from TSMC 20nm across the street to Intel 14nm. I do know that Altera has taped out at Intel 14nm (with MUCH help from Intel) but I do not know when customers will start getting samples. Soon I hope because competition is what makes the fabless semiconductor ecosystem a force of nature, absolutely.

    The other interesting news from Xilinx is from an email I just got this afternoon:

    Subject: $99 FPGA kit for the curious engineer (that’s you)!
    From: “Xilinx, Inc.”
    Date: Wed, September 30, 2015 12:23 pm

    Okay, I’m not a curious engineer, but even worse I’m a curious blogger, so yes I’m totally going to get one:

    The $99 Arty Evaluation Kit enables a quick and easy jump start for embedded applications ranging from compute-intensive Linux based systems to light-weight microcontroller applications. Designed around the industry’s best low-end performance per-watt Artix®-7 35T FPGA from Xilinx. Arty kit features the Xilinx MicroBlaze™ Processor customizable for virtually any processor use case.

    More information is HERE.

    Also read: Xilinx Skips 10nm

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    Automotive MCU code fault-busting with vHIL

    Automotive MCU code fault-busting with vHIL
    by Don Dingee on 09-30-2015 at 7:00 pm
    Categories: Automotive, EDA, Synopsys

    With electronic and software content in vehicles skyrocketing, and the expectations for flawless operation getting larger, the need for system-level verification continues to grow. Last month, we looked at a Synopsys methodology for virtual hardware in the loop, or vHIL Continue reading “Automotive MCU code fault-busting with vHIL”

    Posted on

    IoT need Low-cost, Low-power…and Silicon Proven IP

    IoT need Low-cost, Low-power…and Silicon Proven IP
    by Eric Esteve on 09-30-2015 at 4:00 pm
    Categories: IP, Synopsys

    Today, IoT devices are available in our daily life through wearable, smart appliances or metering application and some prediction call for 33 billion connected objects, 25 billion being IoT by 2020 (Gartner, 2014). Being very synthetic, IoT device (smart appliance or wearable object) will be wirelessly and securely connected to a “server” (smartphone, PC or else) itself connected to the cloud. By the way, we can expect most of the added value to come from cloud located services, but this scenario appears anyway to be an outstanding opportunity for the semi ecosystem. Building these 20+ billion devices will necessarily generate upside revenue. We think that these devices will have to be secured, extremely low-power… and low-cost. IoT has to be secured because hackers should absolutely not be allowed to meddle in the system. Low-cost to allow an adoption rate as fast as predicted and low-power as the user will not accept to change or charge the battery every day, or even every week (except maybe for wearable). In fact, the development of IoT systems could lead to revolutionary change in H/W and S/W design practice, similar to mobile phone explosion pushing to design incredibly more power efficient SoC in the 2000’s.

    This sounds theory, but the recent launch by Synopsys of Silicon proven IP platform on TSMC 40ULP to support IoT designs is a real case. If you look at the IP market landscape, ARM is the undisputed #1, but only addresses CPU and GPU. By opposition, Synopsys ( #2) supports foundation IP (logic libraries, memory compilers), Non-Volatile Memory (NVM), Data Converters (ADC, DAC) IP, the long list of interface IP (USB, PCIe, DDRn, LPDDRn, SATA, HDMI, MIPI, Ethernet…) and wireless interface IP with BLE solution coming from Silicon Vision acquisition. Synopsys is leader on every IP segment, except CPU/GPU and NVM, and the company can support a complete SoC or ASIC design. Noblesse oblige, the IP vendor had to be the first to port these IP to ultra-low power processes (55nm and 40nm). In fact, more than a simple porting, Synopsys has re-architected and optimized most of these IP for smaller area, low voltage and lower power to propose energy efficient IP.

    To support wireless connectivity, Synopsys has bet that Bluetooth Low Energy (BLE) will be the preferred protocol integrated in IoT systems. This sound like a wise choice to support systems developed today, as WiFi appears to be too power hungry and mesh network like ZigBee too advanced (but this may change as Bluetooth SIG plan to add mesh capability). This picture illustrate a Bluetooth (BLE supporting 4.0, 4.1 and 4.2) demo board on 55 nm.

    Security is more than a concern for IoT… it’s a requirement! “As it’s increasingly important to secure devices against the growing number of data breaches and malicious attacks, IP providers need to stay ahead of the security standards,” said John Koeter, vice president of marketing for IP and Prototyping at Synopsys. Security must be addressed at different levels for IoT, from Firmware integrity assurance, secure bootstrap, ID and authorization and cryptography IP. Synopsys has just announced the industry’s first security IP solutions compliant to the Secure Hash Algorithm-3 (SHA-3) cryptographic standard to enable developers to protect the integrity of electronic information in applications such as message authentication and digital signatures, random number generation and key derivation functions.

    Last but not least, you can expect IoT device to be equipped with sensors capturing data from the real world and you need controlling these sensors and processing data. SoC architect can rely on a complete set of power optimized IP, as above described, and on ARC based sensor & IP control subsystem, to support always-on processing required for sensor fusion and voice recognition applications. ARC EM4 is buss-less architected and hardware accelerators help again decreasing the global processing power consumption. Sensor processing at low cost (low area), optimized for low power is the last piece of the winning puzzle to address IoT application, with energy efficient set of IP, security IP (SHA-2, SHA-3) and modules and wireless connectivity (BLE 4.0, 4.1 and 4.2).

    From Eric Esteve from IPNEST