The recent launch of the Open Connectivity Foundation (OCF) was met first with a wave of “oh good, another IoT consortium”, then “phew, it’s just a rebrand of the OIC”, followed by a bit of confusion over why a few AllSeen Alliance players and some other names jumped in. Is it just a marketing ploy, or is there more to this? Continue reading “OCF shows there may be hope for IoT consortia yet”
The Age of Automotive Electronics
One of Intel’s most advanced fabrication sites is called Ronler Acres, located in Hillsboro, Oregon and I jumped at the opportunity to visit this site on April 26th when members from the SEMI Pacific Northwest Chapter are meeting to discuss a timely topic, “The Age of Automotive Electronics”. The previous SEMI event that I attended was back in October 2015 when the topic was, “The Future of Moore’s Law“. Because of the number of speakers the April event will start out with a breakfast at 7:30AM and continue until 11:30AM.
Our society in America is certainly auto-centric and the trends toward increasing sophistication and automation in our driving experience continues at a fast rate. Just stop and think about all of the changes taking place in the automotive world today:
- Electric Vehicles, from Chevy Volt up to the Tesla
- Autonomous Cars, from companies like: Google, VW, BMW, etc.
- ADAS (Advanced Driver Assist)
- Infotainment
- Connected cars
- Embedded software to control all of the electronics
- Smart Streets
- Smart Lights
Source: The Clemson University Vehicular Electronics Laboratory
Attend this event and you’ll get to hear from industry speakers that work at:
- Intel – the largest employer in Oregon and leading semiconductor company
- Mentor Graphics – the largest EDA company in Oregon
- Gartner – a research and advisory firm
- Drive Oregon – innovation in electric mobility
The first three companies I have heard about before, and even worked at the first two. Although I live in Oregon I hadn’t really heard about Drive Oregon until learning about this SEMI event, so I visited their web site and found this informative 2:45 minute overview video:
Plan to bring along some business cards to hand out while you network with other technology professionals and meet local industry executives.
Registration
You may register online here. Get an early bird rate before April 13th.
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Healthcare Predictive Analytics Insights from Patents
Predictive analytics analyzes current and historical data to make predictions about future events and trends. The predictions are based on the predictive models that are generated from a machine learning technique that recognizes pattern in the current and historical data.
US20140275807 illustrates the predictive analytics application in the personalized medicine. Personalized medicine refers to the use of a diagnostic to target a therapy at a patient exploiting the patient’s individual health data including genotypic that are most likely to benefit from the therapy. Diagnostics is the first step in defining the precise nature of a patient’s disease state. Alzheimer’s disease diagnosis is complex, particularly in the early stages of disease. Alzheimer’s disease is caused by disorders of the brain and central nervous system. The predictive analytics can predict a response of the patient to a particular therapy. Thus, by analyzing the integrated diagnostic data of the patient, the predictive analytics can predict Alzheimer’s disease at a pre-symptomatic stage.
US2016001935 illustrates a system for monitoring a healthcare provider’s operation and performance, and thus, providing tools to make better business decisions, reduce costs, and improve operating efficiency using the predictive analytics. The system receives data associated with the healthcare provider’s operation and performance. The predictive analytics models determine forecast and predict future trends utilizing the aggregated data. Especially, the predictive analytics combines clinical, supply chain and claims data to allow a healthcare provider to compare and contrast how changes in choice of medical devices, medicines, etc. impact both clinical outcomes and profits by physicians, specialties, and payers.
US20150310179 illustrates the software as a service (SaaS) platform for providing analysis of large database regarding patients’ diagnosis and treatment information. The predictive analytics defines decision points that are relevant to clinical decision-making by generating optimal probabilities and likelihood ratios through analysis of information contained in the database.
US20120165617 illustrates a system for early health and preventive care using data from wearable sensors. Data collected from the sensors is transmitted to a mobile cloud computing platform-as-a-service (PaaS). The predictive analytics analyzes the received data to predict diseases and other conditions to which the patient may be predisposed.
Five Reasons to be More Bullish on a 2016 Commercial PC Refresh
Last week’s IDC and Gartner Q4-2015 report on PC sales sent a shock-wave through the industry. The stock market responded with a sell-off of major PC-related names like Advanced Micro Devices, HP Inc. (fka Hewlett-Packard), Intel, Lenovo, and NVIDIA. While I was disappointed in the Q4 numbers, I also have a good grasp of what was behind the numbers, what is standing in the way of better sales, and what’s being done to overcome the challenge. What I’d like to talk about here are a few reasons why I think 2016 could be a good year for commercial PCs, barring a global GDP meltdown. I want to focus on a few workplace trends, specifically around millennials. I do a deep dive in a paper here if you want more details.
Millennials are unlike other generations
The key to what I think could be a key driver of a 2016 commercial PC refresh are millennials– you know, those “kids” born after 1980 and adults at the turn of the millennium. Well, those “kids” are now a major part of the workforce and based on Moor Insights & Strategy estimates, account for 30-40% of IT decisions or purchase influences. That millennial generation grew up with PCs in elementary school, GUIs (graphical user interfaces) in middle school, cellphones in high school, and probably a smartphone in college. Today, they cling to their thin and light smartphones (as I do), own a PC and probably a tablet. Expectations of electronics responsiveness, battery life, industrial design, and battery life expectations are dictated by their smartphones.
Credit: (flickr ITU Pictures)
IT still providing Windows 7 clunkers to users
Most of the installed base of commercial PCs are Windows 7-based systems, three to five years old, are slow, thick and clunky. These aren’t systems that you want to open up around your friends. This is one of the biggest drivers of why BYOD PCs came about. IT’-provided PCs stunk. I think the industry talked a good game about what it wanted to do in IT with all those svelte commercial notebooks, but there were a few issues that stood in the way. Most of enterprise IT weren’t prepared to extensively roll-out the thin and light variants because on the whole, they were consumer converted notebooks that looked more like a MacBook than a commercial PC. Also, IT didn’t buy into the “give me a good PC or I won’t work here” attitude and kept issuing clunkers.
Millennials don’t want to work with clunkers
Well, millennials kept bringing in their consumer laptops and found ways to get work done with a “nice” consumer PC in spite of IT. Millennials have had enough and today, our research suggest that they now have bargaining power in that they don’t want to and won’t work for companies that offer clunky technology. Every shred of research I have done, seen from OEMs and the rest of the industry leads me in this direction. Some IT groups gets it, many don’t and are ironically driven by executive staff and HR to step it up and do something different.
New commercial PCs announced at CES very different
The great news is that from what I saw at CES, for the first time, commercial PCs can be as sexy, cool, responsive, with long battery life as the latest, cutting edge consumer PC and even a smartphone, but with the reliability, durability, service of a managed, commercial PC. These are systems primarily from Dell (Latitude), HP Inc. (EliteBook), and Lenovo (ThinkPad) and in my opinion, can provide enterprise users with the best of both worlds. Intel’s 6th generation processor, code-named SkyLake, is at the heart of most all of these systems, and when you compare Intel SkyLake-based PCs from the last 5 years, there’s literally no comparison.
Intel’s SkyLake processor enables these new devices
Intel’s Skylake processors bring not only integration with Microsoft Windows 10, but also performance improvements in Windows 7 and 8.1 over chips from 5 years ago, the average age of currently installed PCs. Skylake delivers about 25% more performance over Sandy Bridge while also reducing power. GPU performance on current generation Intel integrated graphics is in many cases over 500% better than previous generations of Intel graphics over the course of the 5-year average PC age. The improved graphical performance is partly what has enabled the higher resolutions mentioned earlier.
More importantly, when you look at the new levels of style, battery life, and the new responsiveness, it brings the PC much closer to the expectation of a smartphone. While the PC industry doesn’t like to make comparisons to the smartphone, that’s the expectation reality. That’s the bar. From my point of view, the good news is that the commercial PC industryfinally has that platform that brings the best of consumer with commercial and that’s Intel’s SkyLake. This is one reason why I’m bullish on the 2016 commercial PC refresh.
One big caveat here. If GDP tanks, all bets are off. There is a direct relationship between commercial PCs and GDP so if it gets any worse, it probably won’t be a good year. I’ll hit on some of the other commercial PC drivers in future columns. If you are looking for more details on this, you can find a short paper here.
Solving the Next Big SoC Challenges with FPGA Prototyping
The health of the semiconductor industry revolves around the “start”. Chip design starts translate to wafer starts, and both support customer design wins and product shipments. Roadmaps develop for expanding product offerings, and capital expenditures flow in to add capacity enabling more chip designs and wafer starts. If all goes according to plan, this cycle continues.
Unfortunately “all” rarely goes according to plan especially if you are in a competitive market and designing on leading edge processes. This is where FPGA-based prototyping comes in. A complete verification effort has traceable tests for all individual intellectual property (IP) blocks and the fully integrated design running actual software (co-verification) and is far beyond what simulation tools alone can do in reasonable time. Hardware emulation tools are capable and fast, but highly expensive, often out of reach for small design teams. FPGA-based prototyping tools are scalable, cost-effective, offer improved debug visibility, and are well suited for software co-verification and rapid turnaround of design changes.
Which brings us to this week’s tutorial at DVCON. I hope to see you there:
Solving the Next Big SoC Challenges with FPGA Prototyping and Stratix 10
We’re all too familiar with the fact that large SoC designs present challenges in both design and verification. FPGA prototyping offers obvious advantages for both design and verification but many dismiss the notion of employing FPGA prototyping because of size constraints, hardware scalability, partitioning challenges, performance, debug ability, and in-circuit testing. While previous generations of FPGAs and FPGA prototyping couldn’t tackle large designs, advances in both FPGA and FPGA prototyping technologies and methodologies have given way to breaking through these challenges.
This tutorial will explore the advances of Altera’s Stratix 10 FPGA and the FPGA prototyping techniques and technology that will work with Stratix 10 to accomplish the prototyping of even the largest SoC. Case studies will be provided that will demonstrate how to properly take advantage of Stratix 10 FPGA prototyping for compiling, partitioning, and debugging across multiple devices.
THURSDAY March 03, 2:00pm – 5:30pm | Sierra
Speakers:
Toshio Nakama – S2C, Inc.
Manish Deo – Intel/Altera Corp.
If you get the chance to meet Toshio after the tutorial I would highly recommend it. He is the Co-founder and CEO of S2C, Inc. and has over 18 years of experience in the electronic design automation industry as well as FPGA architecture and design. Prior to S2C, Toshio held the positions of Asia director of sales and field applications engineering manager at Aptix and worked at Altera. Toshio has an EMBA degree from CEIBS and a BSEE from Cornell University.
DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsorsDVCon Europe andDVCon India. For more information about Accellera, please visitwww.accellera.org. For more information about DVCon U.S., please visitwww.dvcon.org. Follow DVCon on Facebookhttps://www.facebook.com/DVCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.
Enterprise SSD SOC’s Call for a Different Interconnect Approach
The move to SSD storage for enterprise use brings with it the need for difficult to design enterprise capable SSD controller SOC’s. The benefits of SSD in hyperscale data centers are clear. SSD’s offer higher reliability due to the elimination of moving parts. They have a smaller foot print, use less power and offer much better performance. SSD’s are also more scalable, a big plus where storage needs run into the petabyte range.
Nevertheless, SSD’s create the need for more complex and sophisticated controllers. Unlike early SSD implementations that used SATA, SAS or Fibre Channel to connect to their hosts, enterprise SSD use NVMe protocol to directly connect to PCIe. NVMe was developed specifically for SSD memory and takes advantage of its low latency, high speed and parallelism. The table below from Wikipedia shows the comparison.
Enterprise SSD controllers connect to many banks of NAND memory and deal with low level operations such as wear leveling and error correction, both of which have special requirements in this application. The SSD controller must offer low latency, extremely high bandwidth, low power, and internal and external error correction.
A large number of unique IP blocks must be integrated to deliver a competitive SSD controller SOC. Here is a short list of necessary IP’s that are commonly used: ARM R5/7, PCIe, DDR3/4, NVMe, DMA, RAM, SRAM, RAID, NAND, GPIO, ECC and others. The parallel operation of these IP blocks presents a significant design problem for IP interconnection and internal data movement.
Designing the interconnections between all the functional units has become one of the most critical aspects of these designs. Due to larger IP blocks with wide buses and increasing need for interconnect using wires that are not scaling with transistor sizes, the design effort and chip resources consumed by on-chip interconnections are becoming a large burden to design teams.
Buses and crossbars are running out of steam in these newer designs. For example, going to AMBA 4 AXI for 64 bits requires a width of 272 wires, and 408 wires for 128 bits of data. The other problem is that many of these wires are idle for much of the time. For example, a four cycle burst write transaction only uses the 56 wire write address bus in 25% of the cycles.
Networks on Chips (NoC) dramatically reduce the difficulties that would be encountered with large bus structures. Arteris, a leading provider of NoC IP, has just published a white paper on the advantages of using their FlexNoC to facilitate implementation of enterprise SSD controllers. The biggest advantages come from simultaneously reducing the widths of the block interconnections and tailoring them to the predicted traffic. It’s well understood that the earlier in the design process issues are addressed the easier it will be to deal with the downstream effects of that issue. Instead of waiting for the P&R stage to grapple with interconnect across the chip, FlexNoC planning and implementation starts at RTL, making the process more efficient and easier.
FlexNoC works by converting a wide variety of IP protocols at their source to agnostic serialized packet data and routing it to its target, where is it reassembled upon delivery. There are RTL elements required for the NoC to operate but the overall area required by the NoC IP and interconnect wires is significantly less than the equivalent bus or crossbar structures. Because the NoC data can be pipelined and buffered, it is actually faster than high drive strength busses. The NoC RTL can be synthesized and placed so that it conforms to the predefined routing channels.
The overall effect is less routing congestion, leading to a smoother back end implementation flow. The resulting design benefits from less latency and even more robust data integrity due to built in error correction within FlexNoC.
To gain a deeper understanding of the benefits of using FlexNoC I suggest reviewing the Arteris white paper located here. There are a number of additional benefits and implementation details that are covered in this and the other available Arteris downloads
Multi-Level Debugging Made Easy for SoC Development
An SoC can have a collection of multiple blocks and IPs from different sources integrated together along with several other analog and digital components within a native environment. The IPs can be at different levels of abstractions; their RTL descriptions can be in different languages such as Verilog, VHDL, or SystemVerilog.
Continue reading “Multi-Level Debugging Made Easy for SoC Development”
FPGA tools for more predictive needs in critical
“Find bugs earlier.” Every software developer has heard that mantra. In many ways, SoC and FPGA design has become very similar to software development – but in a few crucial ways, it is very different. Those differences raise a new question we should be asking about uncovering defects: earlier than when? Continue reading “FPGA tools for more predictive needs in critical”
ASML and IMEC EUV Progress
Day 1 of the SPIE conference featured a number of customer updates on the status of their EUV programs. On Tuesday morning we got to hear ASML’s update on their work.
Continue reading “ASML and IMEC EUV Progress”
Reinventing Power Management ICs for Mobile
Semiconductor startups are becoming rather rare in Silicon Valley, otherwise known as the cradle of technology innovation. In an era where social media and cloud-based software startups are sprouting in every nook and corner of the Valley, it is extremely difficult to get venture capital funding for semiconductor startups, in part due to the high capital investment. Yet there is hope that this may change. The battery-centric power conundrum is now opening up a new window of opportunity for semiconductor startups in the area of space-constrained mobile and wearable devices.
Lion Semiconductor, for instance, is a startup that is trying to reinvent the power management IC (PMIC), one of the biggest chips on a mobile phone. The San Francisco–based company claims to have reduced the PMIC footprint and thickness by two to three times, which, in turn, will allow mobile handset manufacturers to make the battery larger and longer-lasting.
Figure 1: Lion Semiconductor is developing smaller, thinner PMICs for mobile systems
The timing for Lion Semiconductor seems to be just right. Mobile consumables are trending and it is becoming extremely critical to manage the different voltages in devices and to manage the power with minimal energy loss. With increases in design complexity, lower technology process nodes, lower noise thresholds and the increase of analog and RF components in the SoC, there is a growing need for proper generation and control of low voltages without any significant power loss.
The constant overheating issues in smartphones are a testament to how a more innovative PMIC solution could help mobile phone hardware create a better balance between performance and power. In a wearable device, the value proposition of a smaller PMIC is even more crucial: it will lead to a smaller wearable device itself.
Reinventing PMIC
In a mobile handset, the power management IC takes voltage from the battery and delivers it to different chips across the smartphone design footprint. However, the use of discrete components like inductors creates inefficiencies inside the PMIC. The alternatives, like low-drop-out regulators (LDOs), come with lower efficiencies, while the use of switching regulators makes PMICs bulky and expensive.
Lion Semiconductor’s answer to this power puzzle: a new breed of power management ICs that use a different circuit design and manufacturing process to meet the more demanding mobile specifications. The power converter design would not require any discrete passives-like inductors (like LDOs), but would offer the efficiencies of switching regulators, merging the advantages of LDOs and switching regulators.
Lion Semiconductor’s co-founder and CEO, Wonyoung Kim, designed an integrated voltage regulator when he was a graduate student at Harvard University. He was then aiming to create a PMIC that does not require discrete passive components. The firm’s other co-founder, Hanh-Phuc Le, was carrying out similar work at the University of California, Berkeley.
Another Berkeley Ph.D. student, John Crossley, later joined them and a PMIC company specializing in solutions for mobile devices was born. Here, it’s worth noting that the battery in a smartphone has to serve a wide range of input and output voltages, and that it is challenging for the PMIC to maintain high efficiencies across this wide range.
Figure 2: The DC-DC converter chip that Kim developed at Harvard a few years back
Lion Semiconductor is tackling that challenge head-on through their proprietary technologies in circuit design and process technology. Lion Semiconductor has successfully verified several fully-functional silicon prototypes and is preparing to start sampling to customers soon.
Do small design startups also need data management tools?
Kim and his friends at Lion Semiconductor had been using the Cadence Virtuoso analog/mixed-signal design platform since their college days and it was only natural that they turned to Cadence for EDA tools. In addition to other tools, Lion Semiconductor uses ClioSoft’s SOS SoC design data management tool, which is integrated into the Cadence Virtuoso platform.
Figure 3: ClioSoft Inc. authored the chapter on SoC design data management in the “Mixed-signal Methodology Guide” published by Cadence
Does it seem strange for a semiconductor chip startup like Lion Semiconductor to use a sophisticated design data management tool created primarily for the semiconductor industry?
“Not really,” said John Crossley, now Lion Semi’s vice-president of engineering. “It just shows how crucial it is to efficiently manage data in the development of a complex chip. Inevitably, the tight schedules in the mobile world and the very short market windows make it imperative that engineering teams are working on the correct version of design data and that all design team members are in sync.”
The Fremont, California–based ClioSoft helps companies like Lion Semiconductor through a flexible licensing program that features low overhead and greater setup and administration support for startups. The SOS design management platform from ClioSoft has built-in integrations with EDA tools and a flexible architecture, making it easily customizable for small and big semiconductor companies alike for their complex design flows.
Lion Semiconductor is planning to set up a design center overseas, which would make it even more crucial to have an efficient design data management system in place.
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