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Next-Generation Formal Verification

Next-Generation Formal Verification
by Daniel Nenni on 12-14-2018 at 12:00 pm
Categories: EDA, Synopsys

As SoC and IP designs continue to increase in complexity while schedules accelerate, verification teams are looking for methodologies to improve design confidence more quickly. Formal verification techniques provide one route to improved design confidence, and the increase in papers and interest at industry conferences like DVCon and DAC reflect the growing usage of formal verification tools in the industry. Despite the increase in usage of formal verification, there are still few opportunities for verification engineers interested in formal techniques to exchange ideas, knowledge, and best practices.

The Synopsys VC Formal Special Interest Group (SIG) events are a step towards broadening knowledge of formal verification. In the inaugural year of the VC Formal SIG, Synopsys held events in India, Japan, and the United States. In all three events, VC Formal customers shared their experience and successes in using VC Formal to address verification problems, alongside Synopsys AEs who presented new or advanced applications of formal verification. The most recent event was held in November in Santa Clara, California, with a keynote discussion from Sean Safarpour and Pratik Mahajan from Synopsys discussing the history and future of formal verification. The Santa Clara event showcased experts from AMD, ST Microelectronics, Qualcomm and Juniper Networks, highlighting the use of formal verification to solve challenging verification problems.

Formal Sign-Off of a Control Unit (AMD)
Wayne Yun discussed the verification of a complex control block using formal methods. The block included an AHB arbiter, microprocessor, data collector, accumulator, and glue logic. First, each block was considered in isolation. Formal techniques such as formal model creation, case splitting, invariant identification, and symbolic variables were applied to each sub-block. Assume-guarantee reasoning validated assertions on interfaces between sub-blocks. He also discussed how AMD used the coverage collection, overconstraint analysis, and fault injection features of VC Formal to signoff the design. VC Formal formal core analysis and fault injection identified several areas that required additional assertions. At the end of the project, over 94% of assertions were proven, all blocks had full formal core coverage, and most blocks detected over 99.8% of injected faults.


Formal Verification of a GPU Shader Sequencer (AMD)Chirag Dhruv and Vaibhav Tendulkar showed the benefits of VC Formal FPV App’s bug hunting effort to find bugs in a GPU shader sequencer. A wide variety of parallel instructions, asynchronous events, and dynamic configuration changes make simulation coverage closure difficult in this block. Sub-block decomposition allowed quick bug exposure and rapid iteration time. Formal reachability analysis, COI coverage analysis, and formal core coverage analysis identified dead code and design areas requiring more assertions. Formal verification found over 30 RTL bugs, several which would have been difficult to discover through simulation, absolutely.

Accelerate Digital IP Formal Verification with Machine Learning Technology (ST Microelectronics)
Giovanni Auditore described a shift of verification resources within ST towards formal verification. They used Verdi Planner to combine the formal and simulation verification plans, allowing a single view of verification progress as formal use increased from project to project. A variety of VC Formal Apps were applied to the design, including FCA for unreachability analysis, FRV for register verification, and FPV for property and protocol verification. Giovanni also described how the Regression Mode Acceleration (RMA) feature of VC Formal sped up formal regression. RMA uses machine learning techniques to accelerate proof time on future runs of the same or incremental versions of RTL. After applying RMA learning to an initial release of RTL, proof time for subsequent RTL releases took 1/3 the time as running identical regressions without RMA. RMA also reduced runtime of fault injection qualification from 21 to 16.5 hours.

Verification Sign-Off with Formal (Qualcomm)
Anmol Sondhi shared how to layer various coverage metrics available in VC Formal to build confidence in assertion quality throughout the design cycle. Early in the project, cone-of-influence based property density will identify testing holes in the design. Unreachability analysis through the FCA App, and over constraint analysis identifies areas in the design where formal stimulus won’t reach, allowing targeted review of RTL and formal constraints. Formal core coverage represents the logic that formal engines use to prove a property. Uncovered areas represent potential test holes. Finally, fault injection identifies areas where modifications in RTL behavior trigger assertion failures. He also showed how RMA resulted in between 2X and 10X improvement in regression runtime. Using VC Formal, the example project achieved over 99.5% property density and 90% formal core coverage and identified only 12 areas of undetected faults that required further investigation.

Designing for Formal Verification (Juniper Networks)
Anamaya Sullerey explained how RTL designers can be involved with formal verification through design methodology and short, frequent formal regressions of RTL. He described how changing an event driven implementation with a complicated state machine and complex, interacting side effects to a functionally driven implementation with lots of small modules that perform simple tasks can simplify and accelerate formal verification. Efficient decomposition of the design allows for meaningful sub-block formal verification regressions of no more than five minutes. Other recommendations for formal friendly design include early parameterization of RTL code, isolating complex blocks into separate modules for easy abstraction, creating meaningful intermediate expressions, and coding assertions for design invariants such as one-hot bit vectors. With a high level of formal friendly design methods, designers or verification engineers could quickly build module level formal testbenches that catch a majority of bugs with five minutes of regression time.

The Synopsys formal verification team presented tutorials on datapath operations and how to discover design invariants. JT Longino talked about using Synopsys tools for formally proving datapath operations. Datapath correctness continues to be a challenge for the industry. High confidence in datapath operations is difficult or impossible to achieve using simulation, but datapath operations have historically exceeded the capacity of formal property verification tools. Synopsys HECTOR technology provides users the ability to prove equivalence between an implementation RTL design and a reference design. The two designs can have different latencies, and the reference design can be untimed C or C++ code. The new VC Formal DPV App integrated HECTOR technology into the VC Formal GUI, allowing formal verification engineers to work on datapath verification problems in a familiar environment.

Iain Singleton described how to use VC Formal to discover design invariants to help converge complex properties. Invariants describe properties that remain unchanged when a specific transformation is applied and can restrict the state space of subsequent proofs if used as assumptions. Although they are powerful tools or assisting convergence, invariants can be difficult to identify and write. The VC Formal Iterative Convergence Methodology (ICM) provides users a methodical, tool-assisted approach to identifying design invariants. Using ICM, convergence time for a selected set of difficult properties was reduced from over three hours to around one minute. To learn more about VC Formal and to stay up to date on dates on VC Formal SIG 2019 events, visit HERE.

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Embeddable FPGA Fabric on TSMC 7nm

Embeddable FPGA Fabric on TSMC 7nm
by Tom Simon on 12-14-2018 at 7:00 am
Categories: Achronix, AI, eFPGA, FPGA

With their current line-up of embeddable and discrete FPGA products, Achronix has made a big impact on their markets. They started with their Speedster FPGA standard products, and then essentially created a brand-new market for embeddable FPGA IP cores. They have just announced a new generation of their Speedcore embeddable FPGA IP that targets leading edge compute applications such as AI/ML. More than just being a process node advancement, they have made a number of strategic architectural changes to improve performance and adapt to certain classes of problems.

Yes, as you might expect this announcement includes moving to the latest process node, TSMC 7nm, and there will be a back port to 16nm later in 2019. However, the really interesting stuff in this announcement has to do with further improvements in the already optimized architecture of the fabric.

I had a chance to speak to Robert Blake, Achronix CEO, at the time of the announcement to gain deeper insight into the specifics. He mentioned that they have successful 7nm validation silicon back that meets their target specifications. The motivation for many of the changes in this new generation are based on the AI/ML market and the big changes in how FPGA technology is being used.

FPGAs have made a dramatic shift over the decades from glue logic and interface uses to becoming a major element in data processing, such as networking and AI. Microsoft demonstrated how FPGAs offer huge acceleration for compute intensive applications. Classic CPUs have seen their year-to-year performance gains flatten out. With this there has been a concomitant growth of the use of specialized processors such as GPUs to fill the gap. FPGA’s represent an even more flexible tool for implementing computational processing. Achronix likes to point out that CPUs are rapidly becoming FPGA helpers, that can deal with exceptions, but are not necessarily in the main data path as much anymore.

The beauty of embeddable FPGA fabric IP is that significant overhead of an off-chip resource is avoided. These include off chip driver loads, board real estate, and interface speed limits.

The Speedcore 7t, which is built with their Gen4 architecture, provides significant PPA improvements. Robert told me that they see simultaneous gains in performance, power and area, namely a 60-300% boost in performance and a 50% decrease in power with an area decrease of 65%. Any one of these would be noteworthy, but they have a combined win. Robert walked me through some of the changes that contribute to these numbers.

Based on the needs of several important applications, Achronix has added or enhanced certain logic blocks. For instance, there is an 8-1 mux, which is critical for networking applications. Another is an 8-bit ALU that is heavily used for AI/ML. Robert also talked about their bus max function, dedicated shift registers, and LUT changes, all of which improve the compute power of their FPGA fabric.

Robert talked about numerous other additions, such as their programmable bus routing. This 4-to-1 bus routing capability can be cascaded to create wider busses. This will save LUT resources and offers a 2X performance improvement.

Going one step further, they have added a new compute block – a Machine Learning Processor (MLP). It is optimized for neural network (NN) matrix vector multiplication. It is clocked at 750 MHz and has flexibility in the number formats is can handle: Fixed point, Bfloat16, 16-bit half precision FP, 24-bit FP, block FP. The flexibility provided with varying configurations, allows customization to adapt to different NN algorithms. It also provides future proofing, because the programmable array can be altered as NN algorithmic technology advances.

There is so much in this announcement, I suggest referring to the Achronix website for all the details. However, it is clear that Achronix intends to maintain its technical and business advantage in this space using a wide range of targeted technical improvements. Rather than rest on their laurels, they are using their experience to help meet the emerging computational requirements for AI/ML, which is poised to become pervasive.

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Sequential Equivalency Checks in HLS

Sequential Equivalency Checks in HLS
by Alex Tan on 12-13-2018 at 12:00 pm
Categories: EDA, Siemens EDA

Higher level synthesis (HLS) of an IP block involves taking its high-level design specification –usually captured in SystemC or C++, synthesizes and generates its RTL equivalent. HLS provides a faster convergence path to design code stability, promotes design reuse and lowers front-end design inception cost.

HLS and Mentor Catapult Platform
The current rise in the HLS adoption has been partly attributed to the availability of verification solutions, which facilitate the validation of the generated RTL codes against the high-level reference design. Both design abstractions can be validated through either simulation based verification (such as coverage metric and assertion driven), or formal verification method to check for their equivalencies.

Mentor’s Catapult® HLS Platform provides a complete C++/SystemC verification solution that interfaces with Questa® (or third party simulators) for RTL verification as shown in figure 1. The platform consists of a design checker (Catapult DesignChecks or CDesign Checker), a coverage tool (Catapult Code Coverage or CCOV), a high-level synthesis (Catapult HLS) and a formal tool SLEC HLS (Sequential Logic Equivalence Check).

Logic and Sequential Transformations
During RTL-GDS2 design implementation, timing optimization frequently necessitates logic restructuring and transformation to meet PPA (Power Performance Area) tradeoffs. While critical timing paths can be resolved through the manipulation of logic cone topology –such as buffering, drive strength adjustments, better resource sharing, and an interconnect layer promotion, sequential related design manipulation can provide opportunities for solving critical timing paths that otherwise impossible to tackle. Such design transformation is hardly available in the later stage of gate level timing optimization as it may introduce state changes and complicates the verification tasks.

Several timing driven sequential modifications include pipelining (managing number of stages along data or control paths to meet throughput target); register retiming (shifting register to balance logic cone latency); state recoding in FSM block (such as from binary-encoded to one-hot implementation); and resource scheduling (what-if scenarios to meet optimal area and performance targets).

Furthermore, a number of design refinements might also introduce changes in sequential element count such as a block interface conversion from abstract data types to bit-accurate busses and augmenting test mode operation involving scan path logic insertion.

Designer also run Catapult HLS to generate power optimized verification ready RTL, which involves sequential transformations due to enable manipulation technique (enable extraction or strengthening) –yielding further clock gating that reduces switching activities. Figure 2 shows the additional clock gatings due to sequential analysis.

All of the previously described design changes alter the maps between registers of the two design abstractions, and render traditional combinational equivalence checkers ineffective. Instead, designers could run SLEC HLS to validate between C++/System C to RTL as well as RTL versus RTL (before and after an incremental power optimization).

The Mechanics of SLEC HLS
Unlike the traditional equivalence checker for combinational logic, proving equivalency across two design abstraction such as C++ versus RTL requires a different approach such as identifying the sequential differences. SLEC HLS has advanced analysis that allows designers to explore what-if refinements that normally might trigger traditional equivalence checkers to generate a false positive. It employs a fine-grain partitioning of design sections in order to provide scalability in handling large design codes.

As illustrated in figure 3, fracturing a function to its associated basic blocks, SLEC HLS analyzes and map them to its corresponding control FSM to schedule the dataflow analysis. Comparison is then performed at the interface of these “state-like” basic blocks along the time axis using micro transactions. HLS synthesis provides both basic block boundaries and information about the micro transactions.

Running and Analyzing SLEC HLS Results
SLEC HLS run setup is quite straight-forward and is achieved by black-boxing non-synthesizable design parts including large memory blocks, and specifying the same reset states and sequences usually captured for synthesis. Other design setting such as state correspondence, which reduces verification complexity as well as clocking and port mapping are automatically derived from the high-level reference codes. To improve run time and quality of results, the tool uses function-based partitioned blocks in the form called CCOREs (Catapult C Optimized Reusable Entities) –which are called for multiple times in the design, to perform a hierarchical verification.

At SLEC HLS run completion, there are 3 possible outcomes: a full proof of equivalency, a mismatch, or a partial proof –which indicates that some remaining points in logic being compared needed further analysis. A neat feature of SLEC HLS is when a mismatch occurs. In this instance, it will generate counter example testbenches containing stimulus sequences that designers use to trace design differences. These testbenches include flip-flop initialization values and all primary input stimuli intended to demonstrate the difference –which are simulation ready, and can be used for further analysis with functional verification tool. Subsequent fixes to mismatches may involve source code or I/O cycle/sampling adjustments, constraint changes and a rerun.

In the case of a partial proof, SLEC HLS will generate a formal coverage report that quantifies the exploration of all possible inputs and states, which is helpful to root-cause issues such as dead-code situation. Such information can also be used to identify incorrect assumptions or constraints that were provided to SLEC HLS such as conflicting dual assignments to an input. Hence, adding a formal verification in the flow reduces the need to do full-blown RTL simulation and cutting the overall verification time.

As part of the Catapult HLS Platform integrated verification solution, SLEC HLS provides designers with formal validation of designs across different abstractions (C++, SystemC, RTL) or refinement stages (pre- vs post-power optimization). Such vectorless validation can be used to complement simulations to deliver a more comprehensive verification and reducing the overall efforts and cost.

Check HERE for HLS and HERE for SLEC HLS.

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Big Data Analytics in Early Power Planning

Big Data Analytics in Early Power Planning
by Bernard Murphy on 12-13-2018 at 7:00 am
Categories: Ansys, Inc., EDA

ANSYS recently hosted a webinar talking about how they used the big-data analytics available in RedHawk-SC to do early power grid planning with static analytics, providing better coverage than would have been possible through pure simulation-based approaches. The paradox here is that late-stage analysis of voltage drops in the power distribution network (PDN), when you can do accurate analysis, may highlight violations which you have no time left to fix. But if you want to start early, say at floorplanning where you can allow time to adjust for problems, you don’t have enough information about cell placement (and therefore possible current draw) to do accurate analysis.

ANSYS have a solution based on something they call Build Quality Metrics (BQM). In the webinar they talk about the general methodology. There are multiple ways to approach BQM; one starts with a static analysis of the design (no simulation) and doesn’t require placement info. For this you build heatmaps based on simultaneous switching (SS) calculations, likely issues in the planned power grid and likely timing criticality. For SS, you calculate peak current per cell based on library parameters and operating voltage. You then combine these values for nearby instances which have overlapping timing windows (taken from STA analysis), summing these currents to generate an SS heatmap.

Next you want to look at where you may have excessive IR drop in the planned grid. In BQM, since you don’t yet have cell instance placements you fake it by placing constant current sources at a regular pitch on the low metal segments and then do a static solve to generate an IR-drop heatmap. The evenly-spaced current draw won’t match exact cell instance current draws but it should be a reasonable proxy, allowing these heatmaps to be generated early in implementation and refined as placement data becomes available.

You can further refine this analysis using timing slack data generated from STA analysis data to prioritize timing critical cases. Combining all these heatmaps together generates the ultimate BQM heatmaps. ANSYS and their customers have shown that there is excellent correlation in observed hotspots between these and heatmaps generated through the traditional RedHawk (non-SC) path.

All of this analysis leverages the ANSYS Seascape architecture underlying RedHawk-SC to elastically distribute compute to build heatmaps. Which means that analysis can run really quickly, allowing for an iterative flow through block place and route. Which is really the whole point of the exercise. Instead of building a PDN based on early crude analyses like shortest path resistance checks, then doing detailed analysis on the finished PnR to find where you missed problems with real vectors, the BQM approach provides high coverage earlier in the flow, without need for vectors or cell placement, enabling incremental refinement to the PDN as you approach final PnR.

ANSYS reports that runtime of the BQM approach can be 3X faster than a dynamic analysis based on just a single vector. Note that the static approach in BQM provides essentially complete instance coverage (all instances are effectively toggled) whereas dynamic coverage is inevitably lower. You can raise dynamic coverage by adding more vectors but then runtime becomes even higher. Overall, you can build and refine your PDN early, avoiding late-stage surprises, you can do this quickly enough that it makes sense as an iterative step in the PnR flow. You’ll still do signoff at the end with whatever method you feel comfortable. Just without nasty surprises. What’s not to like?

ANSYS tells me they have scripts to automatically setup the SC flow from your RedHawk setup, so it seem like there’s really no excuse not to give this a whirl 🙂 You can register to watch the webinar HERE.

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DVCon is coming in February, now is the time to register early

DVCon is coming in February, now is the time to register early
by Daniel Payne on 12-12-2018 at 7:00 am
Categories: EDA, Events

As 2018 wraps up this month it’s time to start thinking and planning for 2019, and if you work in the Silicon Valley then you’ll want to consider adding the 31st annual DVCon event planned for February 25-28 in San Jose. Surveys have shown for some time now that verification tasks actually take up more time on a SoC project than design does, so it makes sense to find out what’s new for verification engineers through:

  • 39 Technical papers
  • 25 Poster sessions
  • Two Panel discussions
  • Four Tutorials
  • Eight Short workshops


The Accellera Systems Initiative is the sponsor for DVCon, and they grind out the much needed standards so that our industry doesn’t get polarized by proprietary and conflicting software automation approaches.


The Universal Verification Methodology (UVM) can track its history from the Open Verification Methodology (OVM) and even the e Reuse Methodology (eRM) from Verisity back in 2001. Cliff Cummings leads a tutorial on Monday, February 25th all about UVM:

  • “Gain Valuable Insight into the Changes and Features that are Part of the New IEEE 1800.2 Standard for UVM and How to Mae the Most of Them”

Cliff Cummings is President of Sunburst Design, Inc., a company that specializes in world class Verilog, SystemVerilog, UVM Verification and synthesis training. Mr. Cummings is an independent consultant and trainer with 33 years of ASIC, FPGA and system design experience and 23 years of Verilog, SystemVerilog, synthesis and methodology training experience. Mr. Cummings has completed many ASIC designs, FPGA designs and system simulation projects, and is capable of answering the very technical questions asked by experienced design engineers.

For keynote this year you’ll hear about the topic of the “Thriving in the Age of Digitalization” from Fram Akiki, VP Electronics & Semiconductor Industry for Siemens PLM Software. Fram’s background includes 21 years at IBM spanning roles in analog IC design, microprocessor manager and GM. His next 13 years were at Qualcomm as a director of operations, then head of the mobile computing connected products.

There’s a buzz around all things RISC-V, so check out the panel discussion on Wednesday, February 27th entitled, “Verification and Compliance in the era of open ISA- is the Industry ready to Address the Coming Tsunami of Innovation?“. Moderator Mike Demler is a Senior Analyst at The Linley Group, and the panelists include:

  • Emerson Hsiao, Andes Technology
  • Adnan Hamid, Breker Verification Systems, Inc.
  • Rob Shearer, Facebook
  • Simon Davidmann, Imperas Software Ltd.
  • Neil Johnson, XtremeEDA Corp.

Neil Johnson is active on Twitter and his tweets are focused on functional verification.

Networking throughout the conference is available during the Expo on Monday from 5PM to 7PM, then again on Tuesday and Wednesday from 2:30PM to 6PM. View the complete agenda online here, and register online now to get the best prices.

DVCon is the premier conference for discussion of the functional design and verification of electronic systems. DVCon is sponsored by Accellera Systems Initiative, an independent, not-for-profit organization dedicated to creating design and verification standards required by systems, semiconductor, intellectual property (IP) and electronic design automation (EDA) companies. In response to global interest, in addition to DVCon U.S., Accellera also sponsors events in China, Europe and India. For more information about Accellera, please visit www.accellera.org. For more information about DVCon U.S., please visit www.dvcon.org. Follow DVCon on Facebook https://www.facebook.com/DvCon or @dvcon_us on Twitter or to comment, please use #dvcon_us.

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56G and 112G SerDes Where the rubber meets the road

56G and 112G SerDes Where the rubber meets the road
by Tom Simon on 12-11-2018 at 12:00 pm
Categories: eSilicon, IP, Semiconductor Services

No matter how high the processing capability of a chip, its overall performance is limited by IO speed. This is very similar to a car with low performance tires, a powerful engine will not be able to transfer its energy to the ground effectively. There is quite literally a race going on between core processing and IO speeds for transferring data on and off of chips. AI, autonomous vehicles, 5G and other advances are pushing a never-ending drive to increase data transfer rates.

One interesting area of innovation is in cell towers, where the radios used to sit in a box on the ground and high power RF signals were carried over copper to the antennas. This architecture created power and cooling problems among others. Common Public Radio Interface (CPRI) uses optical cables to carry the digitized RF signal to an RF power amplifier on the cell tower mast. Interestingly when this happened, carriers realized that they could architect their fronthaul to move the Base Band Units (BBUs) to or near the central office. The BBUs rely on high speed data links to get their job done.

Another area of innovation is the advent of Top Rack (TOR) switching. While it shortened the distance from server blades to the data switches, it also comes with a huge upward demand in transfer rates. The pivotal player in all these and many other changes in data transmission paradigms is the ubiquitous SerDes. Big changes have been needed to move from 28G to 56G and 112G and at the same time to limit cross talk and noise as the number of lanes increases.

High speed SerDes are needed not just for short reach connections, the demand for longer lines adds more consideration in SerDes Design. Other requirements for SerDes are back compatibility for lower data rates andlegacy protocols, and the ability to support copper and fiber. eSilicon, a leading provider of complex FinFET ASICs, has put out an interesting article discussing the complexities of designing SerDes for the leading-edge ASICs they deliver. This is in part due to their presence in the networking, AI and 5G markets as silicon a provider.

In their article, they touch on the need to move to PAM4 from the older PAM2/NRZ operation. Multiple bit-levels add complexity, with level detection made more difficult due to switching levels closer to threshold voltages. The leading edge SerDes, operating at 56G and 112G, are both digital and analog, making their design a challenging prospect.

eSilicon also talks about the increased need for on-chip testing and verification features. They have added full speed digital and analog loopback, and also a variety of smart monitoring features. With all this said, eSilicon has 7nm SerDes that are proven in silicon.

Innovation is needed to keep up with the demands for moving data. Ethernet is moving from 100GbE to 400GbE. The data rates for CPRI, mentioned above, are pushing upward from 25Gb/s to 50Gb/s. Back planes and data centers are soon going to be running at 25.6 and 51.2 Tb/s. More data sources, more data consumers, faster networks and high volumes of video and audio real-time data are all pushing technology forward. The eSilicon paper on 56G and 112G SerDes is pretty interesting and worth reading through to get an idea of what is needed to make fast chips move data effectively.

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IEDM 2018 – ASML EUV Update

IEDM 2018 – ASML EUV Update
by Scotten Jones on 12-11-2018 at 7:00 am
Categories: Lithography, Semiconductor Services, TechInsights
10 Comments

At IEDM last week Anthony (Tony) Yen, Vice President and Head, Technology Development Centers Worldwide for ASML presented a paper entitled “EUV Lithography at Threshold of High-Volume Manufacturing” authored by Anthony Yen, Hans Meiling, and Jos Benschop. At IEDM I had a chance to sit down with Tony and discuss the paper and the current status of EUV.

Before I summarize my discussion with Tony, I want to comment on where I see EUV in the industry today. Leading-edge logic is going to be the first to implement EUV. Current state-of-the-art logic processes make extensive use of multi-patterning in the Middle-Of-Line (MOL) and Back-End-Of-Line (BEOL) and that is where we will see EUV implemented first. Samsung is the most aggressive in their approach with their first generation 7nm logic process utilizing EUV for 7 layers, Samsung is ramping that process up now. TSMC is offering a second generation 7nm process with 6 EUV layers and that process is due to ramp early next year. Intel has announced their 7nm process will also utilize EUV with a planned introduction date of 2020 although many observers question whether they will meet that date. I have heard the Intel process will use EUV for 6 layers, but it is still early, and I am not sure how credible that forecast is. Samsung and TSMC both have 5nm processes due to begin risk starts in late 2019 with more extensive EUV usage. Clearly EUV is on the threshold of high-volume manufacturing. In my ISS presentation from January 2018 I projected nine hundred thousand wafers will be processed with EUV in 2019 and over two million wafers in 2020. My ISS presentation is available here.

ASML has previously announced the availability of a 250-watt EUV source and that source is now deployed in the field. What is new in the current presentation, is that systems in the field are now maintaining 250 watts. Figure 1 illustrates output power stability at multiple customer systems.

Figure 1. Stable performance at >250 watts on multiple customer systems.

New debris mitigation strategies are improving collector cleanliness. ASML has a goal of only a 0.1% degradation in the mirror per giga pulse of laser output and today is better than 0.3%.

In late 2017 ASML announced their 125 wafers-per-hour (wph) milestone had been reached running source power at 195 watts with 96 steps, 20mJ/cm[SUP]2[/SUP] dose and no pellicle. Early this year throughput was improved to 140 wph at 246 watts with 96 steps, 20mJ/cm[SUP]2[/SUP] dose and no pellicle. Authors note, for logic devices, steps are roughly 110 per wafer and while initial EUV implementation are being done without a pellicle a pellicle is really needed. With a pellicle throughput drops to 116 wph. Figure 2 illustrates the achieved throughput.

Figure 2. EUV throughput.

In our discussions Tony mentioned that the 3400B is shipping today (the system used for the results in figure 2) and that next year the 3400C will start shipping with 170 wph throughput. The 3400C is the same source power as the 3400B but has lower overhead and better lens transmission.

There is also work being done in improving the source power. 410 watts has been demonstrated for short bursts at the factory and ASML believes they can get to 500 watts.

Pellicle development continues. The current polysilicon-based pellicle provides 83% transmission and has now been shown to stand up to 250 watts. Work on a 90% transmission pellicle continues.

CD control and overlay are both excellent and customers are running 36nm pitch today.

The current photoresist of record are Chemically Amplified Resists (CAR). Work with inorganic photoresist have shown single digit nanometer features with improved line edge roughness. Interestingly in his Keynote at IEDM, Samsung Foundry President ES Jung projected that inorganic resists would replace CAR for second generation EUV. Figure 3 illustrates the results of resist screening that shows better LER results with inorganic resist and good line/spaces down to a 20nm pitch although at a high dose of 67mJ/cm[SUP]2[/SUP].

Figure 3. Photoresist comparison.

EUV masks are reflective masks with complex absorber stacks. The height of the stacks creates 3D effects in the mask. There is work under way to find more absorptive materials that would allow thinner layers. Nickel and cobalt offer improved absorption but are difficult to etch. Imec is working on alloys as a possible solution.

ASML is also gearing up to produce high numerical aperture EUV tools as a long-term solution for even finer resolution.

In summary EUV is ramping up today as a 36nm solution for 7nm foundry logic processes. Continued improvement in systems, pellicles and photoresists should carry EUV into the mid-2020s. High-NA systems are being developed to continue further scaling into the late 2020s and beyond.

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Changes Coming at the Top in Semiconductor Equipment Ranking

Changes Coming at the Top in Semiconductor Equipment Ranking
by Robert Castellano on 12-10-2018 at 12:00 pm
Categories: Information Network, Semiconductor Services
3 Comments

Semiconductor equipment vendor ranking, which didn’t change much between 2016 and 2017, is undergoing a makeover, as Lam Research, ASML, and Tokyo Electron (TEL) are switching places and top-ranked Applied Materials is getting closer to losing its number one ranking.

Since the 1990s, Applied Materials has been the market leader in the semiconductor equipment space. Previously, Japan’s TEL was the market leader going back to 1989. TEL, which was No. 4 in 2016 is now No. 2 through the first three quarters of 2018. But most important, the spread between the No. 1 and No. 2 companies is rapidly shrinking.

In 2016, Applied Materials was 9.3 share points ahead of Lam Research. In 2017, Applied’s lead dropped to 6.4 share points ahead of Lam. Now, through the first three quarters of 2018, Applied’s lead has shrunk to just 2 share points ahead of TEL.

An important takeaway is that Applied Materials is the only company that lost market share sequentially in each of the time periods, while ASML and TEL were the only two companies that sequentially increased market share in the periods.

More Headwinds Coming
The semiconductor equipment market grew from $41.2 billion in 2016 to $56.6 billion in 2017, an increase of 37.2%. For the first three quarters of 2018, global revenues increased 19.4%. Assuming a growth of 10% for all of 2018, revenues for Q4 2018 should only reach $12.7 billion, down 15.2% YoY from Q4 2017. Chart 1 plots semiconductor market between 2015 and 2018 on a quarterly basis.

Much of the growth in equipment came from Korean semiconductor manufacturers, particularly memory companies Samsung Electronics and SK Hynix. In 2017, Korea represented 31.7% of the $56.6 billion semiconductor equipment sector. Through the first three quarters of 2018, Korea accounted for 29.4% of the global market.

Demand in the server, PC, and mobile markets is weaker than it was earlier in the year, and memory prices are softening in the near term. Because of a drop in average selling prices of DRAMs and NAND, memory companies are pushing out capex spend. Samsung Electronics said the addition of 20,000-30,000 wafers/month of DRAM capacity at the Pyeongtaek plant’s second floor will be postponed to 2020 in order to maintain profitability along with strategic inventory controls.

If margins decrease, Samsung will likely delay a 2019 planned NAND capacity expansion of 30,000 wafers per month on the second floor of Pyeongtaek #1 plant and at its Xian #2 plant to 2020.

While all semiconductor equipment suppliers tout the memory companies among its customers, Applied Materials and Lam Research have high exposure to memory. In its most recent quarter ending October 2018, Applied reported that 60% of its revenue came from the memory sector.

TSMC has also reduced its capital spending outlay for the year, due to weaker than expected sales in iPhones, where it supplies the processor chip, and because the collapse in cryptocurrencies

Applied Materials competes against all equipment companies listed in Table 1 except lithography ASML. ASML is the sole supplier of EUV (extreme ultra violet) lithography equipment. EUV is supposed to slowly replace DUV immersion lithography as the industry moves to the 7nm technology node.

The replacement of DUV immersion by EUV will dramatically reduce deposition, etch, and metrology steps. Current DUV immersion is viable for processing devices with 30nm features. Below that, engineers employ multiple patterning steps as a way of extending the DUV lithography tool. These multiple processing steps are deposition-etch intensively, utilizing equipment from AMAT and LRCX (and others). In other words, semiconductor manufacturers are utilizing multiple patterning processes, requiring extensive use of deposition and etch equipment, to avoid purchasing the extremely expensive EUV lithography equipment.

If we look at Chart 2, using immersion DUV (ArF-1) at the 20nm node there are 13 mask layers, etch of which use multiple dep-etch steps. If we move across the top of the chart, at 10nm there are 18 mask layers, an increase of 50% in the use of deposition-etch steps.

Chart 2

Multiple patterning at the 7nm node, as shown in the bottom left of the chart, requires 27 mask layers. However, by switching to EUV (bottom right) at 7nm, only 14 mask layers are required, similar to the 20nm node with DUV.

As for the terminology, switching from DUV to EUV, the double litho, double etch (LELE) process will be eliminated while ArF-I (immersion DUV) would continue to be used for the self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) processes. Most importantly, half the processing steps will be eliminated.

A combination of all these headwinds are significant detriments to the sustained growth of the semiconductor equipment market in 2019. According to The Information Network’s report “The Global Semiconductor Equipment: Markets, Market Shares and Market Forecasts,” that means global equipment revenues could drop 8%.

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IEDM 2018 Trip Report!

IEDM 2018 Trip Report!
by Daniel Nenni on 12-10-2018 at 7:00 am
Categories: Events
11 Comments

Hello, my name is Daniel Nenni and I am a semiconductor conference addict. I just can’t seem to get enough. The semiconductor ecosystem is very wide now and moves so quickly it is nearly impossible to keep up without constant conference attendance. As a SemiWiki contributor not only do I get free conference passes, I get access to people and materials that help feed my insatiable appetite for semiconductor information. The world really does revolve around semiconductors and now me personally since I know all that is semiconductor, absolutely.

Premier SemiWiki blogger Scott Jones also attended IEDM and will have more detailed blogs coming soon.

About IEDM
With a history stretching back more than 60 years, the IEEE International Electron Devices Meeting (IEDM) is the world’s pre-eminent forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. IEDM is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. The conference scope not only encompasses devices in silicon, compound and organic semiconductors, but also in emerging material systems. IEDM is truly an international conference, with strong representation from speakers from around the globe.

As I mentioned before, IEDM is the premier semiconductor process technology conference. This year the theme is Device Breakthroughs from Quantum to 5G and Beyond. One of the more interesting topics to me was Interconnects to Enable Continued Scaling with papers from ARM, IBM, IMEC, UT Austin, GlobalFoundries, Stanford, and AMAT. This is a must read for those of you who think Moore’s Law (which is actually an observation) and semiconductor scaling is at an end, because it is not, not even close.

There was also an interesting session on 3D integration: High Density Stacked FinFETs and 3D integration of 2D memory. Memory technology was a major focus (especially MRAM), and rightly so, but I did not have time for it unfortunately. Photonics also made it into the program which is a good thing. We track photonics related content on SemiWiki and have seen a significant rise in content and readership in 2018.

Based on my time mingling amongst the crowd I was happy to see a lot of young faces. IEDM is clearly doing a great recruitment job. The old guard, me included, always wonders who will replace us as time goes by. Based on what I saw this week I think we are in good hands, no problem.

The one criticism I do have is the exhibit hall. It was pretty lame to which I say why even have one at all? Seriously, a complete waste of precious space. If a vendor wants exposure make them write papers and rent hotel suites for more intimate conversations. Leave the exhibit halls to the user group meetings and less technical conferences like CES, my opinion.

We can have an IEDM discussion in the comments section if you like. I have copies of the presentations and conference proceedings for reference.

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GM: Stop the Downsizing!

GM: Stop the Downsizing!
by Roger C. Lanctot on 12-10-2018 at 7:00 am
Categories: Automotive
3 Comments

General Motors CEO Mary Barra is known for a number of quotes one of which is: “My father was a die maker for 39 years, so I had a basic understanding of the automobile industry and what the manufacturing world was like, just from the opportunity to spend time with him, just talking, because he was a car buff.” One has to wonder what Mary’s dad would have so say about the latest news out of GM.

Two major press events preceded this year’s Los Angeles Auto Show and AutomobilityLA. The first event arrived the Friday before the Show following the Thanksgiving holiday bringing news of a government report revealing catastrophic human-influenced climate change. On Monday, General Motors announced its plans to idle or close five plants (four in the U.S. and one in Canada), layoff 14,000 workers and terminate five sedans: the Chevrolet Cruze, Volt and Impala, Buick LaCrosse and Cadillac CT6.

The catastrophic climate report was notable for its release occurring on a Friday in the middle of a holiday. Journalists commented that the decision was clearly taken by the Trump administration to dump the report on a Friday to ensure that it received as little attention as possible.

In contrast, the GM announcement came on the Monday following the holiday weekend and preceding the L.A. Auto Show guaranteeing widespread press attention and analysis. The decision was clearly a calculated one as GM’s stock price rose nearly 5% on the news, as investors rewarded GM’s apparent fiscal prudence.

Unfortunately, the decision to release the announcement on Monday also revealed GM’s priorities. In spite of anything GM’s leadership might have to say about its employees or its customers, the top priority is clearly investors.

In spite of GM’s best efforts, though, the stock hasn’t budged much from its IPO price. The latest bump, like those that have preceded it, will rapidly fade and fall.

GM’s massive market retreat has been underway since the government bailout and bankruptcy approximately 10 years ago. At that time GM, along with Chrysler, used the opportunity of bankruptcy to justify the termination of 3,389 dealers.

Terminating dealers seems like a counter-intuitive strategy for a company planning to emerge from bankruptcy and needing to sell more cars. But as Tammy Darvish, author of “Outraged,” describes it, the move was clearly intended to reduce inter-dealer competition and goose profit margins.

GM has continued to pursue higher vehicle prices and profits by dialing back on incentives. It remains unclear as to precisely how sustainable that strategy will be. GM’s profit-driven market manipulations have plunged the company to fifth place globally based on vehicle production – well behind Hyundai and slightly ahead of Ford.

The pursuit of profit has contributed to decisions to close plants in Australia, Indonesia, India and Russia while pulling out of the European market by selling Opel to PSA. Other market exits included India, South Africa, and Russia.

The company has also bought back $10B in stock since 2015. Investors have questioned the purpose or wisdom of these buybacks – normally done to increase the stock price – since the stock has shown little movement.

Meanwhile GM has been sinking hundreds of millions of dollars into Cruise Automation and launching the Maven car sharing service. The company line on this mix of exits and investments is that GM is investing in the future, preparing for a shared, autonomous, electric vehicle future.

But it is difficult for the company to escape the logic that its strategy of focusing on profitable operations and cutting off unprofitable ones directly contradicts its investment strategy of pouring money into ventures with uncertain prospects. Both Maven and Cruise are facing mixed results with Maven expansion plans on hold and Cruise failing to meet critical milestones on the path to autonomous operation.

The biggest and most dubious claim of all at GM – and it is one that is shared by Ford Motor Company – is the company’s almost complete exit from the passenger car market – joining FCA and Ford in focusing on SUVs, crossovers and pickup trucks. GM, like its Detroit competitors, blames a lack of consumer interest in passenger cars and a correlated decline in sales.

GM, Ford and FCA make much more money selling SUVs, crossovers and pickups than they do selling cars. So it is logical to want to make more of these large vehicles and less of smaller, passenger vehicles.

This myopic profit-driven strategy is effectively painting the three Detroit OEMs into a marketing corner. A trucks-and-SUVs-only strategy makes all three of these auto makers more vulnerable than ever to imports and domestically manufactured trucks and SUVs from import makes.

What is perhaps most stunning, though, is GM’s decision to terminate the Volt. It’s easy to make the case that sales of the Volt failed to meet the 30k/month goal originally intended, but it is also easy to make the case that GM never fully funded the market funnel to drive demand.

Car makers often paint themselves as the sad victims of market forces and lagging demand. The reality is that car makers spend billions of dollars telling consumers what cars they “want” or “need.” Consumer demand is not occurring in a vacuum.

The Volt extended range EV has consistently produced some of the most amazing customer satisfaction scores ever seen by General Motors. Volt evangelists are legion, yet GM has somehow failed to embrace these brand ambassadors and leverage them to build a stronger footing in the EV market.

Now GM is terminating the Volt – or so it seems. Such a move represents an extraordinary destruction of market value comparable only to GM’s sales of Opel to PSA.

It’s not too late for GM to turn in the direction of the skid and get itself back on track. Of course, the Trump administration won’t make that easy with threats of suspending GM’s EV subsidies and slapping tariffs on cars imported from GM factories in China.

It’s time for GM to take a greater interest in its customers, its dealers, and its workers and, for at least a quarter or two, tell Wall Street to take a hike. It’s time to get back to basics – get back to the product.

With the passing of FCA CEO Sergio Marchionne and the ousting of Renault-Nissan-Mitsubishi Chairman Carlos Ghosn the stage is clear for a real game changer, GM’s Mary Barra. It’s time for Barra to take her place as the leading voice of the global automotive industry – an industry that needs a more inspiring vison than the prospect of endless downsizing that has unfolded under her guidance thus far.

Another one of Mary Barra’s noted quotes is: “My definition of ‘innovative’ is providing value to the customer.” Right on, Mary.