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When it Comes to Process Migration, “Standard Cells” are Anything But

When it Comes to Process Migration, “Standard Cells” are Anything But
by admin on 08-22-2018 at 12:00 pm
Categories: Automotive, EDA

Standard cell library developers are faced with a daunting task when it is time to create a library for a new process node. Porting an existing library can be a big help, but even then, manual modifications to 800 or more cells is still required. Each of those cells has many geometric elements are that affected by new design rules. All edits and changes have to be adjusted so that the results are DRC clean. In some cases, any advantage coming from reuse might be negated by the amount of effort required for porting.

I recently viewed a webinar by Silvaco on the topic of automating standard cell library porting. Their Cello tool helps with layout migration, layout optimization and standard cell layout creation. Because they use the same tools internally for their standard cell library development and porting services, Cello has evolved based on real world experience. The webinar pretty thoroughly shows how Cello is used to not just to port, but also used to modify cell libraries for specific requirements in areas like Automotive or DFM.

The webinar was hosted by Guilherme Schlinker, Director of Layout Automation at Silvaco. Guilherme made the point early on that in most standard cell libraries there are many cells that might not require special attention, and that there is a smaller set of critical cells that will require hand tuning. Cello frees up skilled library developers to work on the most critical cells while it handles the bulk of the porting effort. Cello has features that include an intuitive GUI cockpit, Tcl scripting, 2D compaction and spacing, built in macros, distributed jobs, and export to GDS, LEF, CDL and LPE. It is integrated with Virtuoso and Custom Complier, or users can use its native layout editor.

The process starts with a proportional scaling of the layout to the new feature size. This is followed by rule specific sizing to ensure that the output is DRC correct. This includes things like enclosure and spacing rules. Additionally, if needed, versions of the cells with increased enclosure can be easily produced for higher reliability applications such as automotive, etc.

Another important element of the porting process is ensuring that there is correct pin accessibility. Silvaco’s Cello takes a unique approach by adding virtual vias and then running DRC checks. In advanced processes via spacing rules can be more restrictive than metal spacing rules. It is painful to learn later that a seemingly DRC correct cell is not usable due to pin accessibility issues. Another interesting application for this technology is in looking at the effect of design rule changes on library performance. It’s relatively straightforward to apply library wide changes and then look at changes in cell or design characteristics.

Also during the webinar Guilherme talked about some of their migration projects. In one instance their Foundation IP Team used Cello to convert ~600 cells from 180nm to 130nm in only 5 days. This included review and fine tuning by a single engineer. He estimated that they benefited from a 10X speed up when compared to manual migration. It’s worth mentioning that Cello works equally well for FinFET processes or planar CMOS.

Fortunately, the webinar is archived on the Silvaco website and available for on-demand viewing. The video goes into much more detail about the user interface, geometry output and the features for controlling the results. I suggest taking a look to get a complete picture of Cello’s capabilities.

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The Pain of Test Pattern Bring-up for First Silicon Debug

The Pain of Test Pattern Bring-up for First Silicon Debug
by Daniel Payne on 08-22-2018 at 7:00 am
Categories: EDA, Siemens EDA
1 Comment

In the semiconductor world we have divided our engineering talent up into many adjacent disciplines and each comes with their own job titles: Design engineers, Verification engineers, DFT engineers, Test engineers. When first silicon becomes available then everyone on the team, and especially management all have a few big questions on their mind:

  • Is first silicon working?
  • Do we have any functional bugs?
  • Do we have any test program bugs?

Getting time on an ATE system is a big challenge, because these specialized testers can be pre-booked for other devices and you may just have to wait for your turn to open up in the schedule. Let’s take a look of the silicon bring-up process:

  • DFT engineers create ATPG patterns
  • ATPG patterns converted into tester-specific format
  • Test program runs on the ATE system
  • STDF output file gets translated into failure date
  • Identify failing logic

Here’s a flow-diagram of silicon bring-up and debug:

Another complexity is that your ATPG patterns can be generated at the core level, but then need to be re-targeted to the chip-level. If so, then the failure date needs to be reverse mapped from chip-level to core-level prior to any diagnosis. This flow is complex, takes precious time and can be prone to mistakes.

See how there can be drama between test engineers and DFT engineers, getting time on the tester, or even diagnosing failures between core and chip levels?

There is a natural back and forth between test engineers and DFT engineer during silicon bring-up, so anything to help communicate or cut time in the debug process is certainly welcomed. Mentor did something about improving this situation by creating a new bring-up flow called the Tessent SiliconInsight Desktop flow, and here’s what their setup looks like:

With this approach a DFT engineer can do silicon bring-up using the Tessent Shell environment connected to simple test instruments, USB to digital adaptor and a validation board. Even the test engineers can use this same setup instead of relying upon a complete ATE system. Nobody has to wait for scheduling time on the ATE when using this desktop flow instead. Failure data is readily understandable with the desktop flow using either non-compressed or compressed ATPG patterns, so there’s no long cycles of pattern execution and analysis.

Alternatively you could try a simple JTAG port approach to silicon bring-up, but then you wouldn’t have the flexibility of SiliconInsight Desktop because with it’s non-JTAG test access it can support ATPG patterns with chip compression and more than 25 external scan channels for test and diagnosis. Yes, there is some engineering effort for your team to create the validation board, but it’s a convenient way to allow control of your DUT with simple instruments.

On the software side here’s how you create your tests and diagnose results during bring-up:

Using this flow during silicon bring-up a failure occurs in a test pattern and you want to know which specific scan cells find the failure. If your chip is using on-chip compression and hierarchical DFT then it calls for some sophisticated decoding and dedicated diagnosis patterns. Fortunately for us when using Tessent SiliconInsight all of those details are automated, so we can focus on the analysis part.

Case Study
Cypress Semiconductor shared their actual experience during bring-up of a touchscreen controller chip at the IEEE%20International%20Workshop%20on%20Defects,%20Adaptive%20Test,%20Yield%20and%20Data%20Analysis%20-%20Call%20for%20participation.eml.html”]2016 IEEE Workshop on Defects, Adaptive Test, Yield and Data Analysis. Here’s their setup using Tessent SiliconInsight:

When ATPG patterns were run then a failing cycle was found, and diagnosis pinpointed the suspects as two flops in a scan chain. The engineer was then able to isolate and mask the failing flops, and create a new ATPG pattern set. With the new pattern set the tests passed with no other failures detected. They found the root cause of the silicon failure with this new bring-up flow, all without having to use a costly ATE system and in a much shorter time frame than before.

Conclusion
Silicon bring-up is filled with anguish, pain and pressure, as everyone in the company wants to know how healthy first silicon is looking. Using a new approach called Tessent SiliconInsight Desktop looks to be quite promising because it only requires simple instrumentation, laptop, adapter board and a verification board. Your expensive ATE systems can be used for production requirements, instead of silicon bring-up now. This new flow supports lots of features:

  • Embedded memories
  • Logic
  • IEEE 1687 IJTAG instruments
  • Quick failure mapping
  • Diagnose to failing memory cell, scan cell or net segment

Read the complete six page White Paper online.

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Harnessing Clock and Power

Harnessing Clock and Power
by Alex Tan on 08-21-2018 at 12:00 pm
Categories: EDA, Siemens EDA

Switching translates to power. Similar to the recent slow down experienced by Moore’s Law, the constant power density (power demand per unit chip area) prescribed by Dennard scaling was no longer affordable across the technological scaling. While the contribution of leakage power component in advanced process nodes was getting somewhat rectified recently, managing the dynamic power attributed to the increase device density is still a challenge as it is critically demanded by many mobile, IoT and data center applications.

Power, Clock and PowerPro
Dynamic power is defined to be proportional to frequency as given by the equation: ; where k is switching activity, f is design frequency, c is capacitance and Vdd is operating voltage. Aside from memory, the clock network has been the major contributor to the overall power number as it is typically the largest net sprawling across the design and operates at the highest frequency of any signal within the entire synchronous system.

The traditional approach of power saving involves controlling switching of the clock network by inserting clock gating, which can be performed either at the RTL capture stage or during the synthesis stage through logic inferencing. On there other hand, there are many logic implementation styles such as in sharing common enable signals, applying derivative clock trees or free-running clocks, among others, hence, addressing a power optimal clock-tree implementation early is key in order to yield the greatest saving impact and to prevent unnecessary undoing of coded RTL as illustrated in Figure 1.

Since design-for-power methodology demands a rather holistic and converging solution, the availability of a solution that could identify a power optimal RTL code early, accurately assess and propagate the incurred power amount throughout the implementation stage is desirable. Mentor’s PowerPro has an integrated platform addressing such needs.

PowerPro has been the solution leader in RTL power optimization domain for the last few years. It provides a complete solution for measuring and optimizing power through an interactive exploration at the microarchitectural level. PowerPro is capable of spotting power leakage and applying opportunistic clock gating insertion during the RTL development cycle, while its physical-aware flow provides the necessary accuracy for estimating design power values. Its guided power reduction includes the recommended RTL codes that would satisfy the power saving and automatically validated by its built-in formal equivalency engine.

Alchip, CTS and Fishbone
Alchip® is a fabless ASIC provider serving various computing market segments and utilizes advanced process nodes to do IC design. In an attempt to further reduce power consumption on high performance designs, they have ventured into applying PowerPro solution on the clock tree implementation.

Clock network implementation can be categorized into two major types. as a tree structure or in gridded/mesh form, with some variations in between. The amount of shared network branches, connecting the a clock driver (root) to the sink points determines if the implementation is closely resembled to the conventional clock-tree network. As part of clock-tree implementation, CTS (Clock Tree Synthesis) is usually presented as an embedded P&R tool function as illustrated in the diagram Figure 2.

A 16nm, 600Mhz core processor design was used as a test vehicle using this flow. Two different clock topologies were applied: a conventional CTS and a fishbone clock tree as shown in Fig. 3. Only the total power numbers of two critical design entities: the flops and design clock network were compared as the power contribution from logic network or memories are effectively unchanged.

Sequential and Memory Clock Gating
Sequential clock gating requires the use of sequential analysis over multiple clock cycles to identify writes that are either unobservable down-stream or the same value is written in consecutive cycles. Deep sequential analysis has enabled PowerPro to take advantage of subtle RTL coding inefficiencies such as unused computations, data dependent function and don’t care cycles. It could disable previous cycle register data generation if data is not used in the current cycle.

Two prominent sequential clock gating techniques adopted by PowerPro: an Observability based Clock Gating in which scenario a change in a signal value does not propagate to a primary output/flop/latch/memory and does not affect the primary outputs (redundant writes that will not be used in subsequent clock cycles).

In the example on Fig.4, the circuit was a three staged pipeline data path containing 5 flip-flops. Under the combinational clock gating condition, only the last flip flop was gated and data flows through two computational stages before being latched into the output register dout. The output of doutis held based on the signal vld_2. Through combinational analysis, the clock gate on doutis added as a simple combinational substitution of the feedback loop. Sequential clock gating on both d_1and d_2requires a sequential analysis to propagate the data hold condition backwards, disabling the unused computations in previous cycles.

As illustrated in Figure 5, the second type is called Stability-based Clock Gating, which is when the same value as in the previous clock cycle is getting latched into a flop/latch such that it will not have any effect on the primary output. Although all of these analyses can be done vector-less, it can take user’s provided activity vectors through various formats (QWAVE, SAIF, FSDB) for further refined results.

Aside from flip-flops, memory components are prone to redundant toggles, as only a few memories are ON at any time. These can be reduced by means of similar coding techniques. The SRAM enable was intentionally left uncontrolled to represent the worst-case scenario for memories. PowerPro showed that it could automatically detect the enable signal and gated the SRAM properly by applying both the Observability-based and Stability-based clock gating –to resolve redundant read and write operation respectively– saving the memory’s dynamic power significantly.

Result Summary
There was an increased of 28% more clock gating covering over 68% of flip-flops compared with only 53% without PowerPro as captured Table 1. The additional clock gating cells did not adversely impact the design, instead it decreased the average toggling percentage on the output of integrated clock gatings (ICG) from 92.7% to 65.1%.

A significant reduction of power was reflected in total power for registers (26% less) and memories (80% less) as shown in the Table 2.

When PowerPro application was combined with the fishbone architecture, the overall impact is more pronounced of 59% total power reduction. Both the pre and post layout power numbers were also shown to correlate well: 31% post-layout vs 26% @ RTL for FF and 86% post-layout vs 80% @ RTL. PowerPro results were produced in the context of the RTL code, schematic display, design hierarchy representation and various sortable reports to enable efficient analysis and easy power tracking throughout the design cycle. It also accommodates the ECO flow by non-disruptive validation of post-ECO generated gate-level netlist to assess power.

Key takeaways from this case study: Mentor’s PowerPro allows power exploration and significant power optimization at micro-architectural level. Its pre-layout/RTL level power estimation shown with Alchip’s testcase to be within 6% compared with post-layout for both memories and sequential cells. The embedded equivalency checking facilitates an optimal RTL code that is correct-by-construction, thus helps ensuring convergence during design implementation. Such process agnostic power optimization should provide good starting point for power sensitive design as we head into 7nm process node and beyond.

For more details on PowerPro check HEREand Alchip case study and others please check HERE.

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Computer Vision Design with HLS

Computer Vision Design with HLS
by Bernard Murphy on 08-21-2018 at 7:00 am
Categories: AI, EDA, IoT, Siemens EDA
3 Comments

I’m on a mini-roll on the subject of high-level design for ML-based systems. No complaints from me, this is one of my favorite domains and is certainly a hot area; it’s great to that EDA vendors are so active in advancing ML-based design. Here I want to talk about the Catapult HLS flow for use in ML design.

Since I’ve covered the ML topic multiple times, I won’t bore you with a lengthy discourse on the basics. ML (at least in this context) is based on convolutional neural nets (CNNs), inspired (somewhat) by the way neurons process information in our brains, starting from a full image and progressing through transformations in layers of operations with coefficients/weights pre-determined by training to ultimately indicate recognition of a trained image.

From a design point of view, this doesn’t look much like regular logic design/architecture, though of course it all winds up in logic functions, primarily multiply-accumulate (MAC) functions, 4-port registers for tightly-coupled memory and SRAM for next-level caching, all most commonly supporting some type of fixed-point representation. But these are leaf-level functions. The layers in a vision CNN may be processing images with 1M+ pixels, each with 24+ bits for color. So the first layer alone has to process a huge number of inputs (down-sampling through later layers will progressively reduce these sizes).

That means you have to use high-level modeling to experiment with architecture choices and to validate your design against real image data. And if you can map your ultimate design to RTL through high-level synthesis (HLS), such as Mentor’s Catapult HLS, so much the better, especially since that tool supports design in straight C++, making it an appealing starting point for people more familiar with algorithms than the intricacies of SystemC (FYI, Catapult HLS also supports SystemC).

Of course if you want to synthesize to a CNN, you’re going to have to accept some limitations on your C++ coding style. For example, you need to use fixed-point data types and you should use fixed-size memory arrays and array indexes, rather than dynamically allocated memory and pointers. Which is not really a problem because you want to do this anyway to reduce power. Mike Fingeroff (HLS Technologist at Mentor) provides guidance (in the white paper link at the end of this blog) on some of the more common areas where you need to adapt.

Taking the HLS path with Catapult HLS offers a number of advantages. The tool can automatically synthesis interface logic (such as AXI4 video stream) based on simple user choices. It will also automatically optimize timing during the synthesis scheduling step, given constraints you set for other factors such as latency and area. In fact in general this is an area where you can experiment with timing versus resource/area tradeoffs based on feedback from the tool. For example you can look at tradeoffs in unrolling loops to drive parallelism. The tool will also help you explore tradeoffs in memory such as word-width and block or interleave choices. And, using PowerPro technology, the tool lets you explore the power implications of all these tradeoffs, so between all these factors you can get to an optimum PPA for your design.

One question occurred to me – how do you bootstrap this process from a trained network with weights? Ellie Burns, Director of Marketing, Calypto Systems Division at Mentor, provided a revealing explanation. It might seem like this is a big deal, but in practice current customers are carrying over the design (and weights) more or less by hand or using their own scripts without difficulty. The much more important need for those teams is the PPA tuning they can get in optimizing microarchitecture choices. Experimenting with options in the synthesis engine and testing/characterizing with real-images/video at the C-level is where they invest the majority of their effort.

Computer vision has become a critical differentiator in many products, but obviously it is not enough that such products support vision. They also need to be fast, very low power and as low cost as possible in many contexts (such as IoT applications). Those are challenging goals; you are adding state-of-the-art functionality but it still needs to fit inside a consumer-acceptable footprint. HLS is an interesting way to get there, by letting you experiment with your algorithm in C++ to optimize and fine-tune the implementation through synthesis. I should add that this flow works both with ASIC-based and FPGA-based designs. You can learn more from this white-paper.

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Webinar: NetSpeed is about to change the way SOCs are designed

Webinar: NetSpeed is about to change the way SOCs are designed
by Tom Simon on 08-20-2018 at 12:00 pm
Categories: AI, EDA, Events, IP, NetSpeed Systems
2 Comments

A large part of the effort in designing SOCs has shifted to the integration of their constituent IP blocks. Many IP blocks used in SOCs come as ready to use components and the real work has become making them work together. Network on Chip (NoC) has been a huge help in this task, handling the interconnections between blocks and planning for anticipated traffic. NoCs have evolved quite a bit, becoming more like full blown networks, offering features like QoS, traffic management, cache coherency, high reliability and true layered networking protocols. NetSpeed, a leading provider of NoC technology, is using its foundation technology and a number of innovations to expand their offering to address a much larger part of the job of integrating IP blocks to build an SOC.

NetSpeed’s NocStudio already helps with making architecture decisions and analyzing performance. It also helps with some aspects of SOC verification and physical design. Their new offering, SocBuilder goes much further by handling IP integration and assembly. Additionally, it compliments NocStudio in the areas of SOC verification and physical design. Even more interestingly it provides support for SOC bring-up and debug. Because SocBuilder and NocStudio share a single platform, they share metadata and can be controlled and automated as a single system.

One of SocBuilder’s key features is the use of reference designs and an extensive IP catalog. Information gleaned from the reference designs and protocol information from the IP catalog are used by machine learning, and advanced data analytics and visualization to assist the design process. Because much of the work during SOC design is related to protocol related issues, this is a ripe area for improved analysis and automation. SocBuilder works with IP descriptions in IPXACT and has extensions for additional metadata for IP. NetSpeed is working with a large number of partners to ensure good coverage of popular IP in their catalog.

With the large array of metadata and IP information available to SocBuilder, it can help with all aspects of physical design, including clock/reset/power, trace/debug/telemetry, MMU/security, and interrupts. These chassis related aspects of the design can be vexing, so having tools to guide the process can be critical to meeting quality goals and deadlines. SocBuilder uses industry standard LEF/DEF during floor planning. SocBuilder assists with connectivity and address map design as well.

After floor planning, system simulations can be run in SocBuilder to ensure performance, power and functional safety goals are met. There is visual feedback for a wide variety of system performance parameters such as power and thermal, etc. The final design is then run through extensive LINT checks that covers protocols, power, connections, performance, etc. System level deadlock checks are also included in SocBuilder.

The outputs are comprehensive. SocBuilder provides SystemC, RTL for the design description. DEF, SDC and scripts are output for the physical design. Test benches are also generated. SocBuilder helps with the essential task of software design too. It produces C models, reference documentation and a programmer’s guide. PPA metrics are also output.

There is an upcoming webinar to acquaint SOC designers with the features and to go into more depth regarding how it works. The Webinar will be on Tuesday August 28[SUP]th[/SUP] at 8AM Pacific Time and registration information is available on the NetSpeed website.I did not dwell much on the machine learning aspect, but this is a reminder that machine learning is in the process of transforming design. Companies that have experience with ML in design and that are expanding its use will certainly be able to make big leaps in enhancing designer productivity.

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TSMC GlobalFoundries and Samsung Updates from 55DAC

TSMC GlobalFoundries and Samsung Updates from 55DAC
by Daniel Nenni on 08-20-2018 at 7:00 am
Categories: Events, FD-SOI, FinFET, Foundries, GlobalFoundries, Samsung Foundry, Synopsys, TSMC
9 Comments

One of my favorite traditions at the Design Automation Conference is the Synopsys foundry events (the videos are now available). I learned a long time ago that the foundries are the foundation of the fabless semiconductor ecosystem and your relationships with the foundries can make or break you, absolutely. I also appreciate the free food, food tastes much better when it’s free.

Synopsys has an advantage being not only the number one EDA company but also the number one IP provider with the largest IP portfolio known to semiconductor man or woman. You can bet Synopsys tools and IP are silicon proven on every edge of the process technology spectrum (leading through trailing) without a doubt. One of the benefits of live events of course is that you get to mingle with the crowd and speakers which includes ecosystem executives from all over the world and don’t be surprised if Aart de Geus or Chi-Foon Chan are breaking bread at your table.

My favorite breakfast of course is the one with my semiconductor bellwether TSMC. Willy Chen, Deputy Director, Design Methodology and Service Marketing, TSMC, is a great speaker and very transparent in what he presented last year versus this year. Willy is a very smart and fashionable guy and very approachable so approach him if the opportunity presents itself. Kelvin Low (Moderator), VP of Marketing, Physical Design Group, Arm is also a great speaker. Kelvin spent the first half of his career with foundries (Chartered, GF, and Samsung) and is now IP. Hopefully next he will go into EDA completing the ecosystem trifecta! Also speaking were Kiran Burli, Director, Solutions Marketing, PDG, Arm and Joe Walston, Principal Engineer, Synopsys.

Designing with Leading-Edge Process Technology, CPU Cores and Tools
Faster, smaller, cooler product requirements continue to challenge designers to achieve their targets. TSMC, Arm and Synopsys kicked off DAC 2018 to share results of their collaboration to address these challenges to enable optimized design and accelerate design closure for Arm®-based designs on the latest TSMC process technology using the Synopsys Design Platform. This event video introduces the new Synopsys QuickStart Implementation Kits (QIKs) for ARM® Cortex®-A76 and Cortex-A55 processors that take advantage of ARM POP™ technology and Synopsys tools, and the collaborative design enablement for TSMC 7-nm process technology.

My beautiful wife joined me for the GlobalFoundries dinner which was focused on FD-SOI. As you know I am a big fan of FD-SOI which we track closely on SemiWiki. In fact, Scotten Jones just did a very nice FDSOI Status and Roadmap last month following SEMICON West. Kripa Venkatachalam, Director of Product Management, GLOBALFOUNDRIES, did a very nice presentation followed by Wayne Dai, President and CEO, VeriSilicon, and Jacob Avidan, SVP of Design Group R&D, Synopsys.

Addressing the Design Challenges of IoT Wearables and Automotive with 22FDX Technology
In this video of the Synopsys and GLOBALFOUNDRIES dinner panel event at DAC 2018, you will hear a discussion of how GLOBALFOUNDRIES’ innovative FDX process coupled with Synopsys’ design tools are providing mobile, IoT and automotive chip designers with the low-power and high-performance technology required for product success. VeriSilicon shared some specific examples of their successes with GLOBALFOUNDRIES’ 22FDX process and Synopsys tools. The event concluded with a panel discussion on various aspects of designing with 22FDX and addressing barriers to adoption of this technology.

Last but not least was the Samsung breakfast featuring Robert J. Stear, Senior Director, Samsung Foundry; JC Lin, Vice President of R&D, Synopsys; and John Koeter, Vice President of Marketing, Synopsys. Samsung has made great ecosystem strides in the past few years and is clearly experiencing the benefits. In fact, Samsung is holding a Tech Day on October 17[SUP]th[/SUP] in San Jose. If you have a golden ticket I hope to see you there. Tom Dillinger and I will be covering it for SemiWiki.

EUV is a very hot topic and Samsung is leading the way with their 7nm EUV process. Scott Jones has also covered Samsung and EUV with Samsung 10nm 8nm and 7nm at VLSIT and SEMICON West – Leading Edge Lithography and EUV
Enabling Optimal Design with Samsung 7nm EUV Process Using the Synopsys Design Platform
As each new process technology brings with it significant advantages as well as design challenges, Samsung Foundry and Synopsys continue to collaborate to enable optimal design. At this event, you’ll learn how our efforts provide a robust foundation for designers to get the most from Samsung advanced process technologies using Synopsys’ Design Platform with Fusion Technology and state of the art IP.

Take a look at the videos and let’s talk foundries in the comment section…

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AMAT down 10% as expected Foundry spending slow down unexpected

AMAT down 10% as expected Foundry spending slow down unexpected
by Robert Maire on 08-19-2018 at 12:00 pm
Categories: Samsung Foundry, Semiconductor Advisors, Semiconductor Services, TSMC

Applied reported a more or less in line quarter, slightly beating weaker expectations. As we had projected, the October quarter is expected to have revenues down 10% which is at the low end of our expected 10-15% drop in business. Applied services helped partially make up for some of the equipment sales weakness. Revenue came in at $4.47B versus street of $4.43B and EPS was $1.20 versus street $1.17. The October quarter is guided to $4B and EPS of $0.96 versus $4.46B and $1.17. Its clear that most analysts neglected to cut their numbers despite the widespread news.

Similar to what we heard from both Lam and KLA, management suggested Sept/Oct quarter would be a trough. However we were slightly surprised that management refrained from describing what the recovery might look like, and how long we would be in the trough. This is a sharp variation from KLAC which called for a “sharp snapback” and even weaker than Lam’s vague and softer, “positive trajectory” comments.

Perhaps one of the reasons for the weaker and less committed outlook is that Applied revealed on the call that the weakness in spending which had been limited to Samsungs memory side has now spread to foundry customers. Thats customers with an “S” as in more than one foundry is slowing down their spending.

We can only assume that both TSMC and Samsung are slowing their foundry spend as they are the biggest foundries and GloFo isn’t spending that much to start with. This seems to be somewhat confirmed as the mix of foundry business has been shifting from leading edge to trailing edge spend. The company still feels very bullish about 2019 being up in spend but we think its going to be very hard to get there from here if both memory at Samsung and at least two foundry customers are slowing their spend.

Its also clear that there is not an expectation of a rescue coming in from the display side of the business. The part of the business that’s doing a great job continues to be Applied’s services business which is helping to offset weakness in new tool sales. It’s clear to us that the reduced cyclicality is as much a reflection of a higher services business as it is a reflection of more rational spending

Potential share loss???
In doing the math of AMATs tool business against global WFE spend is seems as if AMAT is losing share as its revenue, as quoted on the call, is not growing as fast as the industry top line. Management danced around without directly answering a question on the call on the share loss math. This could be due to the predominance of memory spending we have seen where AMAT has a lower share.

2019 Outlook
Management doubled down on their outlook for 2019 by saying that 2018 and 2019 will now exceed $100B where they had previously just said $100B. If the October and January quarters are weak in 2018 we can see how 2019 could be better but we are more dubious of what will now have to be higher growth in 2019 to make the numbers work, especially in light of BOTH memory and foundry being weaker.

Handset Weakness?
We had previously mentioned our concern about Samsung’s potential plan to shutter a China handset factory. We think this could be evidence of further slowing which manifested itself as a slow down in foundry spend at both TSMC and Samsung that would obviously have been making chips for the factory that is to be shut.

The Stock
Investors obviously did not like the lower outlook and the spread of weakness to now include foundrieS, as the stock was off over 4% in the after market. We would imagine that this new, added concern about foundry spending will likely weigh on the group as a whole tomorrow. We had also been hoping for a stronger rebound statement that would show some hard evidence or confidence in the speed of some sort of recovery but that was also missing on the call. Applied results coupled with less than stellar news out of Nvidia could spread to other semi names and we could see the overall group weaker as well.

Also Read: Chip Stocks have been Choppy but China may return

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Chip Stocks have been Choppy but China may return

Chip Stocks have been Choppy but China may return
by Robert Maire on 08-19-2018 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services

Applied Materials (AMAT) is batting clean up in a quarter that has not been pretty. Lately semi stocks seem to have been hit by not only stock specific issues but continued and increasing memory concerns coupled with more macro issues. On top of all this, China trade issues which have in the meantime taken a back burner to other issues threaten to boil over yet again.
Continue reading “Chip Stocks have been Choppy but China may return”

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Measuring Up 7nm IP

Measuring Up 7nm IP
by Daniel Nenni on 08-17-2018 at 12:00 pm
Categories: eSilicon, FinFET, IP, Semiconductor Services

The Linley Group is an industry-leading source for independent technology analysis of semiconductors for networking, communications, mobile, and data-center applications. Their Microprocessor Report is widely read as a source of un-biased, no-nonsense analysis of technologies and trends. So, when they dig into something it’s worth reading.

Mike Demler recently did a piece on eSilicon entitled “eSilicon 7nm SerDes Hits 56GBPS – NeuASIC Platform Includes AI Accelerators for 2.5D/3D ICs”. I know Mike, and he’s one of those “just the facts” kind of guys that speaks from experience, absolutely. I have a copy and here is a quick summary with a link to the report:

The report spends some time reviewing eSilicon’s 7nm SerDes IP. This one IP block has become Star IP for many customers. It implements high-speed serial communication between chips and it’s performance is critical to achieving the overall throughput needed for advanced ASICs. The report goes into some detail about eSilicon’s 56G SerDes – its programmability to allow designers to tune power and performance for long or short reach channels for example. Several other performance statistics about eSilicon’s SerDes are also disclosed in the report.

eSilicon’s 56G SerDes test chip on the bench

eSilicon’s HBM2 PHY is also discussed. This IP implements the physical channel between an ASIC and HBM2 memory stacks. It’s available for a variety of technologies and foundries. The use of this IP to implement 2.5D designs with integrated HBM2 memory stacks on a silicon interposer is also discussed. eSilicon’s line of content-addressable memories are also reviewed in some detail, including application scenarios and performance comparisons with other vendors. The report also delves into eSilicon’s platform focus for its IP offerings, with specific packages for AI and high-performance networking. The details of what goes into a high-performance networking chip are discussed. The methodology eSilicon uses to create platform-based AI chips is also reviewed in some detail.

The report concludes with a frank assessment of market dynamics for the highly competitive networking and AI markets – where eSilicon fits well, and what challenges they will likely face. I believe companies like eSilicon that both develop IP and use the same IP for their ASIC business have a built-in advantage in terms of proven IP quality. As part of my research, I hear all of the bad IP stories from the top semiconductor companies and the foundries. IP really is critical and silicon-proven IP is quite valuable. This Linley report is definitely worth reading. You can download a free copy from the eSilicon website.

Also read: eSilicon and SiFive partner for Next-Generation SerDes IP

About eSilicon
eSilicon is an independent provider of complex FinFET-class ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC+IP synergies include complete 2.5D/HBM2 and TCAM platforms for FinFET technology at 16/14/7nm as well as SerDes, specialized memory compilers and I/O libraries. Supported by patented knowledge base and optimization technology, eSilicon delivers a transparent, collaborative, flexible customer experience to serve the high-bandwidth networking, high-performance computing, artificial intelligence (AI) and 5G infrastructure markets. www.esilicon.com

About The Linley Group
The Linley Group is the industry’s leading source for independent technology analysis of semiconductors for networking, communications, mobile, and data-center applications. The company provides strategic consulting services, in-depth analytical reports, and conferences focused on advanced technologies for chip and system design. The Linley Group also publishes the weekly Microprocessor Report. For insights on recent industry news, subscribe to the company’s free email: Linley Newsletter. www.linleygroup.com

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Why Do Brilliant People Like to Work Together?

Why Do Brilliant People Like to Work Together?
by Daniel Nenni on 08-17-2018 at 7:00 am
Categories: Wally Rhines

This is the eleventh in the series of “20 Questions with Wally Rhines”

In high technology, there are numerous instances of highly productive groups coming together and generating game-changing ideas and products. This happened at Shockley Semiconductor in the 1960s when Gordon Moore, Bob Noyce, Jean Hoerni and more found each other and took advantage of Sherman Fairchild’s offer to start a semiconductor company. It also happened to me in Houston, Texas in 1978 (a much less likely place than Palo Alto, California).

As related in previous blogs, TI had a late start in the microprocessor contest, focused its attention on calculator chips, and was left behind by Intel and Motorola in the general purpose host microprocessor business. But failure has a way of stimulating the desperation needed for success and the group in Houston went on to develop the TMS 320, the first really successful single-chip DSP, and a host of other important technologies.

Although TI arguably has the original microprocessor patent (awarded to Mike Cochran and Gary Boone), the MOS Division was struggling just to produce MOS Memory and the Microprocessor group was focused on a strategy that would catch up with Intel by second-sourcing the 8080A, develop TI’s own set of 8-bit microprocessors and peripherals (the 5500 series) and then leapfrog with the TMS 9900 16-bit chip that would also be used by the computer and defense businesses of TI
( https://spectrum.ieee.org/tech-history/heroic-failures/the-inside-story-of-texas-instruments-biggest-blunder-the-tms9900-microprocessor ).

Brilliant junior designers like Kevin McDonough and Karl Guttag were involved in the process when I arrived in October 1978. The group was in melt-down mode because the 16-bit microcontroller, called the TMS 9940, was in its sixth or seventh re-spin and looked like it would never work. Although good engineers were resigning at a rapid rate, we had a group in Bedford, England that had just been started. This was the first case I know of where design teams were organized around the world to do 24 hour per day design, with groups of engineers assigned to a particular product in Japan, England and the U.S. could, if needed, pick up the work of each other as the sun moved around the globe and the databases remained in our IBM 4341 or IBM 7090-600 computers.

The Bedford, England design group, was assigned the task of developing peripheral chips for the TMS 9900 16-bit microprocessor. The most notable was the TMS 9914 which implemented the HP GPIB standard. The chip became a long term success despite the lack of success for the TMS 9900. The team even anticipated the risk that others would copy their chip so they went to great lengths to disguise the transistors, making enhancement mode devices look like depletion mode, just to confuse anyone who tried to copy.

A small group was assigned responsibility to develop a graphics chip for the TI Home Computer (https://spectrum.ieee.org/tech-history/heroic-failures/the-texas-instruments-994-worlds-first-16bit-computer ). While the TI 99 Home Computer was a disaster, the chip was not. It led to development of new concepts in graphics and became part of a standard known as MSX that was promoted by K. Nishi, CEO of ASCII Microsoft and was used by more than twenty different computer and video game manufacturers. Many people in graphics development are still familiar with the term “sprites”, a graphical representation that was developed by the TMS 9918 team. This same group went on to develop the TMS 340 graphics processor that was adopted by IBM for the 8514A standard that, unfortunately, experienced a short life before being replaced by VGA in the IBM PC.

About a year after I arrived in Houston (from my previous job as Engineering Manager of Consumer Products in Lubbock), we combined all the logic design resources in Houston under one manager, Jerry Rogers. Jerry had been a career enlisted man in the Navy and joined TI after retirement as a technician while he worked on his engineering degree at the University of Houston. He was an effective manager but very tough, with no sympathy for any performance less than the best. He had a thick skin and was willing to push back on management, a trait that helped with many successes. Later Jerry founded Cyrix, a very successful floating point processor and X86-compatible microprocessor company, and eventually married Jodi Shelton, Founder and CEO of GSA.

During this period in Houston, we hired an amazing array of innovative engineers. TI started a program to train new sales application engineers by assigning them to short stints in the product divisions. Rich Templeton was one of those early assignees. We liked him so well that we convinced him to join our group and give up the rotational training program and he did. Later he became Chairman & CEO of TI. K. Bala was his supervisor. One day in about 1991, Bala mentioned in a conversation with me that he thought one of his employees might be his future supervisor. “Who is that?”, I asked. “Rich Templeton, and I think he might be your boss as well”, said Bala.

Over the years, people who started their careers in that group in Houston eventually managed much of the company. We needed a marketing manager for DSPs when David French (later CEO of Cirrus Logic) was running the business so we brought in Mike Hames who was in the Bipolar PROM group and knew nothing about DSP. When Dave French left to join Don Brooks at Fairchild, we brought in John Scarisbrick to manage the DSP business and he later took it to new heights.

One of the most impressive capabilities came when we needed improved manufacturing. Yukio Sakamoto, the most capable operations manager I’ve ever known, joined us to run all the manufacturing operations. He was dissatisfied with our status and so he promoted Kevin Ritchie multiple levels to the job of DMOS 4 Wafer Fab Manager. People tell me that Kevin became one of the most effective manufacturing managers in the semiconductor industry and recently retired after a distinguished TI career as Senior VP of Technology and Manufacturing. Sakamoto became CEO of Elpida Memory, the company that combined NEC’s and Hitachi’s DRAM businesses.

The 20 Questions with Wally Rhines Series