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The Evolution of the Extension Implant Part V

The Evolution of the Extension Implant Part V
by Daniel Nenni on 05-13-2019 at 7:00 am
Categories: Events, Semiconductor Services, Threshold Systems
1 Comment

Part 4 of this series discussed how a transistor Extension could be fabricated in a planar device without using an implant operation, and is instead formed using a preferential etch followed by a selective epitaxial deposition. This final installment of the series will present the formation of an Extension in a FinFET transistor using the same etch and deposition methodology.

As in the planar case, this technique for fabricating an Extension region depends on etching out a precisely formed cavity adjacent to, and on both sides of, the transistor channel region. Also, like the planar case, this cavity etch is performed as part of the replacement Source/Drain etch that takes place prior to the epitaxial deposition of the SiGe compressive stressor. However, in the case of a FinFET, the Extension cavity is formed as part of the fin removal process.

Figure #1 illustrates PMOS and NMOS fins just prior to the Source/Drain cavity etch and the formation of the SiGe stressor crystals. The NMOS fins are coated in a protective hard mask. (Note that the PMOS fins are located in the N-Well and the NMOS fins are located in the P-Well.)


Figure #1

The process begins by etching away the PMOS fins located outside of the gate electrode. This is accomplished by first etching away the thin coating of oxide (left on the on the top of the fins after the sidewall spacer etch), and then etching away the Silicon fins using a wet etch of NH[SUB]4[/SUB]OH. Alternate etch chemistries that will also work for this task are NH[SUB]3[/SUB]OH, TMAH, KOH, NaOH, BTMH or amine-based etchants.

Once the fins are removed, the nitride spacers along the fin sidewalls will collapse and they can be easily removed from their attachment points to the Gate Electrode nitride spacer. The result of this etch is illustrated in figure #2.

 

Figure #2

Figure #2 displays the device structure after the PMOS fins have been removed. The TMAH etches preferentially into the N-Well forming the characteristic “V” shaped groove that self-limits the etch process. Perpendicular to this groove, and along the (111) plane, the TMAH etches the silicon fin more slowly and forms the Extension cavity beneath the Gate Electrode spacer. Figure #3 displays a close-up view of the Extension cavity.


Figure #3

Following the etch, a selective deposition of SiGe takes place. This operation will deposit SiGe only on the exposed silicon surfaces which restricts the deposition to the silicon in the V-shaped groove and the Extension cavity as displayed in figure #4.

Figure #4

The Gate Electrode in figure #4 has been made transparent in order to make the Extension structure visible. Figure #5 is a close up of the Extension structure that is located beneath the Gate Electrode spacer.


Figure #5

So is this technique for forming the transistor Extension actually being used?

Figure #6 displays a Transmission Electron Micrograph of an Intel 22nm PMOS FinFET gate array.

The TEM preparation of this image makes it initially difficult to understand. It is a dark-field image so the denser materials appear lighter and the view is top-down and the Gate Electrodes have been polished back to the tops of the SiGe crystals. As a result of this polish, the Gate Electrodes no longer wrap around the top of the fins but are located on either side of them. This reveals the transistor channels and the Extensions located on either side of the channels.

As the TEM illustrates, the SiGe crystals extend behind the nitride spacers and slightly into the channel region to form the transistor Extensions. Based on this evidence it would appear that the technique described in this paper has been in use for some time.

Figure #6

Forming the transistor Extensions as part of the fin removal and SiGe deposition process offers a number of important advantages. First, it is a simpler process. It eliminates all of the implant steps required of other Extension formation methodologies and their associated photo-masking operations. More importantly, it provides a robust solution for effectively forming transistor Extension regions even with the very tight Gate Electrode pitches found at the 10/7/5nm nodes.

This technique would require careful control of the fin removal etch to ensure that the Extension cavity is formed to the correct dimensions, but the advantages provided by this method far outweigh any disadvantages.

This content was authored by Jerry Healey of Threshold Systems Inc. For detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

Also read: The Evolution of the Extension Implant Part IV

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Uber’s Sandcastle

Uber’s Sandcastle
by Roger C. Lanctot on 05-13-2019 at 7:00 am
Categories: Automotive
2 Comments

As Uber’s initial public offering arrives this is a good moment to consider what kind of employment model for the future we all, as employees and employers, would prefer to adopt: Amazon or Uber?

One of my sons has interviewed with Amazon. The other has his Amazon moment today. My across-the-street neighbor works for Amazon Web Services. I don’t know anyone that works for or has “interviewed” with Uber – though I have spoken with Uber drivers all over the world.

It is worth considering the two different value propositions posed by these pivotal employers and purported economic engines. Amazon is already the second largest employer in the U.S. with 566,000 employees. Uber employs more than 22,000 people at headquarters or in support roles along with more than three million drivers.

Municipalities and states vie over incentives to entice Amazon to open facilities (headquarters, distribution centers, server farms) in their areas thereby bringing employment. Amazon leverages that local support to demand concessions such as a greening of existing power grids, for example, in the case of server farms installations.
Amazon is famous for its 14 leadership principles:

1. Customer Obsession
Leaders start with the customer and work backwards. They work vigorously to earn and keep customer trust. Although leaders pay attention to competitors, they obsess over customers.

2. Ownership
Leaders are owners. They think long term and don’t sacrifice long-term value for short-term results. They act on behalf of the entire company, beyond just their own team. They never say “that’s not my job.”

3. Invent and Simplify
Leaders expect and require innovation and invention from their teams and always find ways to simplify. They are externally aware, look for new ideas from everywhere, and are not limited by “not invented here”. Because we do new things, we accept that we may be misunderstood for long periods of time.

4. Are Right, A Lot
Leaders are right a lot. They have strong judgement and good instincts. They seek diverse perspectives and work to disconfirm their beliefs.

5. Learn and Be Curious
Leaders are never done learning and always seek to improve themselves. They are curious about new possibilities and act to explore them.

6. Hire and Develop the Best
Leaders raise the performance bar with every hire and promotion. They recognise people with exceptional talent and willingly move them throughout the organisation. Leaders develop leaders and are serious about their role in coaching others. We work on behalf of our people to invent mechanisms for development like Career Choice.

7. Insist on the Highest Standards
Leaders have relentlessly high standards – many people may think these standards are unreasonably high. Leaders are continually raising the bar and driving their teams to deliver high quality products, services and processes. Leaders ensure that defects do not get sent down the line and that problems are fixed so they stay fixed.

8. Think Big
Thinking small is a self-fulfilling prophecy. Leaders create and communicate a bold direction that inspires results. They think differently and look around corners for ways to serve customers.

9. Bias for Action
Speed matters in business. Many decisions and actions are reversible and do not need extensive study. We value calculated risk taking.

10. Frugality
Accomplish more with less. Constraints breed resourcefulness, self-sufficiency and invention. There are no extra points for growing headcount, budget size or fixed expense.

11. Earn Trust
Leaders listen attentively, speak candidly, and treat others respectfully. They are vocally self-critical, even when doing so is awkward or embarrassing. Leaders do not believe their or their team’s body odour smells of perfume. They benchmark themselves and their teams against the best.

12. Dive Deep
Leaders operate at all levels, stay connected to the details, audit frequently, and are sceptical when metrics and anecdote differ. No task is beneath them.

13. Have Backbone; Disagree and Commit
Leaders are obligated to respectfully challenge decisions when they disagree, even when doing so is uncomfortable or exhausting. Leaders have conviction and are tenacious. They do not compromise for the sake of social cohesion. Once a decision is determined, they commit wholly.

14. Deliver Results
Leaders focus on the key inputs for their business and deliver them with the right quality and in a timely fashion. Despite setbacks, they rise to the occasion and never compromise.

These principles serve as the framework for an interview gauntlet known as “having a loop.” It’s a daunting process that not all are able to conclude successfully.

Uber’s CEO, Dara Khosrowshahi, famously reworked Uber’s cultural code when he joined the company:

Uber’s Cultural Norms
We build globally, we live locally.We harness the power and scale of our global operations to deeply connect with the cities, communities, drivers and riders that we serve, every day.

We are customer obsessed. We work tirelessly to earn our customers’ trust and business by solving their problems, maximizing their earnings or lowering their costs. We surprise and delight them. We make short-term sacrifices for a lifetime of loyalty.

We celebrate differences. We stand apart from the average. We ensure people of diverse backgrounds feel welcome. We encourage different opinions and approaches to be heard, and then we come together and build.
We do the right thing. Period.

We act like owners. We seek out problems and we solve them. We help each other and those who matter to us. We have a bias for action and accountability. We finish what we start and we build Uber to last. And when we make mistakes, we’ll own up to them.

We persevere.We believe in the power of grit. We don’t seek the easy path. We look for the toughest challenges and we push. Our collective resilience is our secret weapon.

We value ideas over hierarchy. We believe that the best ideas can come from anywhere, both inside and outside our company. Our job is to seek out those ideas, to shape and improve them through candid debate, and to take them from concept to action.
e make big bold bets. Sometimes we fail, but failure makes us smarter. We get back up, we make the next bet, and we go!

The new ethos at Uber’s headquarters may or may not be conveyed to its drivers. Maybe it should be.
Given the rising volume of hiring taking place at Amazon it is hard to ignore the company’s influence on hiring practices, the economy and even the environment. That doesn’t mean all is rosy at Amazon. Amazon continues to face obstacles of its own making including resistance to economic transformation in New York – where its headquarters bid was ultimately rejected – and claims of employment discrimination and retaliation. Uber has faced and continues to face similar challenges.

Still, Amazon is rapidly supplanting IBM, Xerox, AT&T, or even the U.S. Postal Service as an attractive and sought after place of employment. As has always characterized such employment, a job at Amazon could define one’s career path for a lifetime and ensure lifelong financial security with all of the related benefits.

In stark contrast to the prospect of a job at Amazon, Uber offers a very different employment prospect. I am not writing, of course, of the 22,000 headquarters and support personnel working at Uber. I am addressing the more than three million Uber drivers laboring on the expanding Uber platform – which now includes food delivery – around the world.
Uber offers the ultimate ad hoc employment opportunity with nary an interview at all without any of the security or benefits of a traditional “desk” job. Uber drivers may be fully or partially employed, depending on the amount of hours they work.

While the comparison of Amazon’s interview process with Uber’s ad hoc employment proposition is unfair it highlights two disparate paths to building value. Uber is supporting a bloated valuation freighted with billions of dollars in insurmountable losses. Amazon has created a solid foundation from a massive and expanding infrastructure supporting a global digital and physical delivery platform.

mazon has built a fortress of customer convenience and satisfaction surrounded by a moat of logistical expertise. Uber has constructed a sandcastle of loss-producing taxi rides on the backs of itinerant and under-compensated drivers. The recent driver strike on the eve of the IPO is but a hint of trouble to come.

The future of employment in the U.S. and around the world is at stake in Uber’s IPO today. We will all serve the machines in the future but will we be nothing but lumps of meat guiding vehicles and living hand to mouth? Or will we be masters of the machines and our own destinies – respected and nurtured.

The question goes beyond the prospect of employment. Both Amazon and Uber are of sufficient size to have measurable impacts on the economy and the environment.

Amazon not only takes responsibility for its impact on the environment, in many instances it has sought concessions from government authorities to ensure the provision of green energy sources. Uber, on the other hand, recklessly and ruthlessly violates local regulations and taxes transportation infrastructure while undermining public transportation resources.

Amazon provides living wages and benefits. Uber actively undermines the livelihoods of taxi drivers around the world – with the exception of those markets where the company has sub-contracted with local taxi services.

Both companies pose a burden to transportation infrastructure. Amazon delivery vehicles and delivery agents routinely impede traffic in major cities. Uber has been blamed for worsening traffic conditions in most cities where the company operates. The implications for emissions are obvious.

As Uber executives and investors ponder the long-term viability of the company today it may be time to reconsider the treatment and compensation of Uber drivers. This applies to Lyft, Yandex, DiDi, Heetch and all the rest. Are these companies building fortresses or sandcastles? Are Uber passengers as devoted to Uber as Amazon Prime customers are to Amazon?

Both Uber and Amazon offer convenience and cost savings, but the value proposition for customers, employees, the environment, and the economy are very different. One is sustainable and one is not.

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Chip Equip Trade War Collateral Damage

Chip Equip Trade War Collateral Damage
by Robert Maire on 05-13-2019 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

We have been very vocal and perhaps the first to warn of the risks to the semiconductor and semiconductor equipment industry from the China trade war with the US. It seems that the war is now fully upon us with the imposition of 25% tariffs by the US and promised retribution by China. The semiconductor industry is at the leading edge of the “made in China 2025” program that the White House would like to blunt, and along with it the current trade imbalance.

We had also warned that the stocks have gotten too far ahead of them selves since the beginning of the year as stocks have soared will fundamentals have wallowed and more importantly, ignored the increasing trade risk which has now returned home to roost.

There should be no question as to the fact that damage will be done to the chip industry, the only question is how much and how long lasting. Some of the damage may be long lasting enough to be permanent. Other damage may go away if we ever manage to find a resolution.

From a simplistic point of view we can look at things that are made in China and subject to the tariffs but we also have to dig deeper and think about potential responses from China and other second and third order impact that is possible.

Who makes stuff in China? AEIS & UCT among others
A number of years ago, Advanced Energy shut down all its manufacturing of semiconductor power systems in Colorado and proudly moved it all to Shenzhen China for lower cost. Virtually all of their semiconductor related product which is the majority of profitability is made in China and likely caught up in the trade war. Given that AE is already suffering from a cyclical down turn in the industry and customers are already putting increased pressure on costs, the cost of a tariff would eat much if not all gross margin. It would be very difficult, if not impossible to move manufacturing as it took years to move it to China in the first place.

UCT is another sub supplier to the industry with significant manufacturing in China. The type of components manufactured by UCT carry relatively low, teenage, gross margins that would be completely swamped by tariffs such that they would be in a loss condition. Again, moving would be difficult and time consuming. Their customers, like Applied Materials and Lam have become accustomed to the low prices and would not allow increases to be passed on in any significant way.

ICHOR could benefit
On the other hand, Ichor, which is a similar supplier to AMAT and Lam of products similar to UCT does not manufacture in China and thus not susceptible to tariff troubles. We think that Ichor could see significant share gains depending on tariff impact and length of the trade war. From an investor perspective we would think about a pair trade of long Ichor and short UCTT, on trade issues.

Rare Earth elements
The technology industry uses a lot of “rare earth elements” that are primarily supplied by China which China has limited access to in the past and could once again use them as a critical lever in trade wars.

The rare earth elements are much tougher problems to try to get around as there really aren’t other sources on the planet for many of them.

As an example, “cerium”, a rare earth element is used in slurries for CMP polishing. Cabot Microelectronics, CCMP, is the leading manufacturer of CMP slurries in the US.

Yttrium is a rare earth element used in etch chambers to protect the etch chambers from “eating themselves up” as part of the etch process. Etch tools are obviously made by Lam, Applied, Tokyo Electron among others.

There are 17 “rare earth elements” that are critical to technology and many have seen prior embargoes from China as well as huge price increases. These could all be used as very strong levers in trade.

Rare Earth Elements in Technology

More Interested in Soy beans and Coal
Unfortunately, the current administration seems more interested in soy bean exports and coal production as that is where its political base of support is strongest. The technology industry has not been a priority as it has not been seen as friendly or loyal to the current administration. Even Tesla could not get the new “brains” (CPU board) for its enhanced Model 3 self driving technology exempted from the China tariff list as the board is assembled in China, even though sourced in the US.
We would expect any tech company, not just chips, with product sourced in China will get hit. Conversely we would expect more protection of the more strategically important soy bean industry.

Export Tariffs
We are remain surprised that the administration hasn’t figured out the idea of export tariffs or restrictions, on technology that China needs for made in China 2025. China has long ago figured out the restricting the export of technologically important rare earth elements or jacking up prices was very effective. We on the other hand haven’t seemed to have figured out that China is desperate for our semiconductor equipment to power the many, many fabs it is building for made in China 2025.

I have said on a number of previous occasions that we are selling China the rope that they will use to hang us in technology, at the very least we could make it very expensive or hard to get.

Obviously this would have a huge negative impact on the semi equipment industry but it may be better in the long run.

We have already permanently lost market share to Japan

We don’t think that export restrictions or tariffs would hurt us any further than we have already been hurt. It is very, very clear that after the whole Jinhua fiasco, that Chinese fab builders are looking for any way possible not to buy US made tools.

Its not like there is any love lost between the Chinese and Japanese, but right now the Japanese look a lot more attractive than Americans.

Obvious beneficiaries are Tokyo Electron, Hitachi, DNS and a host of Japanese chip companies. Most impacted will be Applied and Lam in their dep and etch businesses, least impacted will be KLA as they have much less competition.

A further leg down in the cycle and slower recovery?

We had already been concerned about the length of the current down cycle. We think its clear that memory won’t recover before the end of the year and into 2020.

A significant , ongoing trade ware with China could prove to be a further leg down in the cycle, leading to a lower bottom, and an even further impaired recovery with a longer horizon.

Right now its too early to tell but we are concerned that neither side appears to be backing down in the least and both are continuing to escalate

The stocks
We think there is a lot more trade risk in the stocks than the downside we have already seen. Initial indications are not great for a negotiated peace and the tech industry, and chips in particular have a very high exposure.

We would look to avoid those stocks with high China trade exposure or subject to tariff or retaliatory moves from China such as those we have mentioned above.

We think there is a lot more trade risk in the stocks than the downside we have already seen. Initial indications are not great for a negotiated peace and the tech industry, and chips in particular have a very high exposure.

We would look to avoid those stocks with high China trade exposure or subject to tariff or retaliatory moves from China such as those we have mentioned above.

The group could remain under pressure as this will be a slow motion train wreck over a long period of time.

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The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!

The SiFive Tech Symposiums are Heading to Six Cities in Europe in May!
by Daniel Nenni on 05-12-2019 at 4:00 pm
Categories: Events, IP, RISC-V, SiFive

Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam
Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It’s invigorating to see how the worldwide semiconductor ecosystem is energized and mobilized by the open ISA. One of the areas receiving the most attention is embedded intelligence. The RISC-V ISA is enabling designers and innovators to actively pursue solutions that employ enhanced embedded intelligence at the edge. The real-world applications of this are awesome and we are inspired by what we see!

The next leg of our tour is taking us to six cities in Europe. We’re so excited to meet the brilliant minds in and around Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam!

Cambridge Highlights
Imagination Technologies is our co-host in Cambridge. The symposium will take place on Monday, May 13, and includes a great lineup of speakers, tutorials and demonstrations. There will be keynotes by Naveed Sherwani, CEO of SiFive, and Andrew Grant, senior director of vision and AI at Imagination Technologies. There will also be presentations by Krste Asanovic, chairman of the board at the RISC-V Foundation, a member of the faculty from the computer laboratory at the University of Cambridge, IAR Systems, SecureRF and lowRISC. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Cambridge event, please visit: https://sifivetechsymposium.com/agenda-cambridge/

Grenoble Highlights
This symposium will take place on Wednesday, May 15. There will be presentations by Krste Asanovic, chairman of the board at the RISC-V Foundation, a graduate student from the LCIS laboratory at Grenoble INP, and presentations by SecureRF and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Grenoble event, please visit: https://sifivetechsymposium.com/agenda-grenoble/

Stockholm Highlights
With Qamcom as our co-host, this event will take place on Friday, May 17, and will include a powerful lineup of speakers. There will be keynotes by Krste Asanovic, co-founder and chief architect at SiFive, and Olof Kindgren, senior digital design engineer at Qamcom. There will also be presentations by a professor at KTH, The Royal Institute of Technology, IAR Systems, Antmicro and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Stockholm event, please visit: https://sifivetechsymposium.com/agenda-stockholm/

Moscow Highlights
SiFive and Syntacore are jointly hosting the symposium in Moscow on Monday, May 20. It will feature several presentations by key industry veterans and luminaries. There will be keynote presentations by Alexander Redkin, CEO of Syntacore, and Krste Asanovic, co-founder and chief architect at SiFive. There will also be presentations by IAR Systems, UltraSoC and other ecosystem partners. A lead researcher from ISP RAS (Russian Academy of Sciences) will also be presenting. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Moscow event, please visit: https://sifivetechsymposium.com/agenda-moscow/

Munich Highlights
Mentor is our co-host in Munich. This event will take place on Thursday, May 23, and features a great lineup of speakers. There will be a presentation by Krste Asanovic, chairman of the board for the RISC-V Foundation, and keynote presentations by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive, and Petri Solanti, senior field applications engineer at Mentor. There will also be presentations by IAR Systems, Rambus and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Munich event, please visit: https://sifivetechsymposium.com/agenda-munich/

Amsterdam Highlights
This symposium will take place on Wednesday, May 29. Some of the highlights include a keynote presentation by Sunil Shenoy, senior vice president and general manager of the RISC-V Business Unit at SiFive. There will also be presentations by Imagination Technologies and other ecosystem partners. Attendees will also have an opportunity to see demonstrations and learn about the latest design platforms for RISC-V based SoCs, development boards, IP, software and more. For more information on the Amsterdam event, please visit: https://sifivetechsymposium.com/agenda-amsterdam/

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The Evolution of the Extension Implant Part IV

The Evolution of the Extension Implant Part IV
by Daniel Nenni on 05-10-2019 at 2:00 pm
Categories: Events, FinFET, Semiconductor Services, Threshold Systems

Perhaps the most innovative and effective Extension implant does not involve an implant at all, but is instead an etch followed by a selective epitaxial deposition.

In this Extension fabrication methodology the Source/Drains regions in a planar device are etched away in the normal fashion to accommodate the replacement Source/Drain stressor material (SiGe for the PMOS device and SiC for the NMOS device). This etch is sometimes called the “Sigma” etch. It begins with an HF etch to remove any native oxide present on the surface of the silicon. (Note that the Halo implant is already in place.)

Next, the Source/Drain regions are etched out using a wet etch of NH[SUB]4[/SUB]OH. Alternate etch chemistries that will also work for this task are NH[SUB]3[/SUB]OH, TMAH, KOH, NaOH, BTMH or amine-based etchants.

Initially, the wet etch creates a facet in the lateral direction for a short distance in the channel region beneath the spacer and the gate dielectric and along the {010} plane (refer to Figure #1). This is followed by the formation in the Source/Drain region of an angled facet along the {111} plane. This etch chemistry is substantially preferential in the {111} crystallographic plane and therefore the silicon is etched more deeply in that direction.

The hard mask on the top of the Gate Electrode protects the polysilicon during this wet etch.

Figure #1

The {010} facet creates a precisely shaped Extension cavity that will define the Extension region of the transistor, and when it is filled with N-doped silicon, it will become the Extension of the transistor.

The Source/Drain cavities are then filled with Epitaxially deposited SiC or simply conventional Silicon that is in-situ doped with Phosphorus (refer to Figure #2).

Figure #2

In this methodology the Extension of the transistor is defined by the precisely etched {010} undercut of the gate dielectric, as illustrated. It is claimed that this well-defined structure provides superior dimensional control compared to an implanted Extension, as well as improved short channel effects.

Figure #3 displays the resulting structure when this technique is employed with two adjacent Gates Electrodes. In this instance the wet etch is self-limiting.

Figure #3

After forming the {010} facet, the wet etch will progress along the two {111} facets of the two adjacent transistors until the two {111} facets meet and form a “V” shape. Because of the etch’s directional preference for the {111} plane, once the facets from the two transistors join up to form a “V”, the rate at which the etch proceeds into the substrate decreases. In this respect the etch is self-limiting.

In addition, the depth of the joined facets formed by the “V” can be controlled by controlling the pitch of the adjacent transistors.

The Source/Drain cavities are then filled with N-doped SiC or with Epitaxially deposited Silicon that is in-situ doped with Phosphorus (refer to figure #4).

Figure #4

The Extension of each transistor is now defined by the precisely etched {010} undercut of the gate dielectric, as illustrated. Thus, the Extension of the transistor is formed without an implant operation and this reduces process complexity and produces a superior Extension structure. It is also claimed that this well-defined Extension provides superior dimensional control than an implanted Extension as well as improved short channel effects.

This content was authored by Jerry Healey of Threshold Systems Inc. For detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

Also read: The Evolution of the Extension Implant Part III

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Three Reasons Why You Should NOT Miss 56thDAC

Three Reasons Why You Should NOT Miss 56thDAC
by Daniel Nenni on 05-10-2019 at 7:00 am
Categories: Events

Reason number ONE:The next five DACs will be in San Francisco and this will probably be the last one held in Las Vegas so you absolutely do NOT want to miss it. One of my most memorable DACs was in Las Vegas in 1985. My wife came with me for our second honeymoon and, by definition, it was just that, a honeymoon. This year we will probably spend more time at the conference but you never know, it is Las Vegas.

Reason number TWO:The release of an updated version of our groundbreaking book “Fabless: The Transformation of the Semiconductor Industry”. It has grown more than 60 pages and includes updates from eSilicon, Synopsys, Mentor Siemens, Cadence, ARM, and new “In Their Own Words” entries from Achronix, Methodics, and Wave/MIPS. Also included are industry updates on: FPGA, Foundry, EDA, IP, TSMC, GLOBALFOUNDRIES, and a new sub chapter on IP Management. Most importantly there is a NEW chapter 8: “What’s Next for the Semiconductor Industry” written by EDA icon Dr. Walden Rhines.

At 56thDAC I will be speaking in booth #1321 and signing copies of the book courtesy of Methodics. A free PDF version will be available on SemiWiki.com after 56thDAC.

Reason number THREE:The program. Rob Aitken is the Chairperson and he definitely thinks outside of the box as you can see from the keynotes. Rob is a great guy, if you have not met him you should, he is a tireless contributor to the semiconductor industry. Rob and I talked about the keynotes and I can’t remember a better line-up. Seriously, Thomas Dolby?!?! I grew up with his music and I am always up for a DARPA talk. Reverse engineering the brain? I hope I remember to attend that one!

Game Changers: How Automation Has Changed the Gaming Industry
Monday, June 3 | 9:00am – 9:20am
Mark Yoseloff, PhD – Univ. of Nevada, Las Vegas, NV

Cutting Edge AI: Fundamentals of Lifelong Learning and Generalization
Monday, June 3 | 1:00pm – 1:45pm |
Hava T. Siegelmann, Defense Advanced Research Projects Agency (DARPA)

Hors D’Oeuvres from Chaos
Tuesday, June 4 | 9:20am – 10:00am
Thomas Dolby, Musician, Producer & Innovator, Johns Hopkins Univ.
Thomas Dolby – Youtube

March of the Machines – Building Ethical AI
Tuesday, June 4 | 1:00pm – 1:45pm |
Carolyn Herzog – Arm, Ltd

From student project to tackling the major challenges in realizing safe & sustainable electric vehicles
Wednesday, June 5 | 9:20am – 10:00am |
Bas Verkaik, Founder, SPIKE

The Memory Futures
Wednesday, June 5 | 1:00pm – 1:45pm |
Gurtej S. Sandhu, Micron Technology, Inc.

Reverse Engineering Visual Intelligence
Thursday, June 6 | 9:20am – 10:00am | N250
James DiCarlo, MD, PhD, Massachusetts Institute of Technology

RESEARCH TRACK HIGHLIGHTS
To accommodate this year’s large number of accepted papers, we have organized forty-four technical sessions conducted in five daily parallel tracks. A few highlights from this year’s conference include twenty-two papers (four sessions) on machine-learning and artificial-intelligent architectures. For example, session 31, Emerging Technologies Meet Intelligent Machines, highlights recent advances in emerging device technologies for hardware implementation of neural networks. While session 61, ET meets AI: Emerging Technologies for Accelerating AI, explores emerging memory technologies such as RRAM and 3D die-stacked memory, and novel computing ideas such as stochastic computing to achieve low power consumption while improving performance and maintaining sufficient accuracy.

Other highlights from this year’s conference include twenty-eight papers (five sessions) dedicated to hardware, embedded and cross-layer security. For example, session 41, Hide and Seek: Encryption and Obfuscation, presents methods and tools for quantum-resilient cryptography and piracy-resilient hardware. While session 52, Secure and Private Embedded System Design, focuses on security and privacy of future embedded systems in the context of consumer privacy solutions and secure communication/computation.

In terms of core EDA technical paper highlights, RTL and high-level synthesis continues to be a popular research area with twelve papers (four sessions). For example, session 34, What happens in logic synthesis stays in logic synthesis, presents advances in traditional logic synthesis and emerging applications.

This year, physical design and verification, lithography and DFM continues to be another popular core EDA topic area with sixteen accepted papers (three sessions). For example, session 64, Deep Manufacturing : Design, Data, and Machine Learning, where you will learn how deep learning is opening doors to new approaches for Design for Manufacturing.

For a complete list of technical sessions, please visit this year’s online DAC program.

Research Panel Highlights:
7 research panels in machine learning, security/privacy, autonomous systems, architecture, design and CAD, provide exciting opportunities to hear internationally renowned experts from industry, academia and government debate critical controversial topics, such as:

  • Will revolutionary computing hardware and software such as Quantum Computing lead a major paradigm shift for future EDA?
  • Is open-source EDA making a comeback to lead the future or is it just another hype?
  • Will open-source hardware live up to the promise of offering better security against malicious attacks than traditional proprietary architectures?
  • Will in-memory computing for machine learning ever become reality or is it all just a fallacy?
  • Can we ever trust AI to provide robust cybersecurity given that the machine learning models and algorithms are themselves vulnerable to adversarial manipulation?

And please someone have an Elvis impersonator in your booth…. Viva Las Vegas!

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ESD Alliance CEO Outlook Features Powerhouse Lineup

ESD Alliance CEO Outlook Features Powerhouse Lineup
by Bob Smith on 05-09-2019 at 2:00 pm
Categories: ESD Alliance, Events, Semiconductor Services

Just two more weeks before the 2019 CEO Outlook Thursday, May 23, at SEMI. If you haven’t registered yet, do so today. We’re expecting a full house as a result of our powerhouse lineup and networking opportunities.

That lineup includes Ed Sperling, editor in chief of Semiconductor Engineering, who will serve as moderator. Panelists will be John Chong, vice president of product and business development for Kionix, Jack Harding, president and CEO of eSilicon, John Kibarian, PDF Solutions’ president and CEO, and Wally Rhines, CEO emeritus of Mentor, a Siemens Business.

The panel’s unfamiliar composition is intentional. We are acknowledging our move into SEMI where the focus is on the entire electronic product design and manufacturing chain, not just electronic system design. Two member companies are part of our Governing Council, while two, eSilicon and Kionix, a division of Rohm, have experience in other supply chain segments. Kionix is the third largest supplier of MEMs devices to the electronics industry. eSilicon is a fabless semiconductor design company and a leader in FinFET ASIC design and 2.5D packaging integration.

The evening begins at 6 p.m. with networking, dinner and drinks. The panel discussion begins at 7 p.m. and goes until 8:30 p.m. For anyone who wants to miss the traffic to Milpitas, registration opens at 5:30 p.m. Everyone from the electronic system and semiconductor design ecosystem is welcome to attend free of charge, though advance registration is required.

SEMI is located at 673 S. Milpitas Boulevard, Milpitas, Calif.

ESD Alliance’s 10-Member Governing Council
Results are in, votes are counted and we offer a hearty welcome to our 10-member Governing Council who will serve a two-year term.

Returning Governing Council members are:

  • Aart de Geus, chairman and co-CEO of Synopsys, Inc.
  • Dean Drako, president and CEO at IC Manage
  • John Kibarian
  • Wally Rhines
  • Simon Segars, CEO at Arm
  • Lip-Bu Tan, CEO of Cadence Design Systems

New Governing Council members Raik Brinkmann, president and CEO of OneSpin Solutions, Prakash Narain, president and CEO of Real Intent and David Dutton, CEO of Silvaco. Congratulations to all!

As executive director of the ESD Alliance, I am a member of the council as well.

ESD Alliance’s ES Design West
We’re working hard to make the inaugural ES Design West July 9-11 co-located with SEMICON West 2019 at San Francisco’s Moscone Center South Hall a success. As its host, we are working diligently to showcase the design ecosystem’s innovation and commercial successes from IP, EDA and embedded software to design services, design infrastructure and the cloud. And, we are continuing to see more companies sign up to exhibit at this inaugural event.

The Advisory Council has done an outstanding job of lining up topics and speakers that will satisfy a broad range of interests. Attendees can expect presentations and panel discussions showcasing electronic system design, its business achievements, commercial technological accomplishments and role in the broader electronics manufacturing supply chain. Exhibitors are enthusiastic and preparing for a great event. The result will be an event that enabled and accelerate conversations, information exchange and collaboration to address common issues, challenges and opportunities that move new electronic products from concept to consumer.

Details can be found at the ES Design West website.

Follow ES Design West on Twitter: #ESDesignWest and @ESDAlliance

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Bottom of a Semiconductor Canoe Cycle Shape

Bottom of a Semiconductor Canoe Cycle Shape
by Robert Maire on 05-09-2019 at 12:00 pm
Categories: Semiconductor Advisors, Semiconductor Services

Nice numbers despite the cycle bottom
KLA put up EPS of $1.80 versus street of $1.67 on revenues of $1.097B versus street of $1.08B. However guidance was weaker than the street was hoping for with a range of $1.21B to $1.29B in revenues generating between $1.55 and $1.85 in non GAAP EPS. This is compared to current street estimates of $1.21B and EPS of $1.88.

Obviously the inclusion of Orbotech added slightly to the complexity but it seems fairly straight forward.

Given that the stock was down in the after market its safe to assume that investors were somewhat underwhelmed by the June quarter guidance.

March is the bottom of a “canoe” shaped down cycle
We have talked a lot about the shape of the semiconductor cycle and it seems fairly clear that we are not in a “V” shaped bottom nor even a “U” shaped bottom but rather an extended, flattish bottom shaped a bit like a “canoe”. Managment confirmed their prior view that March is the likely bottom but the bottom is very flat and we are not seeing a “bounce” off the bottom but rather a slow and shallow recovery.

To be clear, this cycle shape is not unique to KLA as the whole industry is in this soft, murky bottom waiting for memory pricing to stabilize and excess supply to get sopped up so that memory spending can recover. Until then the industry will bump along at lower levels subsisting primarily on foundry and logic spending.

Orbotech Upside
KLA’s acquisition of Orbotech couldn’t have come at a better time as the diversity away from mainstream, core, semiconductor tools, will help during the down cycle. The expected roughly $50M in synergies should be easily achieved.

Orbotech gives KLA more diversity than Lam, AMAT or ASML. AMAT does have the display business , but the display business makes the semiconductor business look stable by comparison.

While Orbotech is certainly not large enough to offset all of the cyclicality of the core semiconductor business , it will, none the lessen, dampen the volatility.

China Downside
Of the group, KLA has one of the highest exposures to China. The recent negative news about the China trade deal sounds like things have gone backwards. While KLA is critical to China’s chip business and tariffs don’t YET affect exports, the worsening trade environment is an added risk that investors will likely be concerned about. KLA could be collateral damage if things escalate.

Yield management still better than process
In our view, yield management remains the best segment in the semiconductor tool space. Process tools, especially dep & etch, are most impacted by the memory slowdown and KLA’s traditional bias toward foundry & logic helps given that those sectors are the ones spending the most money right now.

A slow ramp into H2
It sounds like things will slowly improve into the second half but no real bounce back, just continued improvement. Our guess is that the balance of 2019 remains weak with some marginal improvements until we get a true recovery in the memory business.

Its important for investors to remember that even if memory pricing increases, due to capacity being artificially taken off line, spending will not recover until excess capacity has been used up and demand gets back on track.

This means that even though memory pricing may stabilize or get better, it could still take a few quarters before that trickles down to tool makers.

Will investors get impatient?
We have asked this question before as the stocks have flown way ahead of reality. While we think KLA remains one of the best of the group, given its positioning and now new diversity, we think part of the negative reaction in the after market is that perhaps investors are hoping for a faster recovery that is not coming.

The stocks
In general, we don’t see KLA’s report as being much different than expected with perhaps a bit more tepid outlook. We have suggested this will be a slower recovery and investors may get more unhappy and frustrated as time goes by.

The negative China news today will also obviously weigh on the group and could get worse through the week. The has the potential to become a catalyst.

Our view remains that most of the stocks are ahead of themselves and have a lot of air that could quickly come out with negative news points (like China).

Of the large cap stocks, KLA is perhaps our favorite, but we see no reason to pay the currently overly high valuation in the face of a slow lumpy recovery coupled with other risks.

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Meeting Automotive IC Design Challenges for Safety using On-Chip Sensors

Meeting Automotive IC Design Challenges for Safety using On-Chip Sensors
by Daniel Payne on 05-09-2019 at 7:00 am
Categories: Automotive, Moortec

I’ve been driving cars since 1978 and have even done a few DIY repairs in the garage, so I know how warm the engine compartment, transmission or exhaust system can become which makes automotive IC design rather unique in terms of the high temperature and voltage ranges that an electronic component is subjected to. Our safety while driving a car is paramount, so automotive designers have a big responsibility to manage the electronic subsystems that are hidden from view. Recent advances in ADAS (Advanced Driver Assistance Systems) by the major automotive companies along with EV startups like Tesla, are also adding an unprecedented number of ICs and sensors like RADAR and LiDAR to our vehicles.


ADAS Features. Source: Robotics & Automation

Ideally then, at the chip-level, your designers would like to know what the Process variation, Voltage levels and local Temperatures (PVT) are so that they can control the chip operation, keeping it operating safely and within specifications, instead of failing from heat-induced electromigration failures or supply voltages out of spec. Let me just summarize some of the automotive IC design challenges:

  • Reliability
  • Adherence to standards like ISO 26262
  • Long term commitment from suppliers
  • Monitoring aging effects
  • Drift
  • Safety
  • Long development cycles

ISO 26262. Source: National Instruments

ITRI Industrial International forecasts an 11.9% annual growth rate for automotive electronics from 2017 to 2022, so that has the IC design community highly motivated to design new chips to meet the challenges of ADAS. On the infotainment side our cars are becoming mobile hotspots, enabling us to enjoy non-stop smart phone use along with new ways of controlling the car dashboard with our voice or touching a screen.

Chips inside of cars can use bleeding edge 7nm silicon from Samsungor TSMC, all the way up to mature 180nm nodes. The smaller the node, the greater the impact of process variation has on the reliability. If you knew which process corner each block was operating under, then you could take design steps to control the frequency and voltage levels in order to stay within your power spec for example.

Thermal effects continue to be important for automotive ICs:

  • FinFET structures are less able to dissipate heat than planar CMOS
  • Increased density is leading to increased thermal challenges
  • Electrical OverStress (EOS)
  • Electromigration (EM)
  • Hot carrier aging
  • Increased Negative Bias Temperature Instability (NBTI)
  • Device leakage causes heat and heat causes more leakage (Thermal runaway)
  • Leakage to increase when we move from one FinFET node to the next smaller node

Ashish Kumar Gupta from Freescale Semiconductors summarizes thermal concerns, “Designers face new challenges of providing thermal-efficient systems that balance or equally distribute possible on-chip hot spots. In this scenario, Dynamic Temperature Management (DTM) techniques arise as a promising solution. DTM relies on accurately sensing and managing on-chip temperature, both in space and time, by optimally allocating smart temperature sensors in the silicon.“

Fortunately for new chip designs targeted at automotive you don’t have to create your own semiconductor IP for PVT monitoring, because there’s a vendor focused solely on PVT monitoring fabrics, Moortec. They are members of the TSMC IP Allianceand have over a decade of experience in this domain. Their in-chip monitoring subsystem IP is silicon proven at 40nm, 28nm, 16nm, 12nm and 7nm, so that’s a wide range to choose from. In addition the IP that Moortec supplies to TSMC users has passed the rigors of the TSMC9000 quality program.


Source: TSMC

Engineers want to know how all of the pieces fit together for IP, so here’s a diagram that shows the concept of connecting multiple PVT monitors and a subsystem to control them.


PVT Sub-system

For automobiles the environmental temperature range is typically -40C to 125C, but the junction temperature of the IC is going to be even hotter than 125C worst case based on the number of transistors, process node, operating frequency and voltage levels. Having multiple Temperature monitors on-chip is a wise choice in managing the thermal specification. As a chip reaches its thermal limits then the control logic can be used to lower voltage levels, decrease frequency or a little of both.

As IC designers identify thermal hotspots in the layout, then engineers can judiciously place Thermal monitors around the chip in order to measure junction temperatures in realtime, then take corrective action when needed.

Summary
The process variation, voltage variation and thermal challenges of designing automotive ICs can be met by placing multiple PVT monitor IP blocks as a fabric across your chip. Moortec is the leader in PVT monitoring subsystems from 40nm through 7nm nodes and has plenty of silicon proven results and use case experience, so that you can quickly use their IP and control how your chips react to variations, keeping them safe and operating within spec.

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eSilicon ASICs all in the Google Cloud

eSilicon ASICs all in the Google Cloud
by Daniel Nenni on 05-08-2019 at 12:00 pm
Categories: eSilicon, Semiconductor Services
4 Comments

Having just completed a cloud evaluation for SemiWiki I can tell you why eSilicon chose Google. Simply put, they are working harder to get cloud business. Google ($4B) is the number five cloud provider behind Microsoft ($21.2B), Amazon ($20.4B), IBM ($10.3B) and Oracle ($6.08B). There is a lot of money in the cloud and a lot more to come which is why cloud providers are designing their own chips and partnering with ASIC providers like eSilicon to get that competitive edge. Speaking of ASICs in the cloud:

eSilicon Signs Multi-Year Agreement with Google Cloud
Under the terms of the agreement, Google Cloud will provide support from their professional services team to assist eSilicon as it moves its ASIC and IP design workloads to GCP. eSilicon has been running a hybrid on-premise/cloud environment for approximately the last 18 months, with ASIC design running on premise and IP design running primarily on GCP. This new agreement paves the way for a complete migration of all design activity to GCP.

“Google Cloud has demonstrated the resources, technical depth and domain knowledge to successfully move IC design to GCP, a significant undertaking,” said Naidu Annamaneni, CIO & vice president of global IT at eSilicon. “There are many unique requirements to support this kind of workload on the cloud and the need to collaborate with several infrastructure vendors to create the complete solution. Google Cloud possessed the domain knowledge and operational focus, backed by a substantial worldwide computing capability to get the job done.”

“Moving to the cloud provides the flexibility to build the right compute environment for each design project, resulting in improvements in time-to-market and design quality,” said Mike Gianfagna, vice president of marketing at eSilicon. “This is a substantial project with a lot of innovation and many partners. We’ll be talking more about this fast-paced program at it unfolds over the coming months.”

The big news here is that eSilicon is committing to move ALL ASIC and IP design to the Google Cloud Platform (GCP). They have been operating in a hybrid cloud environment for about a year and a half and now they are taking the next big step. Most of the chip design cloud activity today is hybrid so eSilicon is blazing trails here.

When it’s all said and done, there will be very few computers left inside eSilicon with all major infrastructure served in a flexible, cost effective, and highly secure way with GCP. Cost and security is critical but it’s the flexibility that makes the cloud a no-brainer for chip designers.

Remember, chip design is spiky in regards to compute resources. Processor speed, memory and storage requirements can vary a great deal, especially during the tapeout phase. There is no way an on-premise server farm can be competitive with a cloud offering during a tape-out. eSilicon can now apply the required compute resources needed to meet schedules, perform rigorous verification and deliver world-class ASICs. This ability to apply massive compute resources only when needed is unique to the cloud. The result is a higher quality design and all-important first-time-right silicon which is a make-or-break for the ultra competitive ASIC business.

The downside of the cloud is that you get what you ask for so you had better be careful what you ask for. For example, SemiWiki cloud resource requirements are easily predicted. Google cloud load balancing is as simple as adding a CPU, memory, or disk in a matter of clicks. eSilicon on the other hand is applying machine learning algorithms for an intelligent orchestration layer that assesses the need of a specific design project in regards to compute resources. It also manages costs based on project budgets from IP to full chip design. Expert resource management is a normal part of the ASIC business but with ML and the cloud it will be a completely different type of business, absolutely.

AbouteSilicon
eSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC™ platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com