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Using ML to Build Efficient Low Power Platforms for Augmented Vision

Using ML to Build Efficient Low Power Platforms for Augmented Vision
by Tom Simon on 04-16-2019 at 7:00 am

We are all pretty familiar with augmented reality, where real world images are overlaid with computer generated images, graphics and even audio. Of course, our first exposure to augmented reality might have been images of heads up displays in fighter jets or perhaps in the movie The Terminator. Augmented reality is moving rapidly towards mobile devices, handhelds and also automotive applications. Developing augmented reality systems on these new platforms requires crucial decisions about the image processing implementation.

For system level and embedded processing vision, we have several choices, which include GPUs, FPGAs, vision DSPs, or vision DSPs combined with neural networks. The considerations include cost, energy efficiency and performance.

At Embedded World 2019 Synopsys presented a paper on implementing augmented reality in low-power systems. The presenter was Gordon Cooper, product marketing manager for processor IP at Synopsys. One focus of his presentation was simultaneous localization and mapping(SLAM), which is the technique used to determine the actual 3-D location of objects relative to the camera. To do this in real-time a 3-D model of the environment must be produced and the location of the camera must be determined. Often a two-camera technique is used which relies on stereoscopic vision to determine distances. However, many new systems only have a single camera, so techniques are needed to determine distance using monocular SLAM.

Using a single camera requires more complicated algorithms. Depth cannot be directly inferred from a single image because it can be difficult to determine absolute scale. So, Synopsys asks the question as to whether neural networks can be used to improve depth maps for monocular SLAM. They found that this has been studied and can be an attractive approach, as shown in the paper titled Predicting Depth, Surface Normals and Semantic Labels with a Common Multi-Scale Convolutional Architecture, by David Eigen, Rob Fergus, 2015. This paper shows that with just a two-dimensional RGB image it was possible to output a depth map as well as determine the surface normals.

For real time processing, frame rates of above 25 frames per second are necessary. This means that just 30 to 40ms of total processing time is available to avoid significant latency. Coming back to the question of implementation, it is clear that GPUs can be useful for running neural networks, but they may consume too much power for automotive applications. CPUs may be able to perform SLAM but again there’s the question of performance, power and area. Synopsys’ solution is to combine these functions into a single embedded processor which contains a 32 bit scalar unit, a vector unit and a neural network engine.

Software is the other important element of the complete solution. The software must perform feature extraction and feature matching between frames to determine camera motion. Additionally, there must be support for a variety of different neural network types. Synopsys offers its OpenVX framework which includes C/C++, OpenCL C, OpenCV, OpenVX libraries, and CNN mapping tools. With this their customers can develop user applications that address their specific requirements.

Synopsys also supports a number of optimizations including feature map compression in hardware, which offers runtime compression and decompression, use of simplified Huffman encoding, and CNN DMA with a hardware compression mode. In addition, there is coefficient pruning, where coefficients with zero value are skipped/counted, leading to dramatic reductions in the number of required operations.

Synopsys believes that properly implemented vision processors that include neural networks can help improve SLAM accuracy in determining depth perception and scaling. At the same time these vision processors can help improve performance and lower power consumption, which will be needed in many of its applications. Although we do not necessarily see augmented reality used on a day to day basis yet, it will probably be one of those things that gathers momentum and will soon become something that we rely on for numerous daily activities, such as driving, learning new skills or appreciating the world around us. More information on Synopsys vision processing solutions for SLAM and CNN can be found on their website.


TechInsights Gives Memory Update at IEDM18 NAND Flash

TechInsights Gives Memory Update at IEDM18 NAND Flash
by BHD on 04-15-2019 at 12:00 pm

On the Sunday evening at IEDM last year, TechInsights held a reception in which Arabinda Das and Jeongdong Choe gave presentations that attracted a roomful of conference attendees. Arabinda was first up, giving a talk on the “10-year Journey of Apple’s iPhone and Innovations in Semiconductor Technology”, followed by Jeongdong discussing “Memory Process, Design and Architecture: Today and Tomorrow”.
Continue reading “TechInsights Gives Memory Update at IEDM18 NAND Flash”


From Wild West to Modern Life the Semiconductor Evolution

From Wild West to Modern Life the Semiconductor Evolution
by Daniel Nenni on 04-15-2019 at 7:00 am

What started as blogs, or vignettes as Wally calls them, posted on SemiWiki is now a free PDF eBook. The journey starts with his school days at Stanford through 20+ years at TI and 24+ years at Mentor Graphics. Wally has traveled millions of miles meeting with every customer imaginable while presenting hundreds of different keynotes on the semiconductor industry. If we ever came out with an AI smart speaker on all things semiconductor it would be called Wally.

The crowning achievement of Wally’s career (my opinion) and one of the most disruptive moves in EDA history is the acquisition of Mentor Graphics by Siemens in 2017 for $4.5B (representing a 21% stock premium). Acquisition rumors had been flying around the fabless semiconductor ecosystem but no one would have guessed it would be the largest industrial manufacturing company in Europe. At first the rumors were that Siemens would break-up and sell Mentor keeping only the groups that were part of the Siemens core business, specifically they would sell the Mentor IC Group. Those rumors were flatly denied at the following Design Automation Conference during a CEO roundtable with Wally. Now Mentor, including the IC group, is an integral part of the Siemens corporate strategy. Thank you again Dr Walden Rhines, EDA would not have been as fun without you, absolutely.


From LinkedIn:
Wally Rhines is widely recognized as an expert in business value creation and technology for the semiconductor and electronic design automation (EDA) industries. Dr. Rhines was CEO of Mentor Graphics (a “Big Three” EDA company with $1.3B+ revenue) for 24 years, has served on the boards of four public companies, managed the semiconductor business of Texas Instruments (TI), and is a spokesperson, writer and highly-sought-after speaker for the high-tech industry delivering more than twenty keynotes per year.

Dr. Rhines currently serves as CEO Emeritus of Mentor, a Siemens Business, consults for investors, corporations and the U.S. government on strategic directions, value creation and technology, serves on public and private boards, and supervises a $20M foundation. Business achievements include major turnarounds, both at Texas Instruments, through his creation and management of the digital signal processing business, and at Mentor, where he managed more than 3X growth in revenue and a 10X increase in enterprise value before acquisition by Siemens AG.

Dr. Rhines’ technical expertise includes semiconductor design, process engineering and manufacturing as well as financial modeling of trends and value creation. He has been deeply involved in global business development including projects in China and India.

As CEO and Director, he has managed businesses through difficulties including unfriendly takeover attempts, favorable outcomes for both the company and the activists, with three of the world’s leading activist investors, and volatile economic and business cycles. He continues to seek new opportunities to grow businesses, particularly through private equity, consulting and personal investing.

From the book:

From Wild West to Modern Life the Semiconductor Evolution

Foreword

In 1968, Texas Instruments, Motorola, and Fairchild dominated the emerging semiconductor business with 66% combined market share. Over the next fifty years, the industry de-consolidated – dozens of new semiconductor companies emerged, creating a more dynamic market that altered the list of the top ten largest companies.During the same period, an ecosystem of companies emerged to grow the materials, develop the manufacturing equipment, design the software, and create all the other capabilities needed to support what has become one of the most strategic industries in the world. Much of this evolution was driven by relatively young, inexperienced individuals operating in a totally unregulated,free market, worldwide business environment. I was privileged to work with many of these people and to be involved in some of the revolutionary innovations.Many people, including Daniel Nenni, have asked me to relate some of the stories of game-changing programs and people with whom I was involved,including the dynamics of growth of the Electronic Design Automation (EDA) industry. I’ve put this off for a long time, but Daniel is persistent. So I started writing some short vignettes during long airline flights. This activity required that I contact other people who were involved in this history, some of whom I hadn’t seen for decades, to verify the accuracy of my recollections. I hope this collection of essays provides some feeling for the remarkable history of the growth of an industry as well as insights into its future evolution.

Walden Rhines
March 2019


An old IP theft gets a new Chinese label

An old IP theft gets a new Chinese label
by Robert Maire on 04-14-2019 at 7:00 am

The Dutch financial newspaper Financieele Dagblad (FD) reported on the past theft of ASML technology after doing some investigative digging. It now appears that a number of Chinese nationals and ASML employees, in ASML’s Santa Clara office stole key technology back in 2015. Though ASML talked about it at the time, little was said, with no further information disseminated.

Brion technology was stolen
Brion technology, which ASML acquired back in 2006, makes software which optimizes the results of the mask and scanner working together to produce better and finer lithographic images. It is critical technology as it greatly improves the performance of scanners and allows sharper and finer images to be printed thus enabling Moore’s law.

The technology was passed on to XTAL, a Chinese company with clear Chinese government connections. ASML apparently figured it out back then when XTAL started stealing customers away from ASML (obviously with ASML’s own software…). XTAL was started by two former ASML/Brion employees, other co-conspirators also had worked at D2S, KLA, Hermes (bought by ASML), Mentor Graphics and Synopsis. Its hard to estimate how much money ASML lost but it was obviously significant.

USB thumb drives are spy tradecraft
As we saw in the Jinhua/UMC/Micron case, employees simply walk out the door of the victim company with all the trade secrets they can copy on a USB drive. Probably the only limit to the theft is the size of the drive. Its very hard to prevent this sort of theft and we are very sure it occurs in every semiconductor company of size, every day of the week.

It is also clear that China is helping, encouraging and probably directly acting to obtain any and all technical information in the semiconductor industry to reach their made in China 2025 goal, through any and all means.

US and others have been unable to stop the loss
So far we have not only been powerless to stop the covert loss through spying but we have also been unable to stop the overt loss through the required “technology sharing” enforced by the Chinese government. Key technology is exiting the back door in USB drives and out the front door in “technology sharing” arrangements.

ASML swept it under the rug to avoid riling China & regulators
ASML kept the theft quiet for years until the newspaper FD dug it up. ASML also publicly denied the clear case of Chinese spying by saying;

“The suggestion that we were somehow victim of a national conspiracy is wrong,” CEO Peter Wennink said ,”We resent any suggestion that this event should have any implication for ASML conducting business in China. Some of the individuals (involved) happened to be Chinese nationals,” he added.

The corporate thieves just “happened to be” Chinese, who “happened to be” working for a Chinese company (XTAL is a subsidiary of Dongfang Jingyuan), which “happened to be” financially sponsored by Chinese government, that’s a lot of happenstance.

Saying that the Chinese stole from ASML wouldn’t get the stolen property back and would only tick off the Chinese government, and we saw what happened to Micron when they accused a Chinese related company of theft, they got shut down in China. In addition, if ASML were to broadcast the fact that China ripped them off it would give the US government and European regulators even more reason to shut down sales of ASML products in China….best to make the problem go away.

XTAL is gone but the problem lives on
After the $223M judgement against XTAL, they will likely go belly up. God only knows where the stolen software wound up. You can’t put the toothpaste back in the tube. Microns memory process is probably for sale on the dark web as well.

Scanners are too big to steal
Obviously stealing the plans for an ASML EUV scanner would be useless as it would be virtually impossible to duplicate one given the very specialized components, yet stolen software can be easily transported, hidden and used. All semiconductor processes and tools have a lot of software and there are many tools that can actually be easily copied . AMAT and Lam have had past problems and likely already have and will have more problems. KLA has high software content in their tools that is vulnerable.

The industry needs to increase its vigilance significantly as the problem won’t go away with a trade agreement (if we ever get one). We are sure the problem is only getting worse as no concrete steps have been taken to prevent it.

We told you so…
We gave a talk about China’s aspirations and potential issues with IP at Semicon West in 2018. This is a link to the presentation in which we spoke about these issues:

“China Chips- Semicon West 2018”

More Information on ASML/XTAL

XTAL’s website

Legal Summary of ASML v. XTAL

XTAL backgrounds

The Stocks
The ASML “news” is just old news rehashed which is not relevant to today, happened years ago and is not impactful to ASML’s financial model. ASML took the correct course of action and was not wrong in any way. The information does not add to or detract from existing China related risks as we see it. In essence it is much ado about nothing, and as such should have no impact on the stocks other than “headline risk”.

The only take away is the ongoing risks that all technology firms face in protecting their technology and that those risks are higher today with higher software content and USB drives that can hold 100’s of gigabytes of data in something the size of a key. The technology industry is more competitive than ever and this competition is a proxy for competition for global political dominance.


Real Time Object Recognition for Automotive Applications

Real Time Object Recognition for Automotive Applications
by Tom Simon on 04-12-2019 at 7:00 am

The basic principles used for neural networks have been understood for decades, what have changed to make them so successful in recent years are increased processing power, storage and training data. Layered on top of this is continued improvement in algorithms, often enabled by dramatic hardware performance improvements. There was a time not all that long ago when classifying objects in a still picture was impressive – and this was often done with training and classification running on large servers. The growing demand for autonomous vehicles has raised the bar. What is needed is the ability to perform real-time detection and recognition of objects at high framerates within the power, size and reliability constraints of automotive systems.

Recently in San Jose the Autonomous Hardware Summit brought together innovators in this field to discuss the latest technology trends. Autonomous vehicles must be able to identify and classify multiple objects in each frame of high resolution images. Frame rates must be high enough to keep up with high vehicle speeds. One new neural network type is extremely good at this. It is known as You Only Look Once (YOLOv3) and avoids the problem older approaches have with needing to break each frame up into separate identification tasks based on the detection of potential objects in various parts of the image. In previous techniques, each of these candidates needed to be run through a separate recognition step to determine what if anything is in the region.

YOLO works on the whole image at once, locating and recognizing objects much faster. Of course, its processing power and memory demands make this approach more difficult to implement. At the summit Dr. Cheng C. Wang, Co-Founder & Senior VP Engineering/Software at Flex Logix Technologies outlined their approach to tackling this challenge. With a resolution of 1920 x 1080 YOLOv3 can require over 100 GOPS per frame. Flex Logix offers modular neural inference building blocks called nnMAX 1K Tiles. They can be added to their EFLX embeddable FPGA to create specialized silicon hardware configurations to maximize performance.

YOLOv3 is made up of over 100 layers, often requiring over 200 billion MAC operations. The Flex Logix nnMAX 1K tile contains 1024 MACs in clusters of 64 with weights stored locally in L0 SRAM. It supports a wide range of data types with optimizations such as Winograd Acceleration when appropriate. nnMAX tiles can be reconfigured rapidly at runtime between layers to optimize data movement. For instance, layer 0 and layer 1 operations can be combined so the intermediate data stays in SRAM. In fact, their nnMAX compiler will automatically combine layers in this manner if there are enough resources.

Flex Logix’s ArrayLinx is used to perform the interconnect remapping of thousands of wires btween nnMAX tiles. nnMAX can also connect to 1,2 or 4MB of SRAM depending on how it is configured. Optimizing SRAM configurations can allow for nnMAX arrays that perform up to 100 TOPs

One of Dr. Wang’s main points is that when running YOLOv3 on nnMAX tiles, increasing resources effectively scales performance. nnMAX can be configured in a wide variety of array sizes. His performance example is a 2MP per frame video. With nnMAX 4K and 8MB SRAM it can handle 10 fps. Going to nnMAX 8K with 32MB SRAM yields 24 fps. And an impressive 48 fps can be reached with nnMAX 16K and 64MB SRAM.

Flex Logix also supplies a complete software development environment to accompany the embedded FPGA and nnMAX tiles. The nnMAX compiler will map neural networks to Tensorflow or ONNX. Given any neural network, their software can output performance metrics based on nnMAX provisioning, the amount of SRAM, and DRAM bandwidth. This makes it easy to understand MAC utilization and the overall efficiency of the proposed architecture.

This new development from Flex Logix looks very exciting for the highly demanding automotive market. YOLO has been a game changer and is rapidly becoming a favorite for real-time image processing. YOLOv3 running on silicon designed with Flex Logix IP should provide an effective solution for meeting the demanding requirement of autonomous vehicle hardware. Their presentation from the Autonomous Vehicle Hardware Summit can be found on the Flex Logix website.


DAC56 Keynotes and SKYtalks – The Big Picture

DAC56 Keynotes and SKYtalks – The Big Picture
by Daniel Payne on 04-11-2019 at 12:00 pm

Many of us have engineering degrees and are well paid to maintain a deep but narrow focus into a specific domain, but what about the big picture, like industry trends and emerging challenges? Well, DAC56 has just the thing to deliver us a front row seat to the big picture, and it’s contained in both the Keynotes and SKYtalks.

Hors D’Oeuvres from Chaos

In the 1970’s while living at home, listening to the radio, I stumbled upon this new type of music made with a synthesizer, it was played by Walter Carlos and called Switched-On Bach, and I was hooked on both synthesizers and classical music. Likewise, Thomas Dolby has a colorful musician career that also started out with synthesizers and now he has a popular YouTube channel. What if music were to embrace principles from AI and deep learning? Experience his keynote on Tuesday, June 4th at 9:20AM in the Keynote booth 1145.

From student project to tackling the major challenges in realizing safe & sustainable electric vehicles

As an avid cyclist I also have a bond for motorcycle riders, because we both share a common two-wheel ethos and experience the gradual electrification of our transportation. Bas Verkaiak and a group from the Eindhoven University of Technology actually built an electric motorcycle, then rode it around the world in just 80 days. After completing such an epic feat, the group spun off and created SPIKE Technologies. Find out how this energetic group created their own electric motorcycle and what they learned along the way. Wednesday, June 5th at 9:20AM at the Keynote booth 1145.

Reverse Engineering Visual Intelligence

I love watching SciFi movies where the plot involves getting into the human mind and creating an alternate reality, think The Matrix. James DiCarlo, MD, PhD from MIT is studying Human Intelligence (HI) and Artificial Intelligence (AI), and has an approach using neural network models to form the next generation of computing. How we humans use vision will be the focus of this Keynote held on Thursday, 9:20AM at the Keynote booth.

Cutting Edge AI: Fundamentals of Lifelong Learning and Generalization

If you’ve been reading SemiWiki over the past 12 months, then you recall that most of the recent VC money is pouring into AI startups that are doing new chips and software to tackle AI challenges. Hava Siegelmann from DARPA is presenting a Sky Talk on Monday at 1PM in the DAC Pavilion, booth 871. Find out what she’s learned in AI by studying nature, like Super Turing computation, stochastic and asynchronous communication, adaptivity and interactive computation.

The Memory Futures

I started out my IC design career doing DRAM chips, so I love all things memory related. The two biggies in memory today are NAND Flash and DRAM, so find out from Micron expert Gurtej Sandhu, Ph.D. how memory companies are squeezing even greater densities with each new process node. How in the world do they keep developing to 5nm and smaller. His Sky Talk is on Tuesday, June 4th at 1PM in the DAC Pavilion.

Incorporation of Security into Chip Design

I first met Serge Leef while at Mentor in Wilsonville, Oregon and have kept in touch with him over the years, and since August 2018 he’s been with DARPA as a program manager in the Microsystems Technology Office (MTO). Literally every week I read headlines about cybersecurity threats and data breaches, so his talk will delve into the area of automating security into the actual chip design process. This Sky Talk is on Tuesday, June 4th at 2:15PM in the DAC Pavilion.

Summary

Plan on attending DAC this year from June 2-6 in sunny Las Vegas, get the big picture and inspiration from the Keynotes and Sky Talks, and meet these interesting speakers and some of us SemiWiki folks as we walk around the exhibit area, learning more about our semiconductor industry up close. There should be 6,000 attendees and over 170 companies in the exhibit area, along with the strong technical program.


A Collaborative Driven Solution

A Collaborative Driven Solution
by Alex Tan on 04-11-2019 at 7:00 am

Last week TSMC announced the availability of its complete 5nm design infrastructure that enables SoC designers to implement advanced mobile and high-performance computing applications for the emerging 5G and AI driven markets. This fifth generation 3D FinFET design infrastructure includes technology files, PDKs (Process Design Kits), tools, flows and IPs –all of which have been developed and validated by multiples silicon test vehicles through earlier collaboration with leading EDA and IP vendors.

Normally each process node shift is expected to deliver significant improvements in one or more of PPAC (Performance, Power, Area or Cost) design metrics. For example, the innovative scaling features in full-fledged EUV 5nm node provides a 1.8X logic density and 15% speed gain based on the ARM® Cortex®-A72 core testcase. While the process refresh update seems so regular (about every 18 to 24 months), the intricacies imposed by the new process technology keep rising and its direct impacts on the EDA space have been constantly endured foremost by both the physical verification and circuit simulation tools.

Mentor, a Siemens Business has been the industry leader in providing physical verification solution through its Calibre physical verification (PV) platform, which includes Calibre nmDRCand Calibre nmLVS. As a design signoff tool, there are three most sought criteria in PV: accuracy, reliability and performance –all of which are attainable through tight collaboration with both the targeted foundry and alpha customers. Foundry rigorous trials such as TSMC applied double-blind QA procedure has helped to facilitate tool and design flow readiness.

Design Density, Performance and Rule Complexity
As physical verification has evolved around design rules development and its verification, the rule complexity is directly proportional to the device and interconnect technology of the underlying process. Despite the slow down of Moore’s law, design density is still increasing driven by the relentless compute power demand to process data on the cloud and edge. Historically, transistor count has been used as the classic metric to measure the forward trend. Recent multi-core design and increased IPs inclusion trends have driven the transistor counts, pushing the number of design rules and the associated operations needed to implement those rules upward. The non-linear growth of DRC rules prompts challenges to a timely adoption of new process shift by the design teams.

Deep Collaboration and EDA Tool Certifications
A key success criterion for tool certification is to incorporate new functionality based on the foundry requirements in the early stages of process node development. During this development stage, foundry needs to step through the learning curve and bootstrap their prior known node experiences to enhance the overall ramp time. Over the years, Mentor has participated in repeat successful collaboration including three main physical verification areas (DRC, LVS, xACT/xRC) with multiple foundries.

To have foundries utilize Calibre tools internally as they develop a new process provides the most valuable return as it allows earlier identification and simultaneous fine-tuning of foundry design requirements and hardening the verification tools with any needed rules. For example, Mentor Calibre has been part of the TSMC EDA tool certification.

“TSMC’s 5-nanometer technology offers our customers the industry’s most advanced logic process to address the exponentially growing demand for computing power driven by AI and 5G,”said Cliff Hou, Vice President of Research & Development/Technology Development at TSMC. “5-nanometer technology requires deeper design-technology co-optimization. Therefore, we collaborate seamlessly with our ecosystem partners to ensure we deliver silicon-validated IP blocks and EDA tools ready for customer use. As always, we are committed to helping customers achieve first-time silicon success and faster time-to-market.”

In very advanced node such as TSMC 5nm, a deeper design-technology co-optimization is also necessary. Such earlier and heuristic collaborative efforts among foundry, EDA provider and the alpha customer will culminate in a number of pilot tapeouts and the start of silicon risk production cycle. For example, the flurry of pilot 5nm tapeouts occurring in the last few quarters will be followed by silicon bring-up in the second half of 2019.

Tool Capacity, Memory and Runtime
Tool scalability involves several variables such as code vectorization and optimal memory footprint. Memory usage is a key metric that also ties to tool performance. The diagram in figure 2 shows the normalized Calibre engine performance trend as a result of incorporating continuous speed improvements over several process nodes. In two recent Calibre nmDRC versions across six different 7 nm designs, Mentor reported a consistent 40-50% decrease in memory usage as the underlying data structures and memory management techniques were improved.

Calibre facilitates pre- and post- physical validations by providing ease-of-use interfaces for navigating and visualizing complex verification errors. Without proper integration and planning, completing a verification task may incur significant post-run analysis time. This can be minimized by enabling the many available Calibre features to configure, launch, review, and debug within the designer’s chosen flow as it is built to accommodate many third party and design team internal flows. For example, Calibre has uniquely used special debug layers for double-patterning debugging, and automated waiver processing for masking out IP errors during chip integration debugging.


The immense challenges of a process node shift have strained silicon ecosystem stakeholders which include foundries, designers and EDA companies. Aside from having ample solution expertise and commitment, EDA company such as Mentor has resorted in deep collaboration and partnership with foundries and designers to perform early process exploration and enabling successful deployment of the needed toolset including Calibre physical verification tools.

Check HERE for more discussion on Mentor Calibre physical verification tool for advanced process node.


Functional Verification using Formal on Million Gate Designs

Functional Verification using Formal on Million Gate Designs
by Daniel Payne on 04-10-2019 at 12:00 pm

Verification engineers are the unsung heroes making sure that our smart phone chips, smart watches and even smart cars function logically, without bugs or unintended behavior. Hidden bugs are important to uncover, but what approach is best suited for this challenge?

With the Universal Verification Methodology (UVM) there’s the constrained-random approach that can find bugs that designers or verification engineers never thought of. The only downside of using constrained-random is the limitation to smaller DUTs, not covering all state spaces, missing corner-case bugs and not finding all Trojan paths.

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Lip-Bu Keynote at CDNLive 2019

Lip-Bu Keynote at CDNLive 2019
by Bernard Murphy on 04-10-2019 at 7:00 am

Cadence CEO Lip-Bu Tan is always an interesting guy to listen to for his broader technology industry overview and his insight into emerging tech through his Walden International investments. Though we’re usually heads-down in challenging technical problems, it’s good to look up from time to time to check whether what we are working on is hot or not – not always a secure bet in the rapidly-changing markets of today.

Lip-Bu gave the opening keynote at CDNLive Silicon Valley this year, starting with a theme of the data-driven economy, which is driven by 5G, machine-learning (ML), the cloud and Industry 4.0. His views here were pretty much in sync with what you’ll hear from the infrastructure equipment guys and many others, that demand is all about data creation, processing, transmission and storage.

He echoed a number of points I have written about before, which is at least validation for me that I’m not making this stuff up. First, the McKinsey analysis of the impact of AI on semiconductors. Better hope that AI isn’t a passing fad because they project the CAGR for AI-based silicon will be 5X of that for non-AI silicon up through 2025, though Lip-Bu dialed this down to 3X. He also supported the view that more systems companies are building silicon, the hyperscalars certainly, but also infrastructure equipment makers coming back to silicon design, new silicon startups and more industries moving to (more) electronification (is that a word?).

Where does he put his money? The Walden portfolio includes investments from the cloud to the edge to devices. In the cloud, focus is on scale-out, security and micro-verticals for AI healthcare and robotics, automotive, smart devices and vision.

What I found most interesting is how Lip-Bu and his team are positioning Cadence to meet these needs. This they call SDE 2.0 for intelligent system design. In these areas, Lip-Bu always stresses humility; they’re not trying to become something radically different. They’re instead building on their core competency in design excellence through computational software (EDA+IP) while extending this into adjacent areas through system innovation and pervasive intelligence. In system innovation, they see opportunities in system analysis, embedded software and security. In pervasive intelligence, they see opportunities in their Tensilica platform and algorithmic know-how in verticals. All innovation will continue to be heavily supported by a culture of organic innovation – end-to-end tool rewrites, massive parallelism, machine learning and cloud enablement. Importantly for Cadence and for EDA in general, Lip-Bu sees the potential for this expansion to break through the $10B ceiling to reach $30B.

He also talked about the Cadence cloud strategy. I know that Dan has already written about this, so I won’t spend much time on this topic. What did strike me was their CloudBurst introduction, a hybrid cloud, making it easier for teams to burst excess workload onto a cloud (AWS or Azure) while still taking advantage of their in-house compute assets. Makes a lot of sense to me, at minimum as a half-step to broader cloud-based deployment.

Particularly interesting to me is the Cadence partnership with Green Hills Software. “Partnership” understates the relationship as Cadence has taken a 16% ownership stake in the company and Lip-Bu sits on the board. This might be viewed as a counter to the Synopsys direction in software, though I see it as more like the Mentor direction, but stronger. Green Hills has strong safety and security software IP, such as their RTOS, and is well-established with automotive, aerospace and defense customers. The partnership offers an opportunity to bridge safety and security assurance across the hardware/software divide.

Interesting directions and interesting insights. Cadence clearly understand directions and seems to be making some aggressive moves to follow these trends.


IC Integrity Thesis

IC Integrity Thesis
by Jim Hogan on 04-09-2019 at 12:00 pm

Most of my investments are associated with large changes in the semiconductor industry. These changes create opportunities for new and disruptive technologies. I also look to find solutions that provide a compelling reason to adopt a new technology or approach. When talking about a new approach, it often takes longer to overcome the status quo.
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