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In Their Own Words: TSMC and Open Innovation Platform

In Their Own Words: TSMC and Open Innovation Platform
by Daniel Nenni on 06-01-2019 at 8:00 am
Categories: Foundries, TSMC

TSMC, the largest and most influential pure-play foundry, has many fascinating stories to tell. In this section, TSMC covers some of their basic history, and explains how creating an ecosystem of partners has been key to their success, and to the growth of the semiconductor industry.

The history of TSMC and its Open Innovation Platform (OIP)® is, like almost everything in semiconductors, driven by the economics of semiconductor manufacturing. Of course, ICs started 50 years ago at Fairchild (very close to where Google is headquartered today, these things go in circles). The planarization approach, whereby a wafer (just 1” originally) went through each process step as a whole, led to mass production. Other companies such as Intel, National, Texas Instruments and AMD soon followed and started the era of the Integrated Device Manufacturer (although we didn’t call them that back then, we just called them semiconductor companies).

The next step was the invention of ASICs with LSI Logic and VLSI Technology as the pioneers. This was the first step of separating design from manufacturing. Although the physical design was still done by the semiconductor company, the concept was executed by the system company. Perhaps the most important aspect of this change was not that part of the design was done at the system company, but rather the idea for the design and the responsibility for using it to build a successful business rested with the system company, whereas IDMs still had the “if we build it they will come” approach, with a catalog of standard parts.

In 1987, TSMC was founded and the separation between manufacture and design was complete. One missing piece of the puzzle was good physical design tools and Cadence was created in 1988 from the merger of SDA and ECAD (and soon after, Tangent). Cadence was the only supplier of design tools for physical place and route at the time. It was now possible for a system company to buy design tools, design their own chip and have TSMC manufacture it. The system company was completely responsible for the concept, the design, and selling the end-product (either the chip itself or a system containing it). TSMC was completely responsible for the manufacturing (usually including test, packaging and logistics too).

At the time, the interface between the foundry and the design group was fairly simple. The foundry would produce design rules and SPICE parameters for the designers; the design would be given back to the foundry as a GDSII file and a test program. Basic standard cells were required, and these were available on the open market from companies like Artisan, or some groups would design their own. Eventually TSMC would supply standard cells, either designed in-house or from Artisan or other library vendors (bearing an underlining royalty model transparent to end users). However, as manufacturing complexity grew, the gap between manufacturing and design grew too. This caused a big problem for TSMC: there was a lag from when TSMC wanted to get designs into high volume manufacturing and when the design groups were ready to tape out. Since a huge part of the cost of a fab is depreciation on the building and the equipment, which is largely fixed, this was a problem that needed to be addressed.

At 65 nm TSMC started the Open Innovation Platform (OIP) program. It began at a relatively small scale but from 65 nm to 40 nm to 28 nm the amount of manpower involved went up by a factor of 7. By 16 nm FinFET, half of the design effort is IP qualification and physical design because IP is used so extensively in modern SoCs, OIP actively collaborated with EDA and IP vendors early in the life-cycle of each

process to ensure that design flows and critical IP were ready early. In this way, designs would tape-out just in time as the fab was starting to ramp, so that the demand for wafers was well-matched with the supply.

In some ways the industry has gone a full circle, with the foundry and the design ecosystem together operating as a virtual IDM. The existence of TSMC’s OIP program further sped up disaggregation of the semiconductor supply chain. Partly, this was enabled by the existence of a healthy EDA industry and an increasingly healthy IP industry. As chip designs had grown more complex and entered the SoC era, the amount of IP on each chip was beyond the capability or the desire of each design group to create. But, especially in a new process, EDA and IP qualification was a problem.

On the EDA side, each new process came with some new discontinuous requirements that required more than just expanding the capacity and speed of the tools to keep up with increasing design size. Strained silicon, high-K metal gate, double patterning and FinFETs each require new support in the tools and designs to drive the development and test of the innovative technology.

On the IP side, design groups increasingly wanted to focus all their efforts on parts of their chip that differentiated them from their competition, and not on re-designing standard interfaces. But that meant that IP companies needed to create the standard interfaces and have them validated in silicon much earlier than before.

The result of OIP has been to create an ecosystem of EDA and IP companies, along with TSMC’s manufacturing, to speed up innovation everywhere. Because EDA and IP groups need to start work before everything about the process is ready and stable, the OIP ecosystem requires a high level of cooperation and trust.

When TSMC was founded in 1987, it really created two industries. The first, obviously, is the foundry industry that TSMC pioneered before others entered. The second was the fabless semiconductor companies that do not need to invest in fabs. This has been so successful that two of the top 10 semiconductor companies, Qualcomm and Broadcom, are fabless and all the top FPGA companies are fabless.

The foundry/fabless model largely replaced IDMs and ASIC. An ecosystem of co-operating specialist companies innovates fast. The old model of having process, design tools and IP all integrated under one roof has largely disappeared, along with the “not invented here” syndrome that slowed progress since ideas from outside the IDMs had a tough time penetrating. Even some of the earliest IDMs from the “Real men have fabs” era have gone “fab lite” and use foundries for some of their capacity, typically at the most advanced nodes.

Legendary TSMC Chairman Morris Chang’s “Grand Alliance” is a business model innovation of which OIP is an important part, gathering all the significant players together to support customers—not just EDA and IP, but also equipment and materials suppliers, especially for high-end lithography.

Digging down another level into OIP, there are several important components that allow TSMC to coordinate the design ecosystem for their customers.

  • EDA: the commercial design tool business flourished when designs got too large for hand-crafted approaches and most semiconductor companies realized they did not have the expertise or resources in-house to develop all their own tools. This was driven more strongly in the front-end with the invention of ASIC, especially gate-arrays; and then in the back end with the invention of
  • IP: this used to be a niche business with a mixed reputation, but now is very important with companies like ARM, Imagination, CEVA, Cadence, and Synopsys, all carrying portfolios of important IP such as microprocessors, DDRx, Ethernet, flash memory and so on. In fact, large SoCs now contain over 50% and sometimes as much as 80% TSMC has well over 5,500 qualified IP blocks for customers.
  • Services: design services and other value-chain services calibrated with TSMC process technology helps customers maximize efficiency and profit, getting designs into high volume production rapidly
  • Investment: TSMC and its customers invest over $12 billion a year. TSMC and its OIP partners alone invest over $1.5 billion. On advanced lithography, TSMC has further invested $1.3 billion in

Processes are continuing to get more advanced and complex, and the size of a fab that is economical also continues to increase. This means that collaboration needs to increase as the only way to both keep costs in check and ensure that all the pieces required for a successful design are ready just when they are needed.

TSMC has been building an increasingly rich ecosystem for over 25 years and feedback from partners is that they see benefits sooner and more consistently than when dealing with other foundries. Success comes from integrating usage, business models, technology and the OIP ecosystem so that everyone succeeds. There are a lot of moving parts that all have to be ready. It is not possible to design a modern SoC without design tools, more and more SoCs involve more and more 3rd party IP, and, at the heart of it all, the process and the manufacturing ramp with its associated yield learning all needs to be in place at TSMC.

The proof is in the numbers. Fabless growth in 2013 is forecasted to be 9%, over twice the increase in the overall industry at 4%. Fabless has doubled in size as a percentage of the semiconductor market from 8% to 16% during a period when the growth in the overall semiconductor market has been unimpressive. TSMC’s contribution to semiconductor revenue grew from 10% to 17% over the same period.

The OIP ecosystem has been a key pillar in enabling this sea change in the semiconductor industry.

TSMC 2019 Update

2019 TSMC Technology Symposium Review Part I

TSMC Technology Symposium Review Part II

 

Global Unichip Corporation

Another facet of TSMC is GUC, Global Unichip Corporation. It is a partially owned subsidiary and also an important partner, providing design services and allowing TSMC themselves to continue to be a pure-play foundry. GUC was founded in 1998 with 10 employees as what has come to be known as a “Design Service” company. It ramped fast and by 2000 it employed over 100 people.

The years between 2003 and 2010 were milestone years for GUC, representing a period of unprecedented growth. The era was marked by a strengthening of both business and technology relationships with the largest semiconductor foundry in the world, TSMC. That relationship set GUC on firm growth, bringing over the core of today’s management and the business strategy that guides the company today.

In 2003, TSMC assumed an ownership stake in GUC. But the foundry leader’s investment went far beyond financial investment. Part of its strategy to enhance the return on its investment was to move GUC to a global business strategy and put it on the road to being an advanced technology leader.

The technology model, and the business model that accompanied it, soon began to gain traction. Prior to 2003, much of GUC’s business came from the consumer electronics companies who tended to utilize more mature technologies and were primarily located in Taiwan. With the installation of new management, and new business and technology models, business emphasis began to migrate to the more technically sophisticated networking and communications sectors that required more advanced technologies. In 2004, 100% of GUC’s revenue was at  the 0.13 µm technology node; by 2005, 5% of revenue came from the new 90 nm node and a year later, an additional 3% of revenue came from the emerging 65 nm node.

The impact of this trend was soon seen in the company finances. Revenue jumped from $20 million in 2002 to $27 million in 2003, $32 million in 2004, and a whopping $48 million in 2005—more than doubling the revenue over a four year period.

The year 2006 marked another major milestone. In the third quarter of that year, GUC became a publicly traded company when it offered its shares on the Taiwan Stock Exchange.

The operations side instituted a major focus on advanced technology. In 2007, the company developed an advanced technology digital design flow, followed shortly thereafter by a low power design flow. As a result, the company saw a large increase in the size of their designs, many with gate counts jumping exponentially. In the face of an industry-wide recession in 2009, GUC showed its confidence in the future by investing heavily in internal IP development, in particular, IP targeting the networking market segment.

This era of prosperity was reflected by a broad set of indices. Annual revenue in 2006 more than doubled that of 2005 ($48 million) at $103 million, then more than doubled again in 2007 to $216 million. In 2008, revenue jumped to $295 million before falling during the recession of 2009 to $252 million. In 2008, GUC saw a jump in revenue from advanced technology to 21 % and to 34 % in 2009, with 1 % of that coming from leading edge 40 nm products. Like all technology companies, GUC experienced a financial decline in 2009, with revenues dropping to $252 million.

But the company would rebound quickly in 2010, posting revenues of $327 million with advanced technologies accounting for 42% of that total. The year also proved auspicious. Driven by the recession to examine its business model, GUC would begin making a series of strategic decisions that would allow it to capitalize on a new era of semiconductor device design.

The company’s growth as an innovative force in the semiconductor industry is also reflected in the number of new employees required to implement increasingly complex technologies. At the end of 2003, GUC employed 132 people, most of them in Taiwan. Three years later, that number had more than doubled to 287 and by the start of 2010, the company counted 484 employees, a number that has held relatively steady through 2013. Employee growth was fueled by expanded geographic growth. GUC opened its first international office when it established a subsidiary in North America (GUC N.A.) in February of 2004 and then opened its Japan office in June of 2005. Nearly three years later, in May of 2008, the company opened its third international office, GUC Europe, in Amsterdam, The Netherlands and one month later opened an office in Korea. GUC entered the fast-growing China market when it opened an office in one of that country’s technology hubs near Shanghai in 2009.

Success in the semiconductor industry going forward is going to be heavily weighted by the ability to leverage industry’s third-party infrastructure that has now matured. Foundries are at the leading edge of the infrastructure, providing the most advanced process technologies, as well as specialized technologies to all comers. IP and chip design implementation are also being outsourced, cost-effectively utilizing technology and financial resources.

It is in this new and exciting environment that GUC evolved the Flexible ASIC Model, which is designed to provide the most effective, efficient and flexible path to semiconductor innovation.

The Flexible ASIC Model is a response to both the business and technical challenges facing today’s semiconductor companies. This model allows companies to allocate their resources more efficiently. It brings together design expertise, systems knowledge and manufacturing resources to efficiently drive delivery of the final packaged IC. The model’s basic strategy is to spread design risks and to minimize IDM, fabless and OEM (Original Equipment Manufacturers) upfront semiconductor-related fiscal and human capital investments. The goal is to increase the efficiency of the entire value chain, from concept to delivery; to shorten all phases of the development cycle; and to ultimately increase device yield quality and reliability.

At the heart of the Flexible ASIC Model is integrated manufacturing. GUC has made a strategic choice to work exclusively with TSMC, the semiconductor industry’s leading foundry service company. It is this relationship that plays an integral role in the company’s ability to achieve early advanced technology access and match designs to manufacturing resources.

Spotlight: Dr. Morris Chang

Dell changed the way personal computers are manufactured and sold. Starbucks changed the amount we would pay for a cup of coffee. eBay took the yard sale out of our yards. TSMC took the semiconductor manufacturing costs off our balance sheets and out of our capital investments.

It’s hard to overstate the impact that Dr. Morris Chang, Founder, Chairman, and until-recently CEO of TSMC, has had on the industry. He has been influential as a leader in business model innovation, and has earned his company roughly 50% of the foundry market share.

Chang left his native China in 1949, moving to the US to attend Harvard University. He soon transferred to MIT as he followed his interest in technology. After earning his MS in 1953 from MIT’s mechanical engineering graduate school, Morris went directly into the semiconductor industry at the process level with Sylvania Semiconductor and was quickly moved to management.

Chang moved to Texas Instruments in 1958, where he stayed for 25 years, rising to VP of the worldwide semiconductor business (and also earned a PhD in electrical engineering from Stanford in 1964). At TI, he worked on a four transistor project in which the manufacturing was done by IBM, thus engaging in one of the early semiconductor-foundry relationships. Also at TI, Chang developed a new model of semiconductor pricing that sacrificed early profits to gain market share and to achieve manufacturing yields that would lead to higher long-term profits.

Chang left TI in 1983 and did a short stint at General Instrument Corporation. He then moved to Taiwan to head the Industrial Technology Research Institute (ITRI), which led to the founding of TSMC.

Chang noticed in the early 1980s, while at TI and GI, that top engineers were leaving and forming their own semiconductor companies. Unfortunately, the heavy capital requirement of semiconductor manufacturing was a gating factor. The cost back then was $5-10 million to start a semiconductor company without manufacturing and $50-100 million to start a semiconductor company with manufacturing. Some of these start-ups used excess capacity from IDMs but were subjected to uncertainties in foundry capacity and sometimes had to buy wafers from a competitor. Around this time, 1985, the first truly fabless startups, like Xilinx and Chips and Technologies, were launched and doing well.

It was in 1987, within this nascent fabless environment, that Chang started TSMC. Although TSMC started two process nodes behind where semiconductor manufacturers (IDMs) were at the time, they had the advantage of being a pure-play foundry, not a competitor. Their focus was on their customers.

Morris Chang made the first TSMC sales calls with a single brochure: TSMC Core Values: Integrity, Commitment, Innovation, Partnership. Four or five years later, TSMC was only behind by one process node and the orders started pouring in. In 10 years, TSMC caught up with IDMs (except for Intel) and the fabless semiconductor industry blossomed, enabling a whole new era of semiconductor design and manufacturing. In the last 20 years, and still today, even the remaining IDMs are being forced to go fabless or fab-lite at 28 nm and below due to high costs and daunting technical challenges.

Dr. Morris Chang in 2007.

Dr. Morris Chang turned 82 on July 10th, 2013. He is still running TSMC full time as the founding Chairman. He works from 8:30 am to 6:30 pm like most TSMC employees and says that a successful company life cycle is: rapid expansion, a period of consolidation, and maturity. The same could be said about Chang himself.

2019 Update: Dr. Morris Chang

In 2017 the TSMC Museum of Innovation opened Under Fab 12 in Hsinchu Taiwan. It not only commemorates the history of semiconductors and TSMC but also the life of Dr. Morris Chang. Morris Chang’s wife Sophie was actively involved in this project:

The TSMC Museum of Innovation encompasses three exhibition galleries: “A World of Innovation,” “Unleashing Innovation,” and “Dr. Morris Chang, TSMC Founder.” Through interactive technology, digital content, and historical documents we will learn about the pervasiveness of ICs in our daily lives and about their continued advancement. In addition, we will learn how ICs are making our lives more fulfilling and how they are driving technology beyond our imagination. We will also learn how TSMC contributes to global IC innovation and to Taiwan’s economy.

In 2018 Dr. Morris Chang retired from TSMC for the second and final time:

TSMC Dr. Morris Chang Announces Retirement in June 2018. Future Dual Leadership Will Be Mark Liu as Chairman And C.C. Wei as CEO.

Issued by: TSMC Issued on: 2017/10/02

Hsinchu, Taiwan, R.O.C. – Oct. 2, 2017 – TSMC Chairman Morris Chang today announces: “I will retire from the Company immediately after the Annual Shareholders Meeting in early June, 2018. I will not be a director in the next term of the board of directors. Nor will I participate in any TSMC management activities after the Annual Shareholders Meeting in early June, 2018. From early June, 2018 on, TSMC will be under the dual leadership of Dr. Mark Liu and Dr. C.C. Wei. Dr. Mark Liu will be the Chairman of the Board, and Dr. C.C. Wei will be the Chief Executive Officer. All present directors of the board have agreed to be nominated, and if elected, serve as directors of the board during the next term. They have also agreed to support the aforementioned dual leadership of the Company under Drs. Liu and Wei. Chairman Morris Chang further said, “The past 30-odd years, during which I founded and devoted myself to TSMC, have been an extraordinarily exciting and happy phase of my life. Now, I want to reserve my remaining years for myself and my family. Mark and CC have been Co-CEO’s of the Company since 2013 and have performed outstandingly. After my retirement, with the continued supervision and support of an essentially unchanged board, and under the dual leadership of Mark and CC, I am confident that TSMC will continue to perform exceptionally.”

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In Their Own Words: eSilicon Corporation

In Their Own Words: eSilicon Corporation
by Daniel Nenni on 06-01-2019 at 8:00 am
Categories: eSilicon, Semiconductor Services

eSilicon was one of the first companies to focus on making the benefits of the fabless semiconductor movement available to a broader range of customers and markets. The company is credited with the creation of the fabless ASIC model. In this section, eSilicon shares some of its history and provides its view of the ever-changing fabless business model.

eSilicon Corporation was founded in 2000 with Jack Harding as the founding CEO and Seth Neiman of Crosspoint Venture Partners as the first venture investor and outside board member. They both remain involved in the company today, with Harding continuing as CEO and Neiman now serving as Chairman of the Board.

Both Harding and Neiman brought important and complementary skills to eSilicon that helped the company maneuver through some very challenging times. Prior to eSilicon, Harding was President and CEO of Cadence Design Systems, at the time the largest EDA supplier in the industry. He assumed the leadership role at Cadence after its acquisition of Cooper and Chyan Technology (CCT), where Harding was CEO. Prior to CCT, Harding served as Executive Vice President of Zycad Corporation, a specialty EDA hardware supplier. He began his career at IBM.

Seth Neiman is Co-Managing Partner at Crosspoint Venture Partners, where he has been an active investor since 1994. Neiman’s investments include Brocade, Foundry, Juniper and Avanex among many others. Prior to joining Crosspoint, Neiman was an engineering and strategic product executive at a number of successful startups including Dahlgren Control Systems, Coactive Computing, and the TOPS division of Sun Microsystems. Neiman was the lead investor in eSilicon and incubated the company with Jack at the dawn of the Pleistocene epoch.

The Early Years

eSilicon’s original vision was to develop an online environment where members of the globally disaggregated fabless semiconductor supply chain could collaborate with end customers looking to re-aggregate their services. The idea was straight-forward—bring semiconductor suppliers and consumers together and use the global reach of the Internet to facilitate a marketplace where consumers could configure a supply chain online. The resultant offering would simplify access to complex technology and reduce the risk associated with complex design decisions. Many fabless enterprises had struggled with these issues, taking weeks to months to develop a complete plan for the implementation of a new custom chip. Chip die size and cost estimates were difficult to develop, technology choices were varied and somewhat confusing, and contractual commitments from supply chain members took many iterations and often required a team of lawyers to complete.

The original vision was simple, elegant and sorely needed. However, it proved to be anything but simple to implement. In the very early days of the company’s existence, two things happened that caused a shift in strategy. First, a close look at the technical solutions required to create a truly automated marketplace yielded significant challenges. Soon after the formation of the company, eSilicon hired a group of very talented individuals who did their original research and development work at Bell Labs. This team had broad knowledge of all aspects of semiconductor design. It was this team’s detailed analysis that lead to a better understanding of the challenges that were ahead.

Second, a worldwide collapse of the Internet economy occurred soon after the company was founded. The “bursting” of the Internet bubble created substantial chaos for many companies. For eSilicon, it meant that a reliable way to monetize its vision would be challenging, even if the company could solve the substantial technical issues it faced. As a result, most of the original vision was put on the shelf. The complete realization of the “e” in eSilicon would have to wait for another day. All was not lost in the transition, however. Business process automation and worldwide supply chain relationships did foster the development of a unique information backbone that the company leverages even today. More on that later.

The Fabless ASIC Model

Mounting technical challenges and an economic collapse of the target market have killed many companies. Things didn’t turn out that way at eSilicon. Thanks to a very strong early team, visionary leadership and a little luck, the company was able to redirect its efforts into a new, mainstream business model. It was clear from the beginning that re-aggregating the worldwide semiconductor supply chain was going to require a broad range of skills. Certainly, design skills would be needed. But back-end manufacturing knowledge was also going to be critical. Everything from package design, test program development, early prototype validation, volume manufacturing ramp, yield optimization, life testing, and failure analysis would be needed to deliver a complete solution. Relationships with all the supply chain members would be required and that took a special kind of person with a special kind of network.

eSilicon assembled all these skill sets. That deep domain expertise and broad supply chain network allowed the company to pioneer the fabless ASIC model. The concept was simple—provide the complete, design-to-manufacturing services provided by the current conventional ASIC suppliers, such as LSI Logic, but do it by leveraging a global and outsourced supply chain. Customers would no longer be limited to the fab that their ASIC supplier owned, or their cell libraries and design methodology.

Instead, a supply chain could be configured that optimally served the customer’s needs. And eSilicon’s design and manufacturing skills and supply chain network would deliver the final chip. The volume purchasing leverage that eSilicon would build, coupled with the significant learning eSilicon would achieve by addressing advanced design and manufacturing problems on a daily basis would create a best-in-class experience for eSilicon’s customers.

eSilicon’s positioning, DAC 2000

As the company launched in the fall of 2000, the fabless ASIC segment of the semiconductor market was born. Gartner/ Dataquest began coverage of this new and growing business segment. Many new fabless ASIC companies followed. Antara.net was eSilicon’s first customer. The company produced a custom chip that would generate real-world network traffic to allow stress-testing of e-business sites before they went live. Technology nodes were in the 180 nm to 130 nm range and between eSilicon’s launch in 2000 and 2004, 37 designs were taped out and over 14 million chips were shipped.

Fabless ASIC was an adequate description for the business model as everyone knew what an ASIC was, but the description fell short. A managed outsourced model could be applied to many chip projects, both standard and custom. As a result, eSilicon coined the term Vertical Service Provider (VSP), and that term was used during the company’s initial public exposure at the Design Automation Conference (DAC) in 2000.

The model worked. eSilicon achieved a fair amount of notoriety in the early days as the supplier of the system chip that powered the original iPod for Apple. The company also provided silicon for 2Wire, a company that delivered residential Internet gateways and associated services for providers such as AT&T. But it wasn’t only the delivery of “rock star” silicon that set the company apart; some of the original e-business vision of eSilicon did survive.

The company launched a work-in-process (WIP) management and logistics tracking system dubbed eSilicon Access® during its first few years. The company received a total of four patents for this technology between 2004 and 2010. eSilicon Access, for the first time, put the worldwide supply chain on the desktop of all eSilicon’s customers. Using this system, any customer could determine the status of its orders in the manufacturing process and receive alerts when the status changed. eSilicon uses this same technology to automate its internal business operations today.

Growing the Business

During the next phase of growth for the company, from 2005 to 2009, an additional 135 designs were taped out and an additional 30 million chips were shipped. Technology nodes now ranged mainly from 90 nm down to 40 nm. It was during this time that the company began expanding beyond US operations. Through the acquisition of Sycon Design, Inc., the company established a design center in Bucharest, Romania. A production operations center was also opened shortly thereafter in Shanghai, China.

Recognizing the growing popularity of outsourcing, eSilicon expanded the VSP model to include semiconductor manufacturing services (SMS). SMS allowed fabless chip and OEM companies to transition the management of existing chip production or the ramp-up and management of new chip production to eSilicon. The traditional design handoff of the ASIC model was now expanded to support manufacturing handoff. The benefits of SMS included a reduction in overhead for the customer as well as the ability to focus more resources on advanced product development. Extensions such as SMS caused the Vertical Service Provider model to expand, creating the Value Chain Producer (VCP) model. The Global Semiconductor Alliance (GSA) recognized the significance of this new model and elected Jack Harding to their Board to represent the VCP segment of the fabless industry.

In the years that followed, up to the present day, eSilicon has grown substantially. The number of tape-outs the company has achieved is now approaching 300 and the number of chips shipped is on its way to 200 million. The company has also expanded into the semiconductor IP space. While its worldwide relationships for third-party semiconductor IP are critical to eSilicon’s success, the company recognized that the ability to deliver specific, targeted forms of differentiating IP could significantly improve the customer experience.

eSilicon’s first logo. The squares symbolize the end product—the chip.

Since so many of today’s advanced chip designs contain substantial amounts of on-board memory, this is the area that was chosen for eSilicon’s initial IP focus. The company acquired Silicon Design Solutions, a custom memory IP provider with operations in Ho Chi Minh City and Da Nang, Vietnam. This acquisition added 150 engineers to focus on custom memory solutions for eSilicon’s customers.

As of June 30, 2013, eSilicon employs over 420 full-time people worldwide, of which over 350 are dedicated to engineering. Headquartered in San Jose, California, the company maintains operations in New Providence, New Jersey and Allentown, Pennsylvania; Shanghai, China; Seoul, South Korea; Bucharest, Romania; Singapore and Ho Chi Minh City and Da Nang, Vietnam. The company’s diverse global customer base consists of fabless semiconductor companies, integrated device manufacturers, original equipment manufacturers and wafer foundries. eSilicon sells through both an internal sales force and a network of representatives.

The Evolving Model

The eSilicon business model has evolved further. VSP and VCP are now SDMS (semiconductor design and manufacturing services). Arguably the longest, but perhaps the most intuitive name. Through the years, Silicon has allowed a broad range of companies to reap the benefits of the fabless semiconductor model, many of which couldn’t have done it on their own.

eSilicon’s current logo. The three “S” graphic symbolized the process and culture—speed, simplicity, and self-confidence.

This ability to bring a worldwide supply chain within reach to smaller companies gave eSilicon its start, but the model has worked well for eSilicon beyond these boundaries. Today, eSilicon serves customers that are much larger than eSilicon itself; customers that could “do what eSilicon does.” In the early days, the company discounted its chances of winning business at an enterprise big enough to maintain an “eSilicon inside.”

Time has proven this early thinking to be too limiting. Many of eSilicon’s customers today can clearly maintain an “eSilicon inside,” but they still rely on eSilicon to deliver their chips. Why? In two words, opportunity cost. It has been proven over time that for any enterprise the winning strategy is to focus on the organization’s core competence and invest in that. All other functions should be outsourced in the most reliable and cost-effective manner possible. Simply put, eSilicon’s core competency fits in the outsourcing sweet spot for many, many organizations. This trend has created new value in the fabless semiconductor sector and facilitated many new design starts.

What’s Next?

As the fabless model grows, there are new horizons emerging. During its early days, the vision of using the Internet to facilitate fabless technology access and reduce risk was largely put on the shelf. The reasons included the challenges of solving complex design and manufacturing problems and the lack of a clear delivery mechanism over the Web.

Today, these parameters are changing. The Internet is now an accepted delivery vehicle for a wide array of complex business-to-business solutions. eSilicon’s talented engineering team has also developed a substantial cloud-enabled environment that is used to automate its internal design and manufacturing operations every day. This team consists of many of the same people who highlighted the challenges of addressing these issues in the company’s early years. What a difference a decade can make.

What if that automated environment could be made available to end users in a simple, intuitive way? New work at eSilicon is taking the company in this direction. The recent announcement of an easy-to-use multi-project wafer quote system is an example. What once could take two weeks or more, consisting of many inquiries and legal agreement reviews, is now done in as little as five minutes with an extension to eSilicon Access. With availability on both the customer’s desktop and smartphone, this is clearly the beginning of a new path. eSilicon changed the landscape of fabless semiconductor in 2000 with the introduction of the fabless ASIC model. It’s time to do it again and bring back the “e” in eSilicon.

2019 Update: eSilicon Corporation

A lot has happened since 2013. Some “ups”, some “downs”, a lot of innovation and some surprises as well. The story told here applies to the industry in general, not just eSilicon.

We ended the original chapter on eSilicon talking about the potential to put the “e” back in eSilicon, leveraging an internet-based business model. That did indeed happen, but there’s so much more to the story.

In our previous closing remarks, we talked about an easy-to-use multi-project wafer (MPW) quoting system. By way of explanation, an MPW is essentially a cost-sharing strategy. Rather than one customer paying the full cost of a mask set and prototype manufacturing run, what if the mask could contain designs from many customers? Each customer would then get a pre-determined number of chips from the prototype run and the cost would be split among all participants. This strategy dramatically reduces the cost of building a prototype of a new silicon idea.

Our online MPW quoting system held the promise of collapsing a two-week fact-finding mission into a five-minute, fill-in-the-blanks quote generation experience. We did deliver that experience, and a lot more. It is interesting to note that, while the semiconductor industry essentially created the internet, the people who work in the semiconductor industry aren’t all that interested in using the internet for their business.

Our online MPW quoting system met with lackluster interest. Except for university researchers. It turns out this is where the customers were. Semiconductor research only becomes relevant when it’s proven in silicon. To achieve that goal, university researchers need to implement their design with a low-cost MPW run. University professors and their students are big fans of the internet, and so our online MPW quoting system was a hit with them. We began to build a worldwide user base for the tool. By January, 2017 we had approximately 1,500 users of our online MPW quoting tool in over 50 countries. We also added a lot more automation beyond quoting.

Prior to our online automation, it took six signatures to implement an MPW run. Uploading the final design could take three days and running final design rule checks could take even more time. When fully deployed, the system required zero signatures and final designs could be instantly uploaded and a design rule check would be automatically run with results sent back to the researcher in hours. We branded the online platform STAR, which stood for self-service, transparent, accurate and real-time. These are the words we always used to describe the system, so we “went with the flow.” We also took the opportunity to do a re-brand of the company. Essentially update our image to reflect the new, online nature of our business.

Those who work in marketing will appreciate this next point. We commissioned a new logo design. Why? Not because we didn’t like the old logo or the three “S” symbology for speed, simplicity, and self-confidence. We liked all that just fine. The problem was that the original logo was designed in a time when print media dominated the communication agenda. The graceful three “S” graphic was quite stunning in high-resolution print, but the detailed graphic elements were not well-suited to digital media. So, we created a new logo that maintained the message but was digital friendly.

We added much more automation technology to our STAR platform as well. The business, while small, was doubling year on year, with the promise to grow even faster, as online businesses tend to do. In January, 2017, we decided to shut down our online MPW business. The reasons for such a radical decision require turning the page to the next chapter of eSilicon and the ASIC business.

While our online business began around 2013, another trend began to take shape around that time. The trend of consolidation in the semiconductor industry. It began slowly at first but picked up steam along the way. LSI Logic was bought by Avago. Then Emulex and few more. And then Broadcom. What was once a focused, flexible top-end ASIC company was now part of a massive, worldwide standard product enterprise. During this same time, the mighty IBM Microelectronics, one of the major players in the top-end of the ASIC market along with LSI Logic, became part of GLOBALFOUNDRIES. There was more consolidation during this time across the world.

The result of this macro trend was the creation of a “hole” in the top end of the ASIC market. The companies that previously addressed this segment were now part of larger enterprises. ASIC was a part of the equation, but not the complete picture anymore. And these larger enterprises tended to compete with their ASIC customers due to their large standard product footprint.
Pure-play ASIC companies to address the needs of the top-end of the market were needed. And eSilicon had the right profile to address these needs. So, in January, 2017 eSilicon’s management team assembled for a strategic planning session. Many options to blend our various businesses were weighed, but one simple analysis, drawn on the whiteboard by our CFO, drove the point home.

Our online business was a good one, but it didn’t fit with the dynamics of our new opportunity to serve the top-end of the ASIC market—a substantial and lucrative opportunity. So, we shut down our online business. Between January and May of 2017, we did a record number of MPW tape-outs and then we moved on.

The next chapter in eSilicon’s history has been quite exciting. It began with one design win in the top-end of the ASIC market and then another and more after that. Today, eSilicon focuses most of its energy serving this market for the high-performance networking, computing, 5G infrastructure, and AI segments. We’ve developed a substantial array of differentiating semiconductor IP to address the unique needs of these markets. While this shift is significant for eSilicon, there is a bigger shift happening that is relevant for the entire ASIC market.

That shift has to do with what we’ll call ASIC success. When the first version of this book was published, ASIC success meant handing off a chip to the end customer that passed the manufacturing test program. Given the levels of complexity and integration delivered by those designs, this model worked. Today, it’s different. At the top end of the market, it’s often not a chip that’s delivered by the ASIC vendor. Instead, it’s a highly complex system-in-a-package that typically contains a massive, FinFET-class chip and multiple 3D memory stacks integrated on a silicon interposer.

Passing the manufacturing test program is just the beginning of bringing up a design like this in the target system. There are chip/package/system interactions, the need to debug potential interactions between semiconductor IP from multiple sources and hardware/software/firmware interactions. In this environment, delivering the required performance of the chip in the system context is the new measure of success. The task is daunting, but rewarding. Hitting the mark on a new router or 5G infrastructure component is quite lucrative for all involved. Getting there isn’t easy, but clearly worth it.

In this new paradigm of what ASIC success means, eSilicon finds itself playing the role of coordinator for multiple supply chain partners. The goal of delivering the required ASIC performance in the system context does take a lot of companies and a lot of coordination. It’s common in this new world to have ALL departments involved in a design kick-off meeting. System, chip, package, test, firmware and quality all have a role to play, and all have to work in a coordinated fashion from the very beginning to stay ahead of the curve. It’s also typical to assemble the bring-up team at the customer months before the chip is out of fab to plan all the hardware/software/firmware/package interactions required to achieve ASIC success.

The systems that these new ASICs power will, undoubtedly, change the world. eSilicon is proud to be part of the revolution.

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Ten Things to see @ 56th DAC!

Ten Things to see @ 56th DAC!
by Daniel Nenni on 06-01-2019 at 8:00 am
Categories: Events

New products always take precedence since EDA is a “mature” market. I have inside knowledge on this one so I can tell you it is not to be missed. Coincidently, but not really, a related white paper was just published so if you are not going to 56thDAC you can still get a virtual briefing. If you are going to DAC be sure and stop by the Fractal booth #561 to get a demo.

New Product: IP Delta QA

Associated white paper Why IP sign-off is not enough

EDA in the Cloud

It has finally happened, EDA is actually in the cloud and the results are incredible. SemiWiki is also in the cloud and as I sit at the Google Cloud Platform control panel I realize that all of the cloud talk in the past barely scratched the surface of what can be done. We are now seeing actual chip design case studies versus marketing hyperbole and DAC is the place for it, absolutely.

There is a dedicated Design-on-Cloud Theater in the Design Infrastructure Alley sponsored by my favorite cloud partner Google. Take a look at the three day schedule, there is plenty to see for all interested parties.

On Tuesday at 10am I will be moderating the Practical Advice From Those Who Have Already Adopted Cloud session. It’s organized by Cadence and will include Willy Chen from TSMC and cloud customers. I spent time with Willy and Vivian Chang at Fab 12 last week so we are ready to go.

The other cloud event I will attend is the “Calibre in the cloud: Case study with AMD, TSMC and Microsoft Azure” lunch. This is an off-site luncheon at the Westgate Hotel. Willy Chen of TSMC will be part of this one as well. A press release just went out in case you are interested:

Mentor and AMD verify massive Radeon Instinct Vega20 IC design on AMD EPYC in ~10 hours with ecosystem partners Microsoft Azure and TSMC.

IP Migration Tutorial

IP is critical for modern semiconductor design and analog IP has always been a challenge. MunEDA has been doing this for the better part of 20 years so they are the ones you want to listen to.

Wally Rhines on Fundamental Shifts in the Electronics Ecosystem

 “The last few years in the semiconductor industry have defied long-term industry trends.  Growth went from 3% average to double digits, M&A was near record lows, while IC venture capital hit a new, all-time high.  What drove this sudden upsurge?  And more importantly, will this dynamic trend continue?”

And don’t forget Wally will be signing complementary copies of his book “From Wild West to Modern Life” books at the Mentor booth #334 Monday at 5:00pm and Tuesday at 10:00am. There is a limited supply so get there early.

SemiWiki Fabless book giveaway in the Methodics booth #945

Copies of the 2019 updated version of “Fabless: The Transformation of the Semiconductor Industry” will be available compliments of Methodics. In addition to signing books I will be presenting my version of Semiconductors: Past, Present, and Future! In the Methodics theater. Stop by, say hi, and check the full theater schedule.

TSMC 2019 Open Innovation Platform® Theater (Booth #326) schedule is HERE.

Being the number one foundry does have its advantages and a massive ecosystem is one of them. It really is interesting to see what the fabless ecosystem is up to so you might want to take a look. Presentations start at 10:15 and end at 5:30pm with raffles in between. The presentations are 15 minutes, which is nice, and the presenters generally stay afterwards to answer questions so it is a great place to network.

Discover the Benefits of S2C’s FPGA Prototyping Solutions booth #952

In the last 15 years S2C Inc. has shipped more than 2,000 systems to over 400 customers including the top semiconductor companies around the world. Stop by and meet the S2C team and see the new AI on the Edge FPGA prototyping demo. See Compiled ONNX models in an FPGA prototype with an ARM Cortex A53 and Mali-GPU on a Xilinx Zynq™ Development Kit using an FPGA implementation of NVIDIA® Deep Learning Accelerator (NVDLA acceleration). You can also learn about Ultra-deep Trace Debugging, High-throughput Transaction-level Verification, and Multi-FPGA Design Partitioning.

If you see me walking around with a beautiful woman that is my wife of 35 years. This is her second Las Vegas DAC, the first being in 1985.  DAC has matured quite a bit since then but so have we so it will be a memorable experience just the same, absolutely.

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Will a Lack of Ethics Doom Artificial Intelligence

Will a Lack of Ethics Doom Artificial Intelligence
by Matthew Rosenquist on 05-31-2019 at 5:00 am
Categories: AI
2 Comments

If there was ever a time that ethics should be formally applied to technology, it is with the emergence of Artificial Intelligence. Yet most of the big AI companies struggle with what should seem a simple task: defining ethics for the use of their products. Without the underpinnings of a moral backbone, powerful tools often become a caustic capability for abuse. AI technology leaders must establish the guard-rails before chaos ensues.

As the great strategist Sun Tzu professed “Plan for what is difficult while it is easy, do what is great while it is small”. It is a tough challenge to find the right ethical balance when it comes to the complexity of Artificial Intelligence. Even more difficult is establishing a reasonable governance and sticking with it. However, as AI gains in power with vast amounts of data, it will impact almost every aspect of our lives, from healthcare, finance, employment, and politics. The benefits will solidify a deep entrenchment of AI systems in our digital ecosystem. Establishing parameters now is challenging, but it will be far more difficult to avoid catastrophe later if we populate the world with AI systems that can be misused.

AI for Everyone
AI/Ethics is crucial for the long-term security, privacy, and safety of those who are intertwined with the digital world. Organizations with forethought and true social responsibility will lead the way and separate themselves from companies who only use such initiatives as thin marketing ploys. But there are tradeoffs that these companies must weigh.

Autonomous systems are perfect for analyzing information from massive amounts of data that groups, classifies, builds profiles, and makes decisions with high degrees of accuracy, consistency, and scalability. Such abilities can be highly prized and profitable but is alarming from a privacy, security, and safety perspective. Should AI systems profile every person to determine the best way to influence them for any topic such as politics, religion, and purchasing preferences? Should they be empowered to make life-and-death decisions? What about AI systems which show preference or discriminate against social, racial, or economic groups? Even if it is accidental, occurring because a lack of design oversight, are these situations ethical?

Such systems have the power to change the world. And where there is power, there is money, greed, and competition. To purposely avoid certain use cases of AI systems comes with an opportunity cost of missed financial windfalls and prestige. Companies understand this trade-off and it is difficult to forego such lucrative prizes especially if their competitors may maneuver to seize them.

Early Moves
Currently, the efforts to establish ethics for the use of Artificial Intelligence is still in its infancy. There are academic, political, and business initiatives, but we are in the early stages of theory and practice. Whatever standards are created and implemented must be tested over time. The real validation will be around the perceived sacrifices of power and financial gain. Although consumers may feel all this is out of their control, in fact as a community, they have a tremendous amount of influence. Society can collectively support or shun organizations based upon their ethical choices, resulting in impacts to profits, influence, and power.

Acting Together and with Forethought
As consumers, we have a choice to support businesses that fall into 3 categories of maturity:

  • Irresponsible: Tech companies that have yet to publish ethical guidelines for their AI products and usages. With a lack of motivation, expertise, or simply only focus on self-interest, they have not taken steps to purposefully guide AI systems to remain benevolent. Instead, either by intent or ignorance, they will use AI for whatever pursuits benefit them without the burden of considering the greater consequences.
  • Striving:Organizations with a moral compass that have put forth the effort to establish AI Ethical policies but are struggling to implement the right balance. Time will tell what direction they go and their true level of commitment. Companies like Google, which recently disbanded their new AI ethics council, have worked hard to define a direction and governance but are finding difficulty in solidifying a structure that represents the optimal balance. Of note, Google does listen to its employees, partners, and the customers when it comes to inputs for decisions.
  • Leaders: Then there are those organizations, still few in number, who have fully embraced AI/Ethics with a greater level of social responsibility. They see both the opportunities and risks and are willing to forego some short term advantages for the betterment of all. They use AI with forethought and transparency to benefit their users, improve their services, and build trust by show their willingness to do what is right.As members of society, each of us should recognize and show economic support for the Artificial Intelligence ethics leaders and those who are continuing to effort attaining such a prestigious status. As citizens, our political support is crucial for proper regulations, enforcement, and legal interpretations that set a minimum standard for acceptable behavior and accountability. As consumers, voting with our purchasing preferences, we can make ethical AI leadership a competitive advantage.
    In the end, Artificial Intelligent systems will be analyzing our data and determining what opportunities and impacts will affect each of us. We have a responsibility to protect ourselves by supporting those organizations who are operating with purposeful ethical standards in alignment to what we deem acceptable.

    #artificial_intelligence #ethics #cybersecurity #AI

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Siemens Shows SOC Simulation Solution for Self-Driving Vehicles

Siemens Shows SOC Simulation Solution for Self-Driving Vehicles
by Tom Simon on 05-30-2019 at 11:00 am
Categories: Automotive, EDA, Siemens EDA
1 Comment

Ever since the early days of computing there has always been a large distinction between ‘regular’ computing and real time computing – where special care had to be made to deal with unordered and asynchronous events. Back then a system typically consisted of a handful of sensors and perhaps some electromechanical devices. The complexity back in those days pales in comparison to the challenges of building systems for automated driving in the present day. Each component of a self-driving car is part of an interdependent whole.

The goes literally from where the rubber meets the road to the high powered SOCs that make the whole system work. Due to the myriad interdependencies, it is not possible to simply build a prototype and test it to arrive at a correctly operating and optimized vehicle. It’s not enough that the AI hardware and software are working properly – sensors and actuators need to be accurate, and reliable. The physical properties of each need to be modeled so inputs can be properly interpreted, and controls are driven precisely. Piled on top of this complexity are the added requirements for safety. Systems in the vehicle need to be self-testing and failover has to occur seamlessly.

Siemens PAVE360 complete automotive design simulation solution

It is customary to make models of physical and electronic systems early in their design process to ensure that the designs are fully verified by the time they are manufactured. Scaling modeling and simulation up to the vehicle level is necessary for autonomous vehicles. The benefits of doing this extend beyond verification, allowing for iterative design improvement long before physical components are available. One such example is determining optimal sensor placement. Also, in the realm of AI, an accurate model of the vehicle can facilitate neural network training.

Closed loop simulation is so valuable in the automotive design space that Siemens has developed a simulation system that can model every element of a vehicle and mix real physical components with virtual ones to allow a wide range of system integration and simulation long before a real working vehicle is ever assembled. The system is called PAVE360.

One of the most interesting aspects to the PAVE360 is its ability to simulate custom SOCs using Mentor hardware emulation tools. In the maturing autonomous vehicle market, manufacturers are looking to improve performance by designing AI/ML SOCs tailored to their specific needs. This is a leading factor in creating product differentiation.

PAVE360 can model every aspect of a vehicle in operation. This not only includes simulating sensor input for real world operation, it also can cover 5G operation for V2V and V2I communications. This illustrates just how comprehensive the system is. Siemens believes that the availability of PAVE360 systems can help every member of the supply chain improve their products. It’s also not just for navigation. PAVE360 can be used for every system in a vehicle, including engine and drivetrain management, safety, infotainment, battery/fuel management, etc.

Siemens has developed a unique system for enabling early simulation of SOC designs in a comprehensive environment that covers every aspect of vehicle operation. Looking back at their acquisition of Mentor, there were many questions at the time about the value proposition. It seems now that building something like PAVE360 could only be done with their combined technology and resources. A PAVE360 installation is on display in the Center for Practical Autonomy Lab in Novi, Michigan. The details of this system are featured in the announcement by Siemens.

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Opening a new front in multi faceted trade war

Opening a new front in multi faceted trade war
by Robert Maire on 05-30-2019 at 5:00 am
Categories: Semiconductor Services
3 Comments

We had warned in our May 10th note about the rare earth element risk.  It is one of the few remaining leverage points that China has left that has a potentially strong impact on the US much similar to the US’s impact on Huawei and perhaps even worse. Cutting the US off from rare earth elements is clearly worse than cutting Huawei off from technology as lack of rare earth elements would cut across many sectors, not just tech and many companies not just one.
Yesterday President Xi visited a Rare Earth Element producer in China and clearly issued a lightly veiled threat relating to rare earth elements. Perhaps Xi read our May 10th note??

 

 

We would expect some sort of action on rare earth elements. It could be anything from a reduction in exports to the US, to an export tariff of rare earth elements (which US consumers will again pay for) or even an outright ban.  We have seen this before in 2010 involving rare earth elements then being lifted in 2015 after which everyone promptly forgot…..
 
Taiwan is an hour and a half away from trouble

Taiwan is roughly 1.5 hours away from China by ferry and even less by faster naval vessel’s. Many years ago when China was flying missiles over the rogue , runaway nation  and we wrote about the risk to the PC industry.
Today, the semiconductor industry centers around Taiwan and TSMC. We have been talking about this new risk for several years.
Could China, after being boxed in on trade by the US respond by sailing over to Taiwan and taking back what it claims is rightly theirs.
Sounds a lot like Russia “annexing” Crimea….no one…not even the US raised a finger to stop it other than some complaining.
Just like with Russia and Crimea, China can claim the common ancestry and language and former connectivity.
China has the excuse of saying that the US was threatening its future access to technology it deserves and thus could easily make excuses.  Its not like the US is doing much about claims n the South China sea nor much progress in Korea.
Its pretty clear that both sides have dug in and continue to escalate….how far will the escalation go?
$16B for farmers….$0 for Semiconductors…..
The US seems to buy farmers off by paying them not to grow crops. Today the administration announced a $16B program to help out farmers hurt by the tariff war (paid for by US tax payers…).
Obviously soybeans are more strategically important than semiconductor chips as there were no semiconductor executives present at a press announcement of subsidies to US chip makers hurt by the US cutting off Huawei….they just have to suck it up….and sell billions fewer chips.
The impact on US chip makers is not a retaliatory move by a foreign government it is a direct order from the US government not to sell product for the strategic benefit of the security of the entire nation….might be worth a few pennies of compensation.  It sounds like the US is going to lose a lot more than $16B in tech sales related to Huawei alone.

 

A Tariff on exported chips and equipment?…
Rather than forcing low end US consumers to pay more at Walmart for all the low cost Chinese goods that can’t be manufactured in the US for 25% more than current pricing perhaps it would make sense to have China pay the tariffs….like on stuff they really need.
They (Huawei and others) really need chips from US companies. Rather than cutting off the supply which hurts US chip makers why not just put an export tax to China on the components. In that way the US companies still get to sell product and the Chinese actually pay the tariffs, not just US consumers. Of course there will be trickle down and US consumers will eventually pay more but so will the rest of the world and Chinese consumers, not just US consumers.
While they are at it , why not put an export tax on US semiconductor equipment? China desperately needs it for made in China 2025 and they would likely have no choice but to pay the tariffs as Japanese, Korean and other equipment can’t make up.  It would make Chinese fabs more expensive and thus less competitive. This would help make up for China’s price advantage due to labor or fewer regulations.
It would likely slow China’s expansion and allow the US, Japan, Korea & Taiwan to remain more competitive.
Food for thought……
We have just seen the tip of the iceberg of impact…….
The Huawei fallout while press worthy is small as compared to the impact of an all out trade war we seem to be headed for.  Given the amount of technology goods and silicon that flows through China it could have a monsterous impact.
We have jumped from ZTE to Jinhua and now Huawei as we have graduated to larger targets.
Xi is threatening rare earth, and we are not far from 100% tariffs on all trade between the US and China.
The next step after tariffs is cutting off trade all together.  Given China’s authoritarian regime they can do what they want, create any impact on the population without worry of complaint. The US does not quite have that luxury.
China can devalue its currency, it can sell US debt (but that is self defeating).

 

Mutually Assured Destruction-On an economic basis rather than Nuclear basis?
The Soviet Union and the US have an uneasy detente due to the premise of MAD (mutually assured destruction) if they were ever to unleash a nuclear war….it is “unwinnable”.
One of the problems facing the trade issue is that over the years the two economies have become so intertwined that MAD has become a reality for the Chinese and US economies.
An uneasy detente is likely the best outcome available, yet both sides seem to think they can “win” a trade war.
While I think the US can get much better trade terms than it has had in the past with China, it cannot “win” as China will not give in.

 

Further Downside risk for the stocks
The downturn in the semiconductor industry, which was primarily driven by weak memory and smart phone sales that saw its nadir around the end of the year could be mild as compared to the China risk.

 

Right now the stock market continues to discount a positive resolution to the trade issue even in the midst of a worsening situation.
We think that is not enough of a discount based on the probability of outcomes given the current trajectory.
There is no “quick fix” on the horizon. Each day brings new escalation. Permanent damage has clearly already been done as the level of mistrust has risen to high levels.
China will push made in China much , much harder now as it will seek sources outside of the US. However, we don’t see manufacturing moving back to the US any time soon as there remain many low cost areas outside the US and China to buy from.
The full effect of all the tariffs has yet to be even calculated before it can be felt by US companies.
We are very hard pressed to see any way that the current chip down cycle is not worsened and lengthened by the trade conflict.  Its only a matter of how long and how deep.
We would point out that previous down cycle bottoms at the end of 2018 were under $30 for AMAT, $125 for LRCX, $82 for KLAC, $29 for MU. Intel has already returned to its low on its own. QCOM was trading at around $50.
This suggests significant potential further downside from an extended trade war most of which is certainly not reflected in the current stock prices.

 

We could continue to experience the “death by a thousand cuts” of ongoing negative trade news flow or a couple of larger events could trigger some sharper drop offs.
There are not a lot of places to hide in the stock market but technology and chips in general continue to take the brunt of the hit and lead the overall averages down.

 

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Synchronizing with Sunlin Chou

Synchronizing with Sunlin Chou
by Sunit Rikhi on 05-29-2019 at 1:38 pm
Categories: General
2 Comments

Sometimes we get to see, up close, leaders who make a truly enormous contribution to society. Dr. Sunlin Chou was one such leader and I was a fortunate fellow traveler. Sunlin led the exponential rise of transistors for 35 years, accelerating the waves of revolutionary digital technologies serving humanity.

Fifty years have passed since Sunlin entered the electronics industry in 1968. At that time, the industry was adding about 1 transistor every year to the service of every human on earth. By the end of Sunlin’s career in 2005, the industry was giving 7 billion transistors every year to each of us. Today, you and I are receiving well over 50 billion transistors each.

Do you know where all of yours are? I don’t either, but I know that my transistors live just about everywhere. They wiggle on and off at speeds unimaginable, to support my everyday needs.

Sunlin had the fortune of joining this transistor exponential in its infancy. The exponential is made up of waves of transistor manufacturing technologies, each bigger, better and steeper than the previous wave. Bigger, because each wave made exponentially more transistors than the previous wave. Better, because we made each transistor faster, less power hungry and half the size compared to its predecessor.  And steeper, because we ramped the production of transistors faster than we did in the previous wave. If a wave was not bigger, better, steeper and on time, there was a stiff economic penalty to be paid.

How do you ride such exponential waves consistently and elegantly over decades?

The answer is found in the architecture and disciplined use of an organizational machine Sunlin invented. The purpose of the machine was to synchronize the aspiration, the energies and the output of thousands of people riding the wave from across the globe and, over several years. The result was one spectacular exponential wave after another, of transistors penetrating our lives at ever increasing rates.

Sunlin’s synchronizing machine was as simple as it was impactful. At its very core was the concept of synchronizing (synch) points. These were well-defined and well-marked stakes in the ground which had to be reached predictably. Sunlin chose the manufacturing ramp of every wave as its master synch point and he mandated its placement on a 2-year cycle between waves (2-year rhythm maximizes the economic value of riding transistor waves).  All activity across Intel and the semiconductor ecosystem was pipelined to synchronize at that synch point.

A key architectural feature of Sunlin’s machine was the partitioning of the multi-year pipeline into Research, Development and Manufacturing (RDM) phases. The Research phase pruned technology options to carry forward into Development. The Development phase defined the new wave’s specifications and developed manufacturable ICs made up of transistors. And the Manufacturing phase ramped and maintained transistor production for the rest of the wave’s life. Each phase was well defined in terms of deliverables and hand-off points which served as intermediate synch points in the pipeline.

The structural integrity of the machine was in the disciplined use of built-in risk management features.

An example is Sunlin’s “COPY EXACTLY!” (“CE!”) doctrine.  In the manufacturing phase of the pipeline, multiple factories were needed to support the manufacturing volumes of transistors in a wave.  Sunlin programmed the machine to replicate technologies in each fab, one after the other, in order to ensure an un-interrupted flow of increasing output during, and after, the rise of the wave. So detailed were the copy spreadsheets, and so strong was the intent to copy exactly, that we never used the phrase “CE!” without the exclamation point.

As a second example, Sunlin designed large overlaps in the transitions from R to D and D to M in the RDM pipeline.  At these transitions, some wave riders stepped off and others stepped on to take the pipeline further. To ensure un-interrupted flow of work through these handoff points, Sunlin sent developers upstream to work with researchers to finish, and select, research streams for the development phase. He sent developers into the manufacturing phase by making them responsible for the first manufacturing ramp of the wave. And, he sent manufacturers to work alongside developers to learn, finish and copy the technology for subsequent factory ramps of the wave.

Yet another example is the way Sunlin limited variables in the development phase of the RDM pipeline. Manufacturing technology in a wave was expected to re-use more than 80% of the equipment of the prior wave. This change control limited exposure. He also imposed a restriction on the design of the chip leading the wave. It was expected to reuse the architecture from the prior generation with changes limited to those required for manufacturing. This controlled the risk that came from debugging simultaneous changes in design and manufacturing of the chip leading the wave, and came to be known as the Intel TICK-TOCK development model.

A networked hierarchy of synch meetings served as the synchronizing machine’s operating system.  These meetings included multiple cross-functional engineers who followed time tested dashboards to keep the wave’s relevant synch points front and center. Sunlin attended the highest synchronization meetings on a regular basis. One of them was a bi-annual meet where he interacted with hundreds of senior engineers representing hundreds of organizations and disciplines, gathered to take a holistic view of the wave.

When Sunlin passed on in December 2018, there was an outpouring of sentiment from those whose lives he had touched: “a brilliant mind”, “a well-balanced man”, “a gentle soul”, “a humble man”, “grounded in competence”, “integrity and class”, “an authentic, empathetic manager”, “a pioneer”, “a conceptual thinker”, “an inspiration to all”, and “a legend!”.

Sunlin was all that and more. Sunlin exemplified the power of architectural integrity in conceptual thinking. He showed us how it can serve as a solid foundation for journeys unimaginable.

 

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Selecting an ASIC Package

Selecting an ASIC Package
by Daniel Nenni on 05-29-2019 at 10:00 am
Categories: Delta, Semiconductor Services

Semiconductor chip package technologies have evolved throughout the years to the point where hundreds of package types are available today. 

Most applications will require the more general, single-element packaging for integrated circuits and the other components such as resistors, capacitators, antenna etc. However, as the semiconductor industry develops smaller and more powerful devices, a ‘system in package’ (SiP) type of solution is becoming the preferred choice, where all elements are placed into a single package or module.

While package types can be easily categorized into lead-frame, substrate or wafer-level packages, selecting a package that will suit all your requirements is a bit more complex and requires evaluating and balancing the application needs. To make the right choice, you must understand the effects of multiple parameters like thermal requirements, power, connectivity, environmental conditions, PCB assembly capability and of course, cost.

Here are some key requirements that you should evaluate to select a suitable packaging technology. For the full-length discussion of requirements, please see our white paper, The Ultimate Guide for Selecting an ASIC Package.

Application Category

Your target application is the primary driver dictating your package selection.  Is your application a low-cost consumer device or a high-cost industrial ASIC?  Will it be running in a hot environment? Will you develop a System on Chip or will your ASIC be a key component within the system?  Such questions will help you decide on the type of packaging – whether you can you use wafer-level or chip-size package, or can standard, more readily available BGA or QFN type packaging be more relevant.

Application performance requirements and the corresponding packaging options can be broadly categorized into three groups:

High-end application requirements are often related to high-speed, high-power chips that have a large number of connections (high pin-out). These devices will require advanced packaging requirements to match the needs of small pad pitch, high-speed signals and decoupling, that can be achieved with the FC-BGA (flip chip BGA), or newer packaging like embedded Wafer Level Ball Grid Array (eWLB).

The Mid-range group typically require packaging that can address thermal enhancements and employ cost-effective plastic packaging technologies – often in the BGA and QFN type approach. At the higher end of this group are chip level and wafer level packaging, suitable for system in package and/or multi-chip module packaging.

The Entry level group includes high-volume applications where cost is the main driver rather than performance. Devices for notebook and mobile applications, for example, will generally require small size wafer level and chip size packaging.

Number of Pins and I/Os

The number and location of input and output connections of any device are key factors to be considered when determining the package requirement. 

High pin count. If you’re looking at a very high pin-count, say 1000 pin package, then your best option may be a standard BGA package, which offers such I/O capability as overall package size can go up to 50-60 mm square.

Low pin count. For a low pint count, say 50 pins your choice would probably be a QFN or WLCSP package. However, a WLCSP will have limitations for heat dissipation within the package. In cases where there is heat generation (e.g., fast switching) or need for good signal grounding, then a QFN is the better package choice, due to the ‘built-in’ metal base pad.

Layout. Another parameter is the location of I/Os. If the I/Os are on the periphery around the die, then wire bonding is quick, easy and reliable provided there is enough surface area in the die and package pads for this. If the I/Os are spread across the surface of the chip in different areas, so that wire bonding out from the center of the chip is difficult, then flip chip packaging offers a direct attach approach onto the substrate of the package, which is usually a multi-layer PCB, and there would be no concerns about the die overlapping.

Heat Management

Thermal management is a key packaging factor for optimizing chip performance. A BGA package, for example, can often offer lower cost/improved thermal management solutions within the package because of its size, as it has a larger area available to dissipate the heat. The smaller real-estate chips can be more expensive in terms of the thermal management solution, requiring an external heatsink or other cooling options.

BGA packages have options with both thermal pads, such as conductive vias or inbuilt metal base plates that can enable adequate heat management. Some options of thermally enhanced BGA packages can have a metal cap built onto them that establishes a thermal conduction path between the IC device and the metal cap, which provides good heat dissipation.

QFN packages are designed such that they have a solid metal die pad as the base of the package, to which the die is bonded.  This enables very good heat dissipation from the silicon die through to the PCB.

Die attach materials. Bonding the chip to the substrate with a thermal conductive adhesive like Sliver filled Epoxy, rather than plain epoxy, will help remove the heat. In addition, newer technologies are available like Silver sinter technology – an interconnection method with high operating temperature, high thermal and electrical conductivity. These materials typically work well in QFN packages, but are not as effective in BGA packages, due to the package construction. 

Chip size and wafer-level packaging. Thermal management in these packages is primarily done on the back of the chip, or in chip size package, on the exposed top-side of the chip.

High-Speed Signals/RF

RF, wireless and high-speed digital designs have specific requirements that affect package selection. The signal speed and the frequencies can be significantly degraded by the parametric effects of the interconnections within the package.

Wire bond vs. flip chip. In RF devices, key design considerations involve inductance, capacitance and resistance, which are affected by the speed of the signals travelling in and out of the device. These issues also impact package selection, primarily between flip chip and wire bond interconnections. Flip chip will provide better RF Performance and enable reaching higher frequencies with lower inductance. Wire bonds, on the other hand, can add a randomly-variable inductance at each RF input or output at higher frequencies.

Package layout. At RF frequencies, signals travel along the surface rather than in the conductor. Hence, the way in which the package is assembled has an important effect on the device. For example, high-speed amplifier chips, RF transistors, and diodes often cannot be put into a “standard” plastic package, as the encapsulation materials affect the speed in which the chip operates. Consequently, such chips should go into a cavity QFN or BGA package.

High frequency signals (1 GHz and above) are likely to require the layout of the interconnections to have isolated signal paths, known as “ground signal ground” interconnect. Here the requirement of two ground connections for every signal i/o will impact the package size and layout.

Additionally, with high-speed ASICs, the signal levels and timing will be affected by the length of the conductor that they travel along. For example, if you are using a BGA package and you have a longer lead to one point and a shorter lead to the next, you will have timing differences on the signal. This must be overcome by putting more consideration into the initial design of the package substrate to accommodate the high-speed RF devices.

BGA substrate dielectric materials are also a key factor in RF chips. For example, a high-performance liquid polymer substrate, like Rogers laminate, is better suited than the standard FR4 PCB material for use as the substrate for BGA packages used for RF designs.

To read a full-length discussion of packaging requirements, please see our white paper, The Ultimate Guide for Selecting an ASIC Package

Author

Written by Sharon Akler.

Sharon has a background in technology and innovation and more than 20 years of experience in global companies and startups. At DELTA, Sharon is looking after sales in Europe covering ASIC supply chain services.  

About DELTA Microelectronics

With over 25 years of experience, DELTA Microelectronics is a European leader in ASIC services for the semiconductor industry. DELTA’s comprehensive services include ASIC design, layout, test development, wafer supply, production testing, package development and assembly, components supply, logistics and supply chain management. DELTA’s development and production facilities are based in Denmark and the UK, with service partners in Europe and Asia. For more information, visit asic.madebydelta.com

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Off with their heads!

Off with their heads!
by John East on 05-29-2019 at 8:00 am
Categories: John East
4 Comments

The “20 Questions with John East” series continues

I started out as a supervisor in the wafer sort and class area.  Today you’d call those probe and final test.  My first boss, a man named Les Faerber who I had never met,  met me in the lobby,  got a smock for me,  took me into the test area and introduced me to the ladies (All the operators were women in those days).  I had no idea what they were doing.  I didn’t even know that integrated circuits were made on wafers much less that those wafers needed to be “sorted”.   Then he said, “I’ve got a meeting.  Gotta go.”  And he left.  Terrifying!!! I was standing there trying to act as though I knew what was going on (I didn’t have a clue) when a really aggressive guy with a British accent came charging in. “Who’s the supervisor here?!!!”  “Why isn’t the waterfall running?!!!”  And, of course I thought to myself,  “Who is this guy? What’s a waterfall? What am I doing here?!!!”  It was John Carey.  He was the operations manager for all integrated circuits.  He wasn’t a patient man!  He scared me to death the first few times I dealt with him, but after a while I grew fond of him.   That was a shame, because very soon he would fall victim to “Off with their heads”.

That first afternoon a technician named Jack Drury was trying to teach me a little of what we were doing in wafer sort and class.  I’m sure it crossed his mind to wonder why an experienced technician like him was now working for an acne-faced college kid who had no clue about anything that mattered, but he tried to be helpful.  We stood in front of a prober and watched a wafer being tested (sorted).  I was impressed with the wafers.  “Wow  — you can make hundreds of these IC things at a time.  That’s cool!”  Each wafer had a few hundred “dice” on it.  Our job was to test them and identify the good ones. (At Fairchild, we called the individual ICs “dice”.  A single IC chip was a “die”. At most other companies they called them “chips”.)  The prober would stop on each die.  The tester would flash cool looking lights on and off for a few seconds, and then a small mechanical arm would put a little red dot on the die.  It seemed pretty efficient.  I asked Jack what the little red dot was for.  He said, “Oh.  That’s the inker.  We put a red ink dot on each die that doesn’t work right.”

Me:  “Oh.  I see.  That’s cool.  But – every one of the dice has a little red dot.”

Jack:   “So?”  

Me: “So all of these wafers that were already sorted have red dot’s on all their dice as well”.

Jack:  “What’s your point?

Me:  “Duh”

Jack:  “That’s a TTL lot.  The lot is zeroing out.  Big deal. That happens all the time to TTL.”

I think it was a 50 wafer lot.  Each wafer probably had 500 dice on it.  So  — the first 25,000 integrated circuits that I ever saw were all thrown out.  Nobody seemed to care. 

Maybe that’s what led up to “Off with their heads.”?

What was “Off with their heads?”  Well,  as I described in “Day One”,  many heads had already rolled after Hogan’s Heroes arrived but before I got there.  I heard some people saying good things about a man named Tom Bay.  I asked what job he was in.  “Oh.  He’s gone.  Fired a month ago.”  Tom was formerly the VP of marketing and, as far as I knew, the first victim of “Off with their heads!” Then, shortly after I got there, the VP of sales, Jerry Sanders, was fired.  Jerry, of course, then founded AMD and went on to a great career.  Then, John Carey (The guy who wanted the waterfall running) was fired.  He went on to be the CEO of IDT. Carey was replaced by a man named John Husher, but he was in and out of there so fast that I never got to meet him.  Bob Noyce,  Gordon Moore, and Andy Grove had left to form Intel.  Charlie Sporck gone too.  Charlie had left to be CEO of National Semiconductor.  Charlie took Floyd Kwamme,  Don Valentine,  and Pierre Lamond (all of eventual Venture Capital fame) with him.   Gene Kleiner was gone as well.  Gene was one of the traitorous eight but went on to be the head of what is probably the most famous Venture Capital firm of all – Kleiner Perkins.  In fact, every one of the Traitorous Eight founders left under various circumstances.   There were people disappearing left and right.  Sometimes you didn’t know if they were fired or if they just quit.  One morning you’d come in and they were gone. Why?  Where?  How?  Who knew?  Who was doing all this firing? Who knew?  It seemed as though a Vice President and Hogan’s Hero named Gene Blanchette was at the root of a lot of it, but before long, Blanchette himself disappeared.  I don’t remember how or why.  I probably never knew.  And then, in 1974 the coup de grace.  Hogan himself was gone. There was a popular song in 1967.  “White Rabbit” by The Jefferson Airplane.   Its lyrics put a new spin on Alice in Wonderland.    —  “And the red queen, ‘Off with their heads!’ ”  —  Wow.  That’s too close for comfort around here!!!

Have I rediscovered Alice in Wonderland? Did I go down the rabbit hole? And where did I put that hookah?

See the entire John East series HERE.

Pictured:  Jerry Sanders at the 1968 Fairchild Hawaii Sales conference.  Jerry had just been informed that Les Hogan had been hired to be his boss.  Jerry sent this picture to Les.  Three months later,  Les fired Jerry.

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Tortuga Crosses a Chasm

Tortuga Crosses a Chasm
by Bernard Murphy on 05-29-2019 at 7:00 am
Categories: IP, Security, Synopsys, Tortuga Logic

I assume you know the Geoffrey Moore “crossing the chasm” concept, jumping from early stage enthusiasts trying your product because they’ll try anything new, to expanding to a mainstream and intrinsically more critical audience – a much tougher proposition. I’d argue there may be more than one of these transitions in the life of a new venture, the first of which can be adoption by a mainstream partner as a part of one of their solutions.

Tortuga, a company that specializes in hardware threat detection and prevention in hardware plus software systems, already had important academic credibility, being birthed from hardware security groups in UCSD and UCSB. They have clients in the semiconductor, aerospace and defense industries, they’re on their second SBIR (small business innovation research) grant, they’ve raised seed funding and last year they received a contract from DARPA to develop new security solutions. All good stuff but feeling like it’s still mostly on the left side of the chasm. Where was mainstream semiconductor support going to come from?

In answer to that question, Tortuga announced just a few weeks ago a partnership with Synopsys. This offers a security verification solution for SoC designs built around the Synopsys DesignWare ARC processor IP and Tortuga’s Radix-S security verification software. Does that mean Synopsys needed extra help to ensure the security of their ARC solutions? Not at all. The unavoidable problem in developing security solutions around any IP is that they depend on the SoC developer not making mistakes in integration. One such example could be a mapping error for the the boundary between secure and insecure operation. Another could be allowing access to secure registers when a debug port has not been correctly disabled. Checking you didn’t make mistakes can become pretty complex, not always easily reducible to assertion VIPs. This is particularly challenging since misbehavior in these cases may be revealed only in interaction between hardware and software over many cycles.

The Tortuga approach to analyzing these integration problems is quite interesting, evolving (as I understand it) from a method called gate-level information flow tracking, coupled with a threat-model in the form of assertions against this analysis. This compiles into verification logic which runs together with your DUT and whatever verification workloads you normally run to check for potential threats as defined by these assertions. I’m told that as long as your verification regressions deliver good general coverage (they’d better at some point), you will have good confidence that these security threats will also have been covered.

Jonny Valamehr (COO at Tortuga) tells me that they and Synopsys have worked together to define a comprehensive set of threat assertions to cover many integration needs. Since an ARC core provides some level of configurability, Jonny said some aspects of the threat model may also need to be configured by the integrator to cover these cases. But I got the impression this isn’t very hard. From what I have seen, threat assertions don’t look so different from SVA assertions, though they express information about paths for assets to flow through the design, rather than logic behaviors. If you’re responsible for security, learning this assertion language doesn’t look like a big barrier.

Jonny tells me that today you buy your ARC core from Synopsys and you buy the Radix-S software from Tortuga. Synopsys and Tortuga have done the development to ensure the technical part of this flow works seamlessly. Making the business flow seamless is still in discussion. Nevertheless, good job Tortuga on taking this important step. You can learn more about Radix-S HERE.