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Selecting an ASIC package

Selecting an ASIC package
by Daniel Nenni on 05-29-2019 at 10:00 am

Semiconductor chip package technologies have evolved throughout the years to the point where hundreds of package types are available today. 

Most applications will require the more general, single-element packaging for integrated circuits and the other components such as resistors, capacitators, antenna etc. However, as the semiconductor industry develops smaller and more powerful devices, a ‘system in package’ (SiP) type of solution is becoming the preferred choice, where all elements are placed into a single package or module.

While package types can be easily categorized into lead-frame, substrate or wafer-level packages, selecting a package that will suit all your requirements is a bit more complex and requires evaluating and balancing the application needs. To make the right choice, you must understand the effects of multiple parameters like thermal requirements, power, connectivity, environmental conditions, PCB assembly capability and of course, cost.

Here are some key requirements that you should evaluate to select a suitable packaging technology. For the full-length discussion of requirements, please see our white paper, The Ultimate Guide for Selecting an ASIC Package.

Application Category

Your target application is the primary driver dictating your package selection.  Is your application a low-cost consumer device or a high-cost industrial ASIC?  Will it be running in a hot environment? Will you develop a System on Chip or will your ASIC be a key component within the system?  Such questions will help you decide on the type of packaging – whether you can you use wafer-level or chip-size package, or can standard, more readily available BGA or QFN type packaging be more relevant.

Application performance requirements and the corresponding packaging options can be broadly categorized into three groups:

High-end application requirements are often related to high-speed, high-power chips that have a large number of connections (high pin-out). These devices will require advanced packaging requirements to match the needs of small pad pitch, high-speed signals and decoupling, that can be achieved with the FC-BGA (flip chip BGA), or newer packaging like embedded Wafer Level Ball Grid Array (eWLB).

The Mid-range group typically require packaging that can address thermal enhancements and employ cost-effective plastic packaging technologies – often in the BGA and QFN type approach. At the higher end of this group are chip level and wafer level packaging, suitable for system in package and/or multi-chip module packaging.

The Entry level group includes high-volume applications where cost is the main driver rather than performance. Devices for notebook and mobile applications, for example, will generally require small size wafer level and chip size packaging.

Number of Pins and I/Os

The number and location of input and output connections of any device are key factors to be considered when determining the package requirement. 

High pin count. If you’re looking at a very high pin-count, say 1000 pin package, then your best option may be a standard BGA package, which offers such I/O capability as overall package size can go up to 50-60 mm square.

Low pin count. For a low pint count, say 50 pins your choice would probably be a QFN or WLCSP package. However, a WLCSP will have limitations for heat dissipation within the package. In cases where there is heat generation (e.g., fast switching) or need for good signal grounding, then a QFN is the better package choice, due to the ‘built-in’ metal base pad.

Layout. Another parameter is the location of I/Os. If the I/Os are on the periphery around the die, then wire bonding is quick, easy and reliable provided there is enough surface area in the die and package pads for this. If the I/Os are spread across the surface of the chip in different areas, so that wire bonding out from the center of the chip is difficult, then flip chip packaging offers a direct attach approach onto the substrate of the package, which is usually a multi-layer PCB, and there would be no concerns about the die overlapping.

Heat Management

Thermal management is a key packaging factor for optimizing chip performance. A BGA package, for example, can often offer lower cost/improved thermal management solutions within the package because of its size, as it has a larger area available to dissipate the heat. The smaller real-estate chips can be more expensive in terms of the thermal management solution, requiring an external heatsink or other cooling options.

BGA packages have options with both thermal pads, such as conductive vias or inbuilt metal base plates that can enable adequate heat management. Some options of thermally enhanced BGA packages can have a metal cap built onto them that establishes a thermal conduction path between the IC device and the metal cap, which provides good heat dissipation.

QFN packages are designed such that they have a solid metal die pad as the base of the package, to which the die is bonded.  This enables very good heat dissipation from the silicon die through to the PCB.

Die attach materials. Bonding the chip to the substrate with a thermal conductive adhesive like Sliver filled Epoxy, rather than plain epoxy, will help remove the heat. In addition, newer technologies are available like Silver sinter technology – an interconnection method with high operating temperature, high thermal and electrical conductivity. These materials typically work well in QFN packages, but are not as effective in BGA packages, due to the package construction. 

Chip size and wafer-level packaging. Thermal management in these packages is primarily done on the back of the chip, or in chip size package, on the exposed top-side of the chip.

High-Speed Signals/RF

RF, wireless and high-speed digital designs have specific requirements that affect package selection. The signal speed and the frequencies can be significantly degraded by the parametric effects of the interconnections within the package.

Wire bond vs. flip chip. In RF devices, key design considerations involve inductance, capacitance and resistance, which are affected by the speed of the signals travelling in and out of the device. These issues also impact package selection, primarily between flip chip and wire bond interconnections. Flip chip will provide better RF Performance and enable reaching higher frequencies with lower inductance. Wire bonds, on the other hand, can add a randomly-variable inductance at each RF input or output at higher frequencies.

Package layout. At RF frequencies, signals travel along the surface rather than in the conductor. Hence, the way in which the package is assembled has an important effect on the device. For example, high-speed amplifier chips, RF transistors, and diodes often cannot be put into a “standard” plastic package, as the encapsulation materials affect the speed in which the chip operates. Consequently, such chips should go into a cavity QFN or BGA package.

High frequency signals (1 GHz and above) are likely to require the layout of the interconnections to have isolated signal paths, known as “ground signal ground” interconnect. Here the requirement of two ground connections for every signal i/o will impact the package size and layout.

Additionally, with high-speed ASICs, the signal levels and timing will be affected by the length of the conductor that they travel along. For example, if you are using a BGA package and you have a longer lead to one point and a shorter lead to the next, you will have timing differences on the signal. This must be overcome by putting more consideration into the initial design of the package substrate to accommodate the high-speed RF devices.

BGA substrate dielectric materials are also a key factor in RF chips. For example, a high-performance liquid polymer substrate, like Rogers laminate, is better suited than the standard FR4 PCB material for use as the substrate for BGA packages used for RF designs.

To read a full-length discussion of packaging requirements, please see our white paper, The Ultimate Guide for Selecting an ASIC Package

Author

Written by Sharon Akler.

Sharon has a background in technology and innovation and more than 20 years of experience in global companies and startups. At DELTA, Sharon is looking after sales in Europe covering ASIC supply chain services.  

About DELTA Microelectronics

With over 25 years of experience, DELTA Microelectronics is a European leader in ASIC services for the semiconductor industry. DELTA’s comprehensive services include ASIC design, layout, test development, wafer supply, production testing, package development and assembly, components supply, logistics and supply chain management. DELTA’s development and production facilities are based in Denmark and the UK, with service partners in Europe and Asia. For more information, visit asic.madebydelta.com