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Dynamic Spectrum Allocation to Help Crowded IoT Airwaves

Dynamic Spectrum Allocation to Help Crowded IoT Airwaves
by Tom Simon on 06-26-2019 at 10:00 am
Categories: 5G, EDA, IoT, Magillem, Mobile

Radio frequency bandwidth has become a precious commodity, with communications companies paying top dollar for prized pieces of the spectrum. However, many radio bands are not often used efficiently. Many existing radio protocols exchange data on a fixed pair of frequencies, tying up those frequencies for other users. When this happens other users of those frequencies experience congestion that affects QoS. Then on the other hand there are often times in a reserved band where no licensed user is communicating at all. Years ago, it was recognized that if devices could more intelligently use the existing frequencies, efficiency could be dramatically improved.

The proliferation of wireless IoT devices is increasing crowding and the demand for improved efficiency. Additionally, it is no longer feasible to build a unique radio in a device to support each RF standard the devices requires. The solution to these problems is coming from software defined radio (SDR) combined with the intelligence to allow switching bands dynamically to utilize available areas of the spectrum. This new method of operation is called Cognitive Radio.

Cognitive Radio will encourage smart usage of IoT spectrum

Cognitive Radio, which allows dynamic switching between bands to access underutilized spectrum, has recently been made feasible through advances in radio design. The challenge has been to build radios that can work on a wide range of frequencies. Moving as much of the RF processing to the digital domain is a major component of this solution. This is coupled with the adoption of Sigma Delta Analog to Digital Converters (SD-ADC) for the down-conversion.

When properly implemented SD-ADCs can reduce quantization noise though oversampling and noise shaping, dramatically improving the signal to noise ratio.  Designers face many choices in the implementation the RF stage. Also, there is significant interplay between the digital portion and the RF stage, especially in tuning the baseband filters. Each wireless standard, such as GSM, LTE, 802.11, etc., has different signal requirements that must be accommodated in the radio.

Modeling and simulating the radio design is extremely important to ensure that it will operate properly once it is implemented and fabricated. SystemC and SystemC-AMS are proving to be useful tools in understanding the performance and behavior of radio designs. Choices need be made about design partitioning, parameter selection, software design, etc.

I recently had a chance to talk to Jean-Michel Fernandez, Embedded Systems Product Line Director, from Magillem about how IP-XACT can help this early design process. With SystemC models for each element in the design, it is easy with their MVP product to create a virtual prototype and then run simulation. This gives designers the ability to experiment with architecture, for instance relocating discrete RF components onto the SOC die. Also, the integration of software and hardware can be verified early in the design process. Later in the flow if the block level RTL has been brought into IP-XACT, the system RTL can be generated for synthesis, targeting an FPGA or ASIC.

With Magillem’s IP-XACT based MVP solution it is easy to assemble the receiver chain and then configure each component. Test benches can also be managed with MVP, so that everything needed for system level simulation is easily available. It is also straightforward to import legacy IP. MVP can automatically package existing SystemC code into IP-XACT.

Cognitive radio is one small piece in the increasing intelligence of electronic systems. It should significantly improve the overall efficiency and utilization of the airwaves. This will be seen by consumers in the form of lower communications costs, as well as in higher reliability and throughput. Magillem has information about their MVP product for managing design configurations and creating virtual prototypes on their webpage.

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Micron beats subdued guidance on output cuts

Micron beats subdued guidance on output cuts
by Robert Maire on 06-26-2019 at 5:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

2020 capex likely down at least 20% vs 2019 DRAM & NAND price drops versus slowing capacity. Investors happy cause it could have been worse.

Micron reported $1.05 in Non-GAAP EPS beating street consensus of $0.79 by $0.26. While this looks like a big beat, we would remind investors that estimates for the quarter were about $1.35 just four short months ago before further previous downward guidance. Revenues came in at $4.79B versus reduced street expectations of $4.7B.

Guidance is for revenues of $4.5B +-$200M and EPS versus street of $4.56B and EPS of $0.45+-$0.07 versus street of $0.70.  Guidance is obviously low but likely “sandbagged” just like the reported quarter.

Still cutting wafer starts to reduce supply to prop up pricing
Micron continues to cut wafer starts another 5% to try to reduce the oversupply condition which was worsened by Huawei.  The company made it clear that the market remains “oversupplied” even though the oversupply may be lessening.

We would imagine that Micron and other memory makers will continue to cut output until we getting into a better supply/demand balance and pricing starts to recover.

This supply/demand cyclicality is typical of many commodity like markets such as oil and other global markets and it sound come as no surprise to seasoned investors that the down part of the cycle always takes a significant amount of time to work off the excess capacity.

It should also be abundantly clear that when you are cutting capacity your capital spending to increase capacity goes to near zero levels.  Spending on “technology buys” continues, but raw capacity they don’t need right now.

2020 capex to be “meaningfully down” versus 2019
Micron has already cut 2019 capex from the prior $10.5B to the current expected $9.0B with a current run rate of about $8B.  While Micron did not specifically quote 2020 capex plans as they are still in flux, they did say “meaningfully down” from 2019’s $9B.  We think “meaningfully ” is code for 20% or more, not just 10%. That would suggest getting down to a “7” handle or lower. That would be down well over 30% from the peak but not as far down as Samsung which drove its capex off a cliff.

Makes it really hard for 2020 to be an “up” year for semicap
With Micron clearly cutting 2020 versus 2019 and Samsung in the exact same boat, we can’t imagine any memory maker who will be planning on a capex increase in 2020 which would imply we are not going to see a recovery that some optimists are suggesting.

Months ago we said that the current downcycle would be longer and deeper than previously expected due to China and only in the last couple of weeks have most analysts finally figured that out.  Many are still in denial by suggesting that 2020 will be up significantly.  Its not like logic and foundry are going to double spending to offset the ongoing memory weakness…its just not going to happen……so get over it.

Bit growth continues without capex increasing
What most investors and many junior analysts don’t get is that memory bit growth can continue without an increase in capex and can in fact see strong bit growth in a declining capex environment.  By continuing to follow Moore’s law, we get more bits in less silicon without increasing capex proportionately.

We have long held to the view that there are in fact two cycles underlying the industry. The technology spending cycle and the capacity spending cycle.  Technology spending (to further Moore’s law) usually goes on almost no matter what while capacity spend can go to near zero when the industry is over supplied such as it is now.

Right now Micron and Samsung can easily keep up with bit growth just with technology improvements to the next node.

Technology spend causes semicap share shift
When capex is focused on technology rather than capacity, more money tends to be spent on yield management and lithography which are the two primary drivers of Moore’s law.  This suggests that spending related to KLAC and other metrology/inspection companies as well as litho spending, with ASML, tends to hold up better than basic process tool sales

The Stocks- the “it coulda been worse” rally
Micron’s stock was up 8% in the aftermarket due to the fact that it wasn’t as bad as it could have otherwise been even though it was worse than expected 4 months ago.  Investors don’t seem to have quite latched on to the great miss on forward guidance. Basically anything is better than a miss.

We would not be surprised if semicap names are up in a sort of “kneejerk” reaction that will be positive across the chip market even though the news for semicap names is very negative given the capex guidance for 2020 being down which blows a hole in the “capex recovery in 2020” theory. But short sighted investors and analysts will likely latch on to the hope of the beat forgetting how reduced the expectations were.

We think the reduced 2020 capex comments clearly reflect the severity of the oversupply situation and Micron is voting with its feet in saying that things won’t get better enough in 2020 to warrant a capex increase.  We agree.  We think memory pricing will continue to stabilize as output continues to be cut but we see no huge rebound in demand that would force memory makers to increase capex any time soon.

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Upcoming HBM and CDM ESD Verification Seminar in Taiwan

Upcoming HBM and CDM ESD Verification Seminar in Taiwan
by Tom Simon on 06-25-2019 at 10:00 am
Categories: EDA, Events, Magwel

The electrostatic discharge that occurs in lightening, as seen in the picture below, can cause serious damage to the objects on the ground. Over centuries mankind has devised ways, such as lighting rods and arresters, to deflect the energy so it is dissipated harmlessly. The same drama plays out on modern semiconductors due to electrostatic build up on people, equipment or the devices themselves. MOS semiconductor devices can easy be damaged or destroyed by the currents and voltages that occur in discharge events during fabrication, assembly or handling.

The very first MOS devices could be destroyed simply by handling them with bare hands. Over the years, on-chip ESD protection has improved dramatically. However, nearly every semiconductor device needs to contain ESD protection circuitry. Properly designed protection networks are transparent during normal operation but are triggered when the device is exposed to an ESD discharge event. Designing these protections is a complex task and verifying them can also be a challenge. While most circuit designers leave the job of designing and verifying the ESD protections to ESD experts, it behooves all designers to understand the design considerations and trade-offs in ESD protection methods.

In Taiwan on July 16th interested engineers and managers will be able attend a seminar organized by Prof. Ming-Dou Ker, where Magwel Chairman and CEO Dundar Dumlugol will discuss the challenges of chip level ESD verification. The presentation will outline each of the steps involved in taking the layout of a chip and modeling it for CDM and HBM simulation. These steps include detailed resistance extraction of the involved nets. Then for HBM and CDM, either TLP or vf-TLP models are used for the ESD devices. Because of snap-back behavior in ESD devices, SPICE simulation is not an option. Dr Dumlugol will discuss the optimal static and dynamic simulation methods for both HBM and CDM.

In addition to triggering intended ESD devices, ESD events can cause triggering of parasitic sneak paths, and parasitic Bipolars. Failure modes can include electromigration and voltage overstress. ESD events can also cross between power domains.  ESD protection failures can affect IO devices and devices in the chip’s core. Dr. Dumlugol will discuss these various failure modes and ways that they can be detected before tapeout.

The Seminar is titled “Simulation Based Chip-Level Verification Methodology Of HBM and CDM Events” and will be held July 16th at Hsinchu Jiaotong University in Taiwan from 1:30 PM to 4:30 PM. At the end there will be a question and answer period. Seating is limited and advance registration is available online at http://www.alab.ee.nctu.edu.tw/~esd/reg.html

The seminar will include a demonstration using the techniques discussed in the presentation. This seminar is unique opportunity for learning about the risks and the underlying mechanisms of ESD failures, as well as practical techniques to prevent them in finished silicon. Here is a link to the PDF invitation download.

 

About Magwel

Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com

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Eta Compute Showcases Continuously Tuned DVFS

Eta Compute Showcases Continuously Tuned DVFS
by Bernard Murphy on 06-25-2019 at 6:00 am
Categories: AI, Eta Compute, IoT, IP

If you practice in advanced levels of power management, you know about dynamic voltage and frequency scaling (DVFS). This is where you allow some part of a circuit, say a CPU, to run at different voltages and frequencies depending on acceptable performance versus thermal tradeoffs and battery life on a mobile device. Need to run fast? Crank up the voltage and frequency to run a task quickly, then drop both back down to save power and allow generated heat to dissipate.

Intelligent compute at ultra-low power

DVFS is a well-known technique in PCs and servers, where boosting performance (for the whole processor) is an option and slowing down to cool off is the noticeable price you have to pay for that temporary advantage. This method is used at a more fine-grained level in the application processor at the heart of your smart-phone, where multiple functions may host their own separate DVFS domains, switching up and down as your usage varies. This method to balance performance versus power-saving can be especially important in any edge application demanding long battery life.

DVFS as commonly used is not an arbitrarily tunable option. System architects specify a fixed set of voltage/frequency possibilities, commonly two or three, then these options are hardwired into the chip design. In synchronous circuit design each clock option comes at a cost in complexity and size for the PLL, dividers or however else you generate accurate clocks.

But what if you’re using self-timed logic? Not necessarily for the whole SoC, but certainly for some critical components. I know of only one independent set of IP options today, from Eta Compute, so I’ll describe my understanding of how they implement tunable DVFS to get ultra-low power in intelligent IoT devices, down to a level that harvested power may be an usable complement to a backup battery. This is based on my discussion with Dave Baker, Chief architect at the company.

I introduced this company a while ago, on their introduction of a self-timed Cortex M3 core which would be a natural to use in this kind of IoT device. Since then, they have also struck a partnership with NXP to offer a CoolFlux DSP which hosts AI computation. As a reference design based on these cores they have developed their ECM3531 testchip with all the usual system functions, serial interfaces, a variety of on-board memory features and a 2-channel ADC interface (to connect to sensors). The system is supported by the Apache MyNewt OS, designed for the IoT, with built-in support for BLE, Bluetooth mesh and other wireless interfaces. Eval boards are already available.

OK, so far pretty standard except for the self-timed cores, but here comes the really clever part. Because this is self-timed logic, performance can be tuned simply by adjusting the voltage supply to the core. If the converter supplying that voltage is tunable, you can dial-in a voltage and therefore a performance. Eta Compute provide their own frequency-mode buck converter for this purpose. And you can tune the converter through firmware. The company’s RTOS scheduler monitors idle-time per heartbeat and computes if idle time is dropping, it should raise the voltage, whereas if idle time is growing, it can afford to lower the voltage. An optimal setting can be tuned to fall somewhere between a target setting for an application stage down to a frequency below which interrupt latencies may become a problem.

Now compare this approach with what I call run-fast-then-stop and Dave calls race-to-idle. When you have work to do, you crank the frequency (and voltage) to the maximum option, do the work as fast as you can, then drop back to the lowest frequency/voltage option. There is timer uncertainty in switching so power wasted during those transitions, scaling with the size of the transition. And of course power (CV2f) during the on phase is high. Compare this with the Eta Compute approach. On-voltage scales up only as high as will meet the idle-time objective, typically much lower than the peak voltage in the first approach. And power wasted during switching is correspondingly lower because transition times are shorter. Even the idle voltage can be lower since this too is tunable, unlike the hardwired option in conventional DVFS.

Eta Compute have run CoreMark and ULPMark benchmarks against a number of comparable solutions and are showing easily an order of magnitude better energy efficiency (down to 5mW at 96MHz), along with IoT and sensor application operating efficiency at better than 4.5uA/MHz. So yeah, you really can run this stuff off harvested power. In fact, they have shown a solar-powered Bluetooth application running battery-less at 50uW in continuous operation.

I skipped a lot of detail in this description in the interest of a quick read. Dave told me for example that the interconnect is also self-timed, important because buffers in the interconnect consume a lot of power. Therefore intelligent scaling of voltage in the interconnect is equally important. If you want to dig more into the details, click HERE.

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Lithography For Advanced Packaging Equipment

Lithography For Advanced Packaging Equipment
by Robert Castellano on 06-24-2019 at 10:00 am
Categories: Information Network, Semiconductor Services

Advanced IC packaging, such as fan-out WLP (Wafer Level Packaging) and 2.5D TSV (Through Silicon Via) will drive the packaging equipment market, particularly lithography. This will help specific equipment manufacturers in 2019, since the WFE (Wafer Front End) market will drop 17%. But the Back-End lithography market, led by Veeco.

Advanced Packages

The IC industry is evolving as new technologies replace old ones. As dimensions on advanced ICs move below 10nm, packages that house and protect them from the environment and aid in bonding to the printed circuit board are also evolving. Traditional wire bonding is being replaced by flip chip (FC) bonding, which, in turn, is being replaced by wafer level packaging (WLP).

Sales in Advanced Packaging are driven by shipments of lithography systems and upgrades to Outsourced Semiconductor Assembly & Test companies (or OSATs) and foundry customers in support of advanced packaging processes, such as Fan-Out Wafer Level Packaging (FOWLP) and Copper Pillar. OSAT growth and capacity will be driven by broader technology trends such as artificial intelligence (AI), mobile, autonomous vehicles, big data and 5G deployments.

 

Lithography Market

Competition in the advanced packaging lithography market comes from various reduction steppers and proximity and projection aligner companies such as: Canon (CAJ), EV Group, Rudolph Technologies (RTEC), Shanghai Micro Electronics Equipment Co., SUSS MicroTec, Veeco, and USHIO.

Chart 2 shows market shares for the advanced packaging lithography market for 2018, according to our report. The top three companies – Canon, Veeco, and EV Group held a 70% share of the market, and if we include SUSS, these companies held an 85% share of the market.

Chart 3 shows the 2018/2017 YoY growth of the advanced packaging lithography companies. Veeco grew 35% after a rocky transition following the acquisition of Ultratech. Veeco’s lithography tool is broadband stepper, which supports all three wavelengths–436nm, 405nm and 365nm. These are produced by a broadband spectrum mercury light.

Canon, a strong contender in the WFE and FPD (Flat Panel Display) lithography markets, grew 20.5% YoY. The company is utilizing expertise from a strong installed base of thousands of lithography tools, combined with improved optic resolution, to make reduction steppers a viable technology in advanced packaging.

According to The Information Network’s report entitled “Flip Chip/WLP Manufacturing and Market Analysis,” the number of ICs packaged in WLP will exhibit a CAGR of 6.8%. In contrast, IC growth in 2019 is forecast to drop 12.1% by industry consortium WSTS. Chart 1 illustrates the growth of WLP in terms of number of devices.

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1971 is the year that Intel changed the world

1971 is the year that Intel changed the world
by John East on 06-24-2019 at 5:00 am
Categories: Intel Foundry, John East
5 Comments

The “20 Questions with John East” series continues

From time to time I present the History of Silicon Valley as I saw it to various audiences.  I always enjoy doing that.  I’ve learned that the part that audiences like the most is the Apple / Steve Jobs story.  That’s not hard to understand.  Steve Jobs was truly fascinating! The story that captivates me, though, is this one.  I was working at Fairchild in 1971 watching this story unfold.  It took me 20 years to understand how important it was.  Looking back at it, it still amazes me!!

The years following the Intel 1101 introduction were dramatic!!  In 1970 Intel introduced the 1103 — the world’s first DRAM.  The yields were very poor. They couldn’t ship many. But the concept was born.  The stage was set for the future.  Then came 1971.

In 1971 the 1103 yields improved and they were able to ship large quantities. (In fact, by the time 1973 had ended, the 1103 was the biggest selling chip in the world.)    Also, in 1971, Intel announced the first erasable floating gate memory — the 1702.  The 1702 was a 2K PROM (Programmable read only memory) which stored its contents on the gates of “floating gate” transistors.  This by itself wasn’t particularly exciting,  but there was a twist:  By radiating the die with UV light (Made possible by a see-through lid on the top side of the package),  you were able to erase the contents and then reprogram it.  It wasn’t a PROM after all.  It was the world’s first EPROM (Erasable programmable read only memory).  Finally, in 1971 Intel introduced the microprocessor.  Their first microprocessor, the 4004, was only a 4 bit processor but again, it set the stage.  And oh –  by the way. They went public in 1971 making many of them multi-millionaires.  You couldn’t be more deserving!!

So,  in 1971 Intel commercialized the first DRAM,  introduced the first floating gate memory,  and introduced the first microprocessor.  How impressive is that?  Today – nearly 50 years later –  those three categories comprise well more than half of the world semiconductor market.  (How much more?  Good question.  To come up with a valid number you’d have to know how much embedded memory and how many embedded processors are inside of all the ASSPs that are being shipped.  That’s way above my pay grade  — but I’ll bet Daniel Nenni could do it)

Boy.  Did that ever aggravate us at Fairchild.  We felt like we were working hard, but they were killing us! How in the world did they do it?  How did they invent their way into stardom while at Fairchild we were spinning our wheels?  I’ve met Gordon Moore only twice  —  the first time was at a party at Larry Sonsini’s home (Wilson-Sonsini is the dominant Silicon Valley law firm).  Some time later I sat next to him at some sort of industry dinner back in the early eighties.  I can’t remember what the dinner was for or why I sat next to him, but I do remember the conversation.  I asked him that question:  How did you do it? How did you build and incentivize a team to foster such innovation?  His answer was:  First  – you hire really smart people.  Second – you make it clear that they will get the credit for their work.  And third – you let them know what you wish they would invent.  If you don’t do that, he said, lots of crazy things are going to get invented that you will have no use for.

I don’t think that Gordon could pick me out of a police lineup if he saw me today.  (I hope he never has the opportunity!!) We met only those two times. But, I’ve heard so much about him from some of my friends who worked for him I feel like I know him. Gordon was always known for being modest and unassuming.  He famously drove an old car to work every day so people wouldn’t think he was putting on airs.  He wanted to be seen as a “regular guy”.  Regular guy?  For a guy with an IQ of 200 and several billion dollars in the bank??? Tough to pull off, I suspect. (I wish I had first-hand knowledge.)  But  — if you sit next to him at dinner,  that’s the feeling you get. By the way, Gordon is at least $5B lighter in the wallet than he used to be.  He once donated 175 million shares of Intel to charity.

The Intel story isn’t all glory.  Real life stories never are.  Their worst stretch came in the early to mid-eighties.  Japan Inc had embarked on a plan to conquer the world’s integrated circuit business by taking control of the three M’s:  Memories,  Microprocessors,  and Master slices (gate arrays).  They (the Japanese) were already good at manufacturing.  They already had low costs.  Their strategy was to bomb prices until the American companies, who were less well capitalized and had huge pressure from shareholders to keep earnings high, gave up and got out of the business.  The easiest and most obvious target was the DRAM market.  DRAM prices were dropping like a rock.  Intel began losing money for the first time since their IPO in 1971.  DRAMs, which once represented 90% + of Intel’s revenues, were down to a few percent by 1984.  Even though Intel had invented the DRAM, by 1984 they had no particular strategic or technical advantage.  They were good at DRAMs.  So was everybody else. On the other hand, because of their design win in the IBM PC, they had attained a near dominant position in the microprocessor market.  That market had barriers to entry much higher than DRAMs ever had or could have.  Should they exit the DRAM business?  There were great debates.  A quote from someone inside the company went, “Intel leaving the DRAM business would be like Ford leaving the auto business”.  In the end they opted to exit.  The P&L was messy for a couple of years.  A quote from their 1986 Annual Report went,   “We’re pleased to report that 1986 is over.” Then, their shares grew steadily until their market cap hit nearly $300 billion.  I guess it was the right decision.

When I was young, America was better at everything.     Cars, steel, shoes, clothing, engineering, etc.  Everything!!  “Made in Japan” was a derogatory term.  China didn’t matter at all in the world economy.  Taiwan and Korea were trying to matter, but they didn’t.  Today, as a nation, the USA has lost a lot of that.  Industries that used to pay for our way of life are now struggling in America.  But  — we’re still really strong in high tech.  Sure, we have competition, but we’re the force to be reckoned with.  If there were a king of high tech, it would be us.  Without the contributions of Intel (And Microsoft) that wouldn’t be true.

Thanks Gordon.  Thanks Bill Gates.

Next week:  Layoffs ala Fairchild

View Entire John East Series

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FPGA Prototyping for AI Product Development

FPGA Prototyping for AI Product Development
by Randy Smith on 06-21-2019 at 8:00 am
Categories: AI, Prototyping, S2C EDA

I recently wrote about The Implications of the Rise of AI/ML in the Cloud. In that article, I wrote about my expectation that the rapidly growing AI market will lead to the accelerated use of high-level synthesis (HLS), prototyping, and emulation. In this article, I will focus on the prototyping portion of that – specifically FPGA prototyping.

As has been noted often recently, the number of Artificial Intelligence (AI) development teams is exploding. While some are in big companies, there are a lot of start-ups as well. But AI differs from many other areas because, it is such a new domain, the things that need to get implemented, such as algorithms, architectures, software, dev ops considerations, etc. are all changing multiple times during the design cycle. How can design teams deal with this, especially the smaller companies with fewer resources?

Emulation boxes are fast, and for an even larger outlay, they can handle design capacities exceeding 2 billion gates. Many start-ups cannot afford those expensive solutions and don’t need quite that capacity. FPGA prototyping offers solid support for several critical functions at a fraction of the cost of emulation hardware. For a small-to-medium sized company, it is a good idea to find a tool for a reasonable price that can handle multiple tasks – more tasks than would typically be handled with an emulation tool. When I looked at S2C’s offering their Prodigy prototyping solutions can be used for design exploration, IP development, hardware verification, system validation, software development, and capability testing. In short, you can use it throughout the hardware design cycle. You can use the same tool in exploring architectural options that you use to validate the functionality of the design. You can also use the same system to develop and the test the software that will run on these devices without having to wait for the final silicon to come back from the factory.

The Prodigy product family also includes ProtoBridge. This product enables the high-speed communications necessary to have a prototyping environment with a transactor interface between software and AXI-compliant hardware. While the system was initially developed with ARM-based systems in mind, it would seem they could easily be used (and probably have already been used) to develop RISC-V systems sporting AXI compliance (such as the SiFive S51). I think this could be very important given the large number of AI teams intending to use RISC-V ISA cores.

My previous article highlighted some AI/ML solutions in the cloud from larger providers in that area – Google, Microsoft, IBM, etc. This is because it is easier to find public information on these offerings since they are available now. But the large and diverse developments at smaller companies is indeed staggering. There are more than 60 startups in the AI market, many of which have already raised $50M or more. While $50M is a lot of money, it doesn’t go very far today if you are designing a chip at one of the newer process nodes. What I am hearing is that developing the AI algorithm in parallel with the chip is quite difficult. These AI algorithms are always under development and yet getting a working prototype before tape-out is critical. Showing a working prototype may also be a critical part of getting the next round of funding. On top of that, just the costs of a new mask set (to fix design flaws that should have been detected earlier) set can kill the company’s dreams. But the creative multifaceted use of FPGA prototyping from a company like S2C can do wonders to stretching that budget.

S2C’s technology is proven. It is trusted by dozens of companies you have heard of, names like Intel, Samsung, Qualcomm, Cypress Semiconductor and LG. AI companies should really give this consideration. S2C pricing starts at under $10,000 for about 10M equivalent logic gates and scales up to much higher capacities.  To get a quick S2C quote click here.

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#56thDAC Discussion on Calibre in the Cloud Brings Sunshine to SOC Developers

#56thDAC Discussion on Calibre in the Cloud Brings Sunshine to SOC Developers
by Tom Simon on 06-20-2019 at 10:00 am
Categories: EDA, Events, Siemens EDA

It was inevitable that EDA applications would meet the cloud. EDA has a long history of creating some of the most daunting compute challenges. This arises from employing current generation chips to design the next generation chips. Despite growing design complexity, many tools have kept pace and even reduced runtimes from generation to generation of process technology.

Mentor’s Calibre is a good example of this, with its annual performance improvements of 25%. Because of that, Mentor’s level of innovation has kept up with the doubling of transistors seen from one node to the next. Naturally designers are glad that turnaround time has held steady over the years. This has been accomplished with foundry assisted rule deck optimization, runtime memory reductions, core engine improvements, and the addition of parallel operations. However, sometimes standing still is not enough.

The cloud presents a huge opportunity to obtain absolute gains in throughput that cannot be realized in any other fashion. However, it is not as simple as launching a few cloud CPU instances and running tools. At the 2019 DAC in Las Vegas, Mentor hosted a four-way presentation about their cloud solution for Calibre. There is no doubt that DRC runtimes can be a bottleneck during the final stages of chip design prior to tapeout. This combined with the accompanying dataset size and computational complexity makes DRC an ideal candidate for cloud based improvements.

The other participants besides Mentor in the presentation were TSMC, Microsoft and AMD. Each of them plays a key role in development of the cloud solution for Calibre. Mentor has made many changes to Calibre to improve efficiency in the cloud. Michael White, Calibre Physical Verification Product Marketing Director, talked about how they worked to make launching cloud-based runs more transparent, by using architectural changes in the way jobs are scheduled and data is transferred to the cloud. Because the cloud can provision extremely large numbers of processor threads, Mentor has exploited every avenue to allow increased parallelization.

Next, we heard from TSMC’s Willy Chen, Deputy Director of Design Methodology & Services Marketing for their Design and Technology Platform. He talked about how on the 10th anniversary of the TSMC Open Innovation Platform (OIP), they worked with Mentor on the “Calibre in the Cloud” project. As part of this this Mentor has joined the OIP Cloud Alliance. This includes a cloud certification process, which focuses on security and creates a legal framework for all the necessary parties to work together.

For the certification process they used a TSMC N5 test chip with Calibre. This design has 500M gates and has a GDS size of 17 GB. The runtime was reduced from 24 hours to 4 hours. This was largely the result of being able to efficiently apply 1024 CPUs as compared to a baseline of 256.

Prashant Varshney, Senior Director, Product Management Azure Engineering from Microsoft spoke about how they looked at every aspect of the chip design process to understand the requirement for each step in terms of memory, CPUs, threading, etc. Using this information, they have mapped each step in the process to specific Azure resources. They also have unique technologies, both in-house and through partnership, for improving cloud performance. Netapp is helping them optimize NFS performance, CycleCompute allows them to bring up 60,000 cores in just 20 minutes. Lastly, AvereNFS helps improve I/O performance with a cloud disk read cache, which is useful for libraries, etc.

The most interesting aspect of the meeting was the AMD presentation. Here we literally see their latest hardware being used to design the next generation of hardware. AMD EPYC processors are used by Microsoft in the Azure Cloud. James Robinson, MTS Silicon Design Engineer at AMD spoke about their experience using Calibre in the cloud. He said that AMD EPYC is well suited for Calibre, with 4 silicon die in each package, containing a total of 32 CPUs that offer 64 threads. There are also 8 DDR4 channels for improved memory support.

Initially the memory requirements for Calibre were prohibitive. However, James observed that Calibre’s per instance memory requirements are reduced as jobs are distributed over greater numbers of processors. He was able to reduce the memory needs so that they fit into available instance types this way. Of course, this offers the added benefit of reduced runtimes. They also learned that it is more efficient to wait to allocate the worker instances until they are needed. Mentor made changes to include this improvement. Mentor gave AMD early cloud-optimized versions of Calibre for testing. James reported that AMD saw a 10 hour run reduced to just over 6 hours.

The takeaway from this presentation was that by combining the efforts of cloud providers, foundries and EDA vendors, significant gains can be made relative to running tools on premises with more limited resources. The cloud can be cost effective because you can literally buy “time”, one of the most valuable commodities for a business. James from AMD pointed out that he was able to apply 4,000 cores to his Calibre runs, which according to him, not even AMD has available on short notice.

After many years it seems that cloud computing for EDA applications is ready and can be an effective tool in increasing productivity. There is more information about Calibre in the Cloud on the Mentor website.

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ARM Spins New IP for Client Applications

ARM Spins New IP for Client Applications
by Bernard Murphy on 06-20-2019 at 5:00 am
Categories: 5G, AI, Arm, IoT, IP
2 Comments

Arm is a machine. They crank out new products in a wide range of categories, Project Trillium for AI, Neoverse for infrastructure, their Automotive Enhanced line and the Pelion IoT platform. And in each they have a regular beat of new product introductions following roadmaps they have already laid out. Not that you’d expect any less from a company in their position. Nevertheless, that they continue to deliver and expand high volume innovation pretty much as they forecast underlines that this is not a company resting on its laurels.

Ian Smythe VP Marketing for the client LOB announced three new IPs last month, directed particularly at mobile devices and the opportunity 5G is creating in those devices. Ian made an interesting point about AI and mobile which I hadn’t realized. I’m generally pretty dismissive about CPU-hosted machine-learning (ML) as the bottom end of the ML hardware hierarchy, but he pointed out that 85% of ~4 billion smart phones are running ML workloads without any dedicated ML hardware assist, using in many cases just CPUs or CPUs plus GPUs. Makes sense – ML hardware on phones is still a pretty new concept and an added cost, so continuing to push CPU-based and GPU-based support for mobile is still very worthwhile.

The first of the IP introduced was the Cortex-A77, building on the A76 architecture but offering a 20%+ advance in instructions-per-cycle performance, still very much targeting smartphone power envelopes and area. Arm sees these devices being particularly helpful in supporting emerging use-cases such as VR/AR/MR (collectively xR) and more advanced ML applications. Ian pointed out an interesting trend in performance for the A-class devices. Arm spent about 4 years, up through around 2016, doubling performance over the A15 but they doubled performance again in the following 2-3 years up to the A77. So they’re accelerating performance improvements while still keeping to mobile client efficiency (power, area) targets.

The next IP up was the Mali-G77. This is also based on an architecture change over the G76, delivering 40% higher performance over that earlier system. This new platform also manages to provide 30% better energy efficiency and 30% better performance density (more performance in a smaller area which is important given the generally large footprint of GPUs in mobile SoCs), along with an improvement in ML performance of 60%. So lower power, smaller area and faster object recognition.

Finally Ian introed the Mali-D77, a second-generation display technology based on their Komeda architecture and targeted particularly to untethered head-mounted displays. This is one of those many domains, almost everywhere, where a general-purpose solution (in this case a GP-GPU) could do the job, but intelligent offloading can do that job so much better. A smaller more dedicated device can do the job of managing display at lower power than the GPU and it can do it faster. The latter is rather important in HMDs because delays between body movement and perceived movement in the display are known to cause motion sickness. So less feeling groggy in your headset and smaller, lighter headsets makes for bad news for your pharmacist and chiropractor but good news for general health.

Ian said that these IPs are available for licensing, early access customers are already designing them into products, and he expects the first of these products to appear in 2020. Good advances, should be a real plus for a fuller mobile 5G experience: gaming, HD video, better voice control and generally more intelligent interfaces on-the-go.

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SiP is the new SoC @ 56thDAC

SiP is the new SoC @ 56thDAC
by Tom Dillinger on 06-19-2019 at 6:48 pm
Categories: Cadence, EDA, Events
3 Comments

The emergence of 3D packaging technology has been accompanied by the term “more than Moore”, to reflect the increase in areal circuit density at a rate that exceeds the traditional IC scaling pace associated with Moore’s Law.  At the recent Design Automation Conference in Las Vegas, numerous exhibits on the vendor floor presented unique packaging options.  Yet, advanced packaging technology also requires corresponding methodology flows, spanning all facets of design, implementation and (electrical plus thermal) analysis.  I had an opportunity to catch up with John Park, Product Management Director for IC Packaging and Cross-Platform Solutions at Cadence, to talk about the flow requirements for these packaging solutions.

Taxonomy – SoC’s, SiP’s, and Chiplets

To start, I asked John for his insights on how to best understand the different terminology used to describe these package offerings.  He began using the image below:

John said, “Multi-chip module (MCM) technology has been around for decades, applied to very specific high-performance computing, communications, and aerospace applications.  The engineering resources to develop the physical implementations were considerable, as was the investment in chip-package-system electrical analysis.”

John continued, “This was followed by two trends.  The ongoing silicon technology scaling of Moore’s Law led to the introduction of system-on-chip (SoC) architectures, integrating IP from multiple sources.  Correspondingly, the signal and power I/O count of these die increased, as well.  The introduction of 2.5D packaging technology, with aggressive interconnect line/space pitch on an interposer (or substrate) enabled these high pin count die to be integrated on a complete system-in-package (SiP).  SiP opportunities have continued to expand.  The introduction of 3D packaging with vertically-stacked die using through-silicon vias (TSV’s) is a recent offering – this technology presents unique constraints to EDA flows, from (limited) pin access for test to different thermal modeling requirements.” 

“I’ve heard a lot recently about chiplets.”, I said.   “What’s a chiplet?”

John replied, “The next trend in SiP design is the integration of heterogeneous chiplets.  It is likely the case that not all functionality in the system needs the PPA characteristics of the same process node.  There may be cost and schedule advantages to the integration of (hard) IP functionality from different sources and technologies – these silicon IP’s are chiplets.  The chiplet I/O’s are simply microbuffers, with an appropriate test wrapper definition.  Chiplets represent a foundry and process node independent disaggregation of the IP in an SoC.  In short, the SiP is the new SoC”.

I asked, “Today, there are some (de facto) architectural definitions for interfacing the IP integrated in an SoC.  How will this extend to a chiplet-based SiP?”

John indicated, “There is a great deal of activity to establish a comparable architectural definition for chiplet based designs – perhaps the best known is the “Advanced Interface Bus” (AIB) specification that Intel has recently provided (license royalty-free).” 

AIB is a parallel bus, clock-forwarded definition for the physical layer interconnect between chiplets, similar to the parallel interface of a DDR DRAM memory module (with single data rate for control signals, double rate for data transfers).  The parallel interface suggests that the connections on the SiP will be “electrically short” and that the available chiplet bumps will be sufficient for parallel bus communications – the additional complexity of SerDes design and the related signal integrity analysis is not required.  Here is a site with more information about AIB, including a download of the specifications (link – registration required for download).

Note that there is also a DARPA program focused on defining a similar IP-chiplet design and reuse platform – “Common Heterogeneous Integration and Intellectual Property Reuse Strategies”, or CHIPS (link).

John added, “There will also be a significant focus on the verification IP (e.g., the verification compliance testbench) for chiplets on an SiP.”

I thanked John for the very lucid description of the nascent chiplet-based design strategy (and for the title of this article).  We shifted gears to discussing how these SiP technologies have impacted EDA tool and flow development.

SiP Reference Flow

The release of a new silicon process design kit (PDK) by a foundry commonly also includes a description of the EDA platform tools that have been qualified for the process node – i.e., the “EDA reference flows”.  John indicated that advanced SiP design kits are also being accompanied by corresponding reference flows.  He described a recent collaboration with TSMC, to provide a comprehensive design and electrical analysis tool suite for TSMC’s advanced (2.5D and 3D) package offerings – e.g., CoWoS, InFO, WoW, and SoIC.  Here  is a list of some of the reference flow tools described in that collaborative announcement, with a few words on their interoperability for SiP designs (link):

Specifically, John focused on the recent enhancements to the OrbitIO interconnect designer.  “The diverse nature of the SiP silicon and package technologies necessitates using different tool platforms.”, John said.  “The methodologies that have been used to manage the overall SiP design tend to be rather ad hoc – for example, spreadsheets exchanged between engineering teams to represent the connectivity between silicon die microbumps, interposer routes/vias, through-silicon vias, and package bumps.  A single, consistent interconnect manager is needed to represent and maintain this model – that is the role of OrbitIO.”

John continued, “OrbitIO provides the SiP model across the platforms used for implementation and analysis of digital die, AMS die, and the package/PCB.  Note that the data representation between OrbitIO and each platform is bidirectional – there is direct integration with the platform to exchange the planning and implementation data.  As additional detail  and/or revisions are made in the specific platform, the updates are reflected in OrbitIO.”

“Are there model connectivity checks available in OrbitIO?”, I asked.  “Sourceless and sinkless pin checks, for example.”

“Yes.”, John replied.  “Further, there are extensions available for customers to develop their own rules and checks.”

There is definitely growing momentum for SiP designs, leveraging advanced 2.5D and 3D packaging technologies.  A significant percentage of those designs will integrate chiplet-level IP – look for standards to emerge for the interconnect fabric (and test methods) between chiplets.  To leverage the packaging technology, a comprehensive EDA strategy is required, to enable planning, implementation, and analysis across different engineering domains as well as to provide a complete, consistent SiP model across tool platforms.  For more information on how Cadence has approached the support for complex SiP’s, please follow this link.

-chipguy