SemiWiki – Page 363 – The Open Forum for Semiconductor Professionals

February 13, 2020January 8, 2021

Thermal Reliability Challenges in Automotive and Data Center Applications – A Xilinx Perspective

Thermal Reliability Challenges in Automotive and Data Center Applications – A Xilinx Perspective
by Bernard Murphy on 02-13-2020 at 6:00 am
Categories: AI, Ansys, Inc., Automotive, EDA, Xilinx
3 Comments

I wrote recently on ANSYS and TSMC’s joint work on thermal reliability workflows, as these become much more important in advanced processes and packaging. Xilinx provided their own perspective on thermal reliability analysis for their unquestionably large systems – SoC, memory, SERDES and high-speed I/O – stacked within a package. This was presented at the ANSYS Innovation Conference in Santa Clara recently. They put special emphasis on applications on datacenters and automotive, two areas where FPGAs are playing important roles for their ability field-upgradable to meet new demands.

I’ve talked before about AI functions in the datacenter. Die sizes of leading-edge 7nm AI chips are already reaching reticle limits and consume hundreds of watts of power. Automotive electronics, on the other hand, operate in very harsh environments for extended periods of time. They must be highly reliable, safe and have a zero-field failure rate over a life span of 10 to 15 years. The smallest failure in a safety critical system could potentially cause a fatality, which is unacceptable. Both create new demands to ensure thermal reliability.

Thermal reliability is a big deal in these advanced designs for multiple reasons. First FinFET transistors are prone to something called self-heating. They heat up more quickly than traditional planar transistors. Second, interconnects have some resistance and generate heat when current flows (Joule heating). Third, heat dissipates very slowly on electronic switching time scales. And fourth, all this heating is compounded when you stack chips on top of each other. That’s a problem for reliability because increased temperatures affect (among other things) increased electromigration (EM), thermally induced mechanical stress and solder joint fatigue, leading ultimately to functional failures.

What I found interesting about the Xilinx story, because I’m a math and physics nerd, is that Xilinx and ANSYS shared a bit more on how this flow handles modeling for the heat diffusion problem in chip/package structures.

ANSYS RedHawk (or ANSYS Totem for analog blocks) computes, based on detailed knowledge of layout and structures together with simulation, a T (temperature above nominal) for each wire. This comes from self-heating and Joule-heating. Do this for all wires. Then, per wire, look at the impact of heating in neighboring wires. The closer a neighbor is to the wire of interest, the higher the impact it will have. These coupling contributions are calibrated to the process in the tool. Add together all meaningful contributions from neighboring wires (superposition) and you get the total heating in the current wire.

Turns out this can overestimate heating in some cases. For example, foundry estimates might show no more than a 5^o T in areas of dense heating, where a superposition calculation can exceed that limit. Xilinx and ANSYS figured out a way to compensate for this effect by applying a T clamping approach which bounds this over-estimate. It also estimates heating for current flow isolated to a single wire to more like 1.25^o, well below the nominal 5^o T, correlating well with foundry estimates. Based on these calculations, local EM failure rates can be calculated quite accurately and can show, especially in those isolated wire heating instances, less pessimistic estimates than global approaches.

Xilinx next talked about temperature gradients across the chip. Traditionally you require that worst-case transistor junction temperatures be held below some maximum allowable level across the design. Heating from any of the above sources adds to this problem, leaving you with few options – spread out any places that get hot, wasting area or go for a bigger device, or run the clock slower until the chip cools down. But a more granular approach may show that trying to design your way out of the problem is over-compensating.

Here the Xilinx approach gets interesting. They calculate a cumulative failure rate (CFR) for the chip in a composition fashion, where each block has its own CFR budget. For blocks where T is low in this temperature distribution, there is no concern. For a block where T is high, they re-examine the CFR budget for that block to determine if it can be adjusted to still ensure an acceptable lifetime for the whole device. They don’t explain how they do this, but they do provide a couple of references that the more determined among you may find relevant.

Interesting study, you can learn more by registering to watch the webinar.

February 12, 2020July 6, 2020

TinyML Makes Big Impact in Edge AI Applications

TinyML Makes Big Impact in Edge AI Applications
by Tom Simon on 02-12-2020 at 10:00 am
Categories: AI, Eta Compute, IoT, IP

Machine Learning (ML) has become extremely important for many computing applications, especially ones that involve interacting with the physical world. Along with this trend has come the development of many specialized ML processors for cloud and mobile applications. These chips work fine in the cloud or even in cars or phones, but they are nowhere miserly enough when it comes to power consumption for use in IoT applications. For instance, many automotive ML processors use between 100W and 500W. Edge devices such as phones can get by with one tenth of a watt, but to go into what Eta Compute calls the extreme edge, power consumption has to be in the realm of 1 to 10mW.

Let’s look at some extreme edge applications and why it is useful to have ML processing performed locally. IoT devices at the extreme edge will perform many sensor related tasks. Examples are thermostats, occupancy sensors, smoke detectors, etc. Included in this group are medical and fitness devices such as fitness bands, health monitors and hearing aids. For commercial applications we see things like asset tracking, retail beacons and remote monitoring. Many of these use small batteries and require long battery life. Some even rely on energy harvesting for power.

Looking at the list above it becomes clear how ML could be useful. Yet these devices cannot afford the energy budget to transfer raw data to the cloud for processing. There is also a cost saving to not relying on cloud processing for every IoT device that needs ML capabilities. Another benefit is the low latency achieved by saving a trip to the cloud for recognition tasks or even training. The solution is to build highly optimized ML processors for IoT and extreme edge usage.

This is exactly what Eta Compute has done with its announcement of their ECM3532 Neural Sensor Processor at the second TinyML Summit held in San Jose on February 12^th. The ECM3532 is an SoC for ML and can be trained with the popular.

TensorFlow software. Their chip is especially interesting because it gains a huge efficiency advantage through their self-timed continuous voltage and frequency scaling (CVFS) technology. Because the control CPU and the DSP, which includes optimized MAC units, both use CVFS they are seeing a 10x reduction in power compared to traditional clocking and voltage supply approaches.

The ECM3532 contains an ARM Cortex-M CPU and a dual MAC 16-bit DSP. It also has onboard memory (Flash, SRAM, ROM), an ADC, serial interfaces, GPIOs, RTC, clock generation and power control. Running a variety of different benchmarks and applications, the ECM3532 is able to perform inference with less than 1mA of power consumption. Even when running COREMARK at up to 100 MHz its power consumption stays in the single digit mW range. The chip is capable enough, with 512KB of Flash and 256KB SRAM, for Eta Compute to provide demos in speech, image and video recognition, and industrial sensors. To provide flexibility in communication choices, the ECM3532 itself does not have onboard RF support, but it is expected to be designed into packages or boards with any desired wireless protocol chip or chiplet for cloud connectivity.

Because of their architecture choices on CPU, DSP and MAC, they are seeing excellent results in performance. On the CIFAR-10 CNN dataset they were able to reduce the number of operations required by a factor of 10 and reduce the weight size by 2 and achieve similar accuracy compared to published academic results.

Eta Compute is opening the doors to making IoT devices smarter and more responsive without drawbacks of shorter battery life or infeasible unit costs. Smarter IoT devices will offer more functionality and play a larger role in industry, medicine, appliances and elsewhere. It will be interesting to see the applications that are developed using this breakthrough technology. More information on their announcement can be found on the Eta Compute website.

February 12, 2020January 8, 2021

De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue

De-Risking High-Speed RF Designs from Electromagnetic Crosstalk Issue
by Mike Gianfagna on 02-12-2020 at 6:00 am
Categories: Ansys, Inc., EDA, Events

At DesignCon 2020, ANSYS sponsored a series of very high-quality presentations. Some focused on advanced methods and new technology exploration and some provided head-on, practical and actionable capabilities to improve advanced designs. The presentation I will discuss here falls into the latter category. The topic was presented by Anand Raman, senior director of application engineering for on-chip EM solutions at ANSYS. Anand is one of those people who has infectious enthusiasm. He will draw you into whatever topic he is presenting and get you involved. Given the impact of his material, it was quite easy to do in this case.

Anand began by pointing out that most people understand the need for electromagnetic (EM) analysis for high-frequency RF designs (chip and board). The structures and operating frequencies of this class of design utilize “purposeful inductance” that needs to be modeled. He then pointed out that these challenges can also exist in ultra-high-speed digital designs, in subtle and hard-to-find ways that can cause large problems due to parasitic inductance. A collection of correctly designed and verified blocks can fail when assembled onto a chip due to remote coupling effects. Power/ground networks can become channels to create these subtle problems.

Anand pointed out that extremely thin routes that run long distances and carry very high-speed data is a formula for extreme inductance effects. Capacitance extraction has been widely used in digital design for a while now. It’s time to consider inductance effects as well. Parasitic inductance causes two problems – signal distortion and parasitic coupling due to the magnetic field.

It turns out that an EM-aware design flow can do more than ensure a working chip. It can also provide the opportunity to improve circuit density as well. The figure below summarizes some of these effects for two generations of the same design. The second one is over 37% smaller, owing to the ongoing and complete modeling of all EM effects, allowing for a more aggressive design.

Going back to the subtle and non-intuitive nature of magnetic coupling, Anand provided a good graphic to explain the problem, see below. The third loop mentioned below could be created by the thousands of structures in a power distribution network.

ANSYS provides a platform of tools to get to the required level of coverage for a true EM-aware design flow. These tools integrate with existing digital design flows and provide several levels of analysis support. The tools, and their field of application, are summarized below.

Regarding the other benefits of an EM-aware design flow, several examples were presented based on real designs. In one case, shown below, active circuitry was folded under an inductor, resulting in substantial area savings. This was made possible by analysis from the previously mentioned ANSYS EM tool platform to ensure this change did not introduce EM coupling effects. VeloceRF was also used to synthesize a much smaller inductor. Overall, there was a 66% area saving with slightly better performance.

Several other real design examples were presented that highlight the way subtle EM coupling can cause significant design problems. These examples included a working chip that degraded in the package due to EM crosstalk from the ground net to the first few package layers. Other cases of degradation due to coupling through the package were presented. Another interesting case illustrated how the seal ring in a chip cause an inductive coupling loop.

I would say Anand made a strong and passionate case for the benefits of an EM-aware design flow. To check out an example of a customer case study on the topic of de-risking high-speed serial links from on-chip electromagnetic crosstalk and power distribution issues, click HERE.

February 11, 2020July 6, 2020

Innovation in Verification – February 2020

Innovation in Verification – February 2020
by Bernard Murphy on 02-11-2020 at 6:00 am
Categories: AI, EDA

This blog is the next in a series in which Paul Cunningham (GM of the Verification Group at Cadence), Jim Hogan and I pick a paper on a novel idea in verification and debate its strengths and opportunities for improvement.

Our goal is to support and appreciate further innovation in this area. Please let us know what you think and please send any suggestions on papers or articles for us to discuss in future blogs. Ideas must be published in a peer-reviewed forum, available (free or through a popular site) to all readers.

The Innovation
Our next pick is “Learning to Produce Direct Tests for Security Verification using Constrained Process Discovery”. This was presented at DAC 2017. The authors are Kuo-Kai Hsieh, Li-C. Wang, Wen Chen, (all from UCSB) and Jayanta Bhadra from NXP.

Security verification is a challenging part of any complete test plan. Black hats know that general testing tends to go more broad than deep in order to bound the scope of tests, so look especially for complex penetration attacks. This paper offers a method to learn from deep penetration testing developed by security experts to generate more penetration attacks of similar type.

All tests in this method are based on sequences, in the paper as sequence of calls to C operations – might be C or portable stimulus standard (PSS). They start with tests developed by security experts and, through grammatical inference (a type of machine learning) they build an automaton model, representing a complete grammar of all such tests.

Training also develops constraints, given observed limitations in sub-sequences in the training examples. The authors say the automaton model matures relatively quickly and constraints continue to mature with more examples.

Once trained, model plus constraints can be used to generate new sequence tests through a SAT solver. Generated tests are run in conventional verification environments. They show result of their analysis, presenting an increase in coverage points (CPs) defined by experts.

Paul
I really liked the exposition of the problem in this paper, concepts of confidentiality, integrity, availability. The authors go on to combine two ideas, constraint solving (a standard verification method), with an idea of grammatical inference. This is a nice follow-on from our previous blog (which used genetic learning to improve coverage).

Another thing I thought was intriguing was using machine learning to generate attacks, rather detect attacks, as AI is often used as a method for detecting behavioral anomalies in real-time. Their method, grammatical inference on a state machine, is something that would be interesting to apply on top of PSS engines. If someone was interested in doing this – for research – I’d be happy to support them with a Perspec license.

The test example shows promise. It would be interesting to see how the method scales over a range of test cases and sizes. I’d also like to see more discussion on metrics for assessing the effectiveness of security verification methods. This is a tricky area, I know, but all insights are useful.

For example, using cover points as a metric is certainly useful to increase general coverage, but doesn’t give a clear sense of impact on security. Is it possible to adapt the approach consider impact on attack surface (for example), a metric more directly tied to security?

Overall, I think there were some nice ideas prompting this work. I would like to see them developed further.

Jim
I’m going to take a bit of a different tack here, more where I think security may head and the current market.

First, directions. At the high end (servers), security is becoming a game of whack-a-mole. Before a vulnerability has been fixed, a new one has been found. I don’t think our current approaches are sustainable. We need to be looking at more vulnerability-tolerant architectures.

At the low end (IoT), decent security is better than none so still plenty of opportunity for methods of this type.

In adoption, there’s a gap between the security must-haves and the security nice-to-haves. Must-haves are the DoD, nuclear reactors, automotive and payment cards. Places where security is not negotiable, and liability is huge if you get it wrong. There’s a middle ground where the same probably applies but there’s no organizational or political will to invest in upgrades. For everything else, regulation may be the only path.

Me
I think an example attack would have helped. One I remember attacks a hardware root of trust (HRoT). Inside the HRoT, a master key is decrypted onto the HRoT data bus, then stored in a secure location. External access to the bus is disabled during this phase.

The HRoT then decrypts data for external access, while access to the internal bus is necessarily enabled. If enabled too soon, the key is still on the internal bus and can be read outside the HRoT. A small coding error exposes the key for a short time. Would this method have found such a bug?

On coverage, incremental improvement isn’t very compelling. I would like to see more discussion on how to determine that some class of penetration attacks could be prevented completely. Expert-defined coverage points don’t seem like the right place to start.

To see the next paper click HERE.

To see the previous paper click HERE.

February 10, 2020January 8, 2021

Emerging Requirements for Electromagnetic Crosstalk Analysis

Emerging Requirements for Electromagnetic Crosstalk Analysis
by Tom Dillinger on 02-10-2020 at 10:00 am
Categories: Ansys, Inc., EDA

This article will describe the motivations for pursuing a new flow in the SoC design methodology. This flow involves the extraction, evaluation, and analysis of a full electromagnetic coupling model for a complex SoC and its package environment. The results of this analysis highlight the impact of electromagnetic coupling on the performance and functionality of modern-day complex SOC designs.

Background
With the introduction of nanometer process scaling, the vertical-to-horizontal aspect ratio of interconnects increased above unity. As a result, the much larger contributions of capacitive crosstalk from a neighboring aggressor to a victim net necessitated new and improved SoC design flows. Noise analysis tools and corresponding IP characterization methods were developed to ensure that the (cumulative) energy injected into a (quiescent) victim net from its aggressors did not subsequently result in a circuit network failure. Algorithms for interconnect delay calculation used in static timing analysis flows were extended to reflect the noise impact on delay, due to the potential waveform modifications at the fanouts of a transitioning signal from concurrent transitions on aggressors.

EDA tools for physical implementation also incorporated new features. Specifically, detailed routing algorithms were extended to include restrictions on the parallel run length of adjacent interconnects. More sophisticated noise calculation/avoidance methods were incorporated to assist with wiring track selection.

Designers also quickly adopted techniques to further mitigate the risk of subsequent capacitive crosstalk noise failures. Specific non-default rules (NDR) for critical nets were coded, to guide implementation tools to use greater-than-minimum spacing between metal segments on a layer and/or to direct segments to a track adjacent to a non-switching (power/ground) net to effectively shield the segment from coupling transitions.

The limited extent of the capacitive electric field lines between metal segments was relatively easily incorporated into SoC physical design and electrical analysis flows, supported by (standards for) library cell output driver waveforms and input pin noise sensitivity models.

As SoC clock frequency targets increased and supply voltages were scaled in nanometer designs, the influence of the (self-)inductance of specific nets became more evident. Dynamic power/ground noise margin analysis methods incorporated extracted RLC models for the P/G grids, to which switching current sources were injected at cell locations. The slew rates of clock nets were analyzed with inductive elements, which presented additional impedance to the (harmonic) high-frequency content of clock driver transitions.

References [1] and [2] below describe a representative partial inductance extraction method for a collection of metal segments – partial inductance assumptions are used for a segment to mitigate the difficulty in defining the “full loop” current return paths. Reference [3] illustrates how clock signal distribution may be influenced.

Electromagnetic Modeling Requirements for Today’s SoC Designs
The complexity of modern SoC designs integrates an extremely diverse set of high-performance IP, with a corresponding increase in the potential for electromagnetic coupling between disparate physical blocks. The isolated (partial) inductance models for P/G grids and clock nets need to be extended to represent the potential mutual-inductance long-distance interaction between current loops on-chip.

The figure above illustrates the importance of modeling this physical coupling. Two “isolated” small loops in the layout are 1mm apart and when fully extracted and analyzed together, they are quite isolated with very weak coupling. The layout also contains a third larger ring 20mm x 25mm. When the RC effects of that third bigger ring are considered, there is a minimal impact on the isolation between the two coils. However, when full electromagnetic (EM) extraction (RLCk) and analysis are performed, the graph shows that the isolation between the two small loops is reduced by 30dB at 10GHz due to the additional EM coupling. Note that the third ring/loop is not physically adjacent to the two IP loops – full electromagnetic coupling differs from the short-range of electric-field capacitive crosstalk.

(Parenthetically, to prove that the EM coupling is from the 3rd loop, an additional analysis was done with the 3rd loop “cut” – the isolation returns to the 2 loop-only results, as depicted in the figure above.)

The surrounding structures on-chip that could contribute to electromagnetic coupling include a myriad of possibilities – e.g., P/G grids (with decoupling caps), seal rings, the bulk silicon substrate, redistribution layer metals on the package, etc.

So, why are SoC EM coupling issues emerging?

The figure above illustrates that the isolation between IP blocks is impacted primarily at very high frequencies. Consider current SoC designs where a multitude of serial transceiver signal lanes are packed together on the die – for example, these SerDes lanes could be transmitting PAM-4 56Gbps signals at 7GHz. A group of lanes would share a common VCO/PLL clock source – multiple groups would be integrated to provide the total required data bandwidth. (Each group could also have multiple VCO’s within, to span a greater range of transmit frequencies.) Electromagnetic coupling contributions between multiple SerDes lanes, their P/G networks, seal ring, and package structures could result in significantly increased clock jitter (at the frequency spectrum of interest), and thus an unacceptable bit error rate.

The topologies of today’s advanced packages are a critical part of the EM coupling model, as mentioned above. The redistribution and power delivery metals in 2.5D packages (with interposer) need to be included. The unique nature of multiple stacked, thinned die in 3D packages (face-to-back or face-to-face) also requires models for EM coupling.

EM Coupling Tools and Flows
The requirement for (high-performance) SoC teams to add EM coupling analysis to their sign-off methodology necessitates new tools/flows that can assist designers with the difficult task of EM model extraction and simulation.

I recently had the opportunity to chat with Yorgos Koutsoyannopoulos, Vice President of Engineering at ANSYS about the recent EM coupling tool/flow advances available.

“We divided the EM coupling analysis task into two flows.”, Yorgos indicated. “The end goal is to provide designers with detailed extracted RLCk models for all relevant structures in the design, annotated to a circuit-level model for time, frequency, noise SPICE simulations. Yet, the full-chip package data volume would be unmanageable, and a large percentage of the IP signals on the SoC would not be of interest. We have developed an assessment flow to help designers pinpoint the specific nets where a detailed EM coupling model simulation is warranted.”

“How is the full chip plus package model initially generated for evaluation?”, I asked.

Yorgos replied, “The focus on the assessment flow using the ANSYS Pharos tool is to evaluate the SoC metals, vias, dielectrics, and substrate model without the circuit level detail. Designers specify the (top-level) interconnect layers of interest, and a topological model is constructed. Ports are automatically added at the physical cut points. At this juncture, without the underlying circuits, there is no annotation of an extracted RLCk model – the chip need not be LVS clean. The analysis will span the SoC IP physical hierarchy, in order to detect larger loops. The goal is to find the interacting structures that warrant further, detailed simulation.”

“What feedback is provided to the designer?”, I asked.

“Pharos provides both general heat maps on the excised layout database for relative visual feedback, combined with the selection of nets/grids for subsequent simulation.”, Yorgos replied. “The excised model is evaluated at a range of frequencies (and increments) provided by the designer.”

“Even with the excised SoC model, this is still a tremendous amount of physical data – what kind of IT resources are required for this early assessment?”, I inquired.

“For example, for a 100mm**2 die with the top 5 metal layers selected, the heat map for each frequency point would take roughly 1-3 hours on a 64-core 1TB memory footprint server.”, Yorgos answered. (Not too bad, I thought.)

Yorgos continued, “Pharos utilizes the same interconnect technology file as other flows – dependencies such as the metal sheet resistivity as a function of linewidth and the process corner definitions are included. For die with package models, we are able to include the package stack-up definition and redistribution layers into a unified extracted model. We also have an advanced method for modeling the die substrate into an extremely accurate RC mesh network.”

Much like design methodologies were extended to support the impact of capacitive crosstalk, it is increasingly the case that high-performance SoC IP’s (potentially utilizing advanced packaging) will need to adopt methods for broad electromagnetic coupling analysis.

To learn more about electromagnetic coupling challenges, check out this ANSYS link. Additional references with an overview of electromagnetic coupling symptoms are provided below.

-chipguy

References

[1] Ruehli, A.E., “Inductance Calculations in a Complex IC Environment”, IBM Journal of Research and Development, p. 470-481, September 1972.

[2] White, et al., “FASTHENRY: A Multipole-Acclerated 3D Inductance Extraction Algorithm”, IEEE Transactions on Microwave Theory and Techniques, Vol. 42, No. 9, p. 1750-1758, September, 1994.

[3] Restle, P., and Deutsch, A., “Designing the best clock distribution network”, VLSI Circuits Symposium, p. 2-5, 1998.

[4] Raman, A., et al., “Electromagnetic Crosstalk Failures and Symptoms in SoC Designs”, 2017 18th International Workshop on Microprocessor and SoC Test and Verification, p. 39-43.

[5] Papadopoulos, P., et al., “Challenges and Trends in SoC Electromagnetic Crosstalk”, 2017 2nd International Verification and Security Workshop (IVSW), p. 63-69.

February 10, 2020March 31, 2020

It’s The Small Stuff That Gets You …

It’s The Small Stuff That Gets You …
by Mike Gianfagna on 02-10-2020 at 6:00 am
Categories: EDA, Siemens EDA

The last session I attended at DesignCon 2020 wasn’t a session at all. Rather it was an interactive discussion with Todd Westerhoff, product manager for electronic board systems at Mentor Graphics. Todd made some observations about the way high-performance PCBs are designed today and perhaps the way they should be designed. Todd has a long career in EDA and high-speed design, including a stint managing high-speed systems design at Cisco, so I was ready to listen carefully. As an aside, we spent some time discussing the birth of EDA and what it all (might) mean. That’s a story for another day.

Let’s start with the fundamental premise of Todd’s discussion – experts can instantly spot problems invisible to others. The experts in this case are the signal integrity design experts that we all wish we had more of. To make this point, Todd shared the image on the right. It’s a brain scan, and it clearly shows a problem. Do you see it? This would require a different kind of expert. If you think you know what’s happening in this picture, put it aside for now. We’ll discuss the answer later.

So, what’s the core issue we’re discussing? The following diagram that details the health of hardware design projects sums it up.

25% simply isn’t a good hit rate. What can be done about this? Ideas around this goal occupied the balance of my discussions with Todd. High performance PCB design is hard – signal integrity issues will kill your design if you’re not careful. There’s nothing really new in this statement, but let’s take a closer look at how the difficulty of these designs is manifested in the design flow.

In any given high-speed, high-performance PCB design, there are clearly areas of concern from a signal integrity perspective. The areas where crosstalk and coupling are likely to be an issue get close attention from the SI experts. There are a lot of tools and a lot of complexity in this part of the design process. The figure below is an example of how things stack up for a SerDes channel.

This is the risky part of the design, but this is NOT where the typical killer defect emerges. There are way too many expert eyeballs looking at this part for that to happen. Rather, it’s the rest of the design, the parts that go through traditional design reviews, that usually get you. The “small stuff” as Todd would say. There are always SI hotspots that are aren’t noticed and so these parts of the design get a level of scrutiny that is insufficient to see and fix the problem.

Todd posed the following solution: What if you could create an automated design review checking system? One that gives designers the capability to run first-order analysis themselves. One that automates and integrates analysis of things like crosstalk and DRC into existing design processes and one that can run overnight, providing the design team a “heat map” of issues to look at as a result of yesterday’s work. This started to make a lot of sense to me.

It turns out Mentor is beginning to work with customers to deploy such an automated design review system. The figure below shows what it looks like. Note the Mentor HyperLynx DRC tool is mentioned. It turns out Mentor has tools to cover the entire automated design review flow. Watch this work from Mentor, I think it has great promise to get that 25% hit rate much higher.

And by the way, regarding that brain scan, the problem area highlighted is an aneurysm. This is a real case, where the problem was identified early and repaired. If you got this right, there might be other job opportunities for you in addition to impossible chip/system design.

February 9, 2020July 6, 2020

The Tech Week that was February 3-7 2020

The Tech Week that was February 3-7 2020
by Mark Dyson on 02-09-2020 at 10:00 am
Categories: China, Semiconductor Services

In a week where the new coronavirus and it’s impact has dominated the news, here is my weekly summary of the key semiconductor and technology news from around the world that you should know but may have missed.

The new coronavirus in China and worldwide is already causing an impact for the electronics supply chain, potentially affecting everything from wafers and assembled parts as well as supplies of raw materials and consumables to non Chinese plants. Everybody is scrambling to get clarity on the current and future impact on the supply chain as many factories in China have either been running on reduced staff or have not restarted after the Chinese New Year yet due to the travel restrictions on their staff. Hopefully next week after the 10th once a lot of people are allowed to return to work there will be more clarity. However the impact is expected to last anything from 3 to 6 months with most experts saying best case it will take until the end of April for things to return to normal. In addition to the impact on the supply chain, many companies have put in place travel bans and many semiconductor events are being cancelled in SE Asia. SEMI has cancelled Semicon Korea in February and Semicon China in March due to the virus.

The EEtimes has an article with some advice on how to optimise your supply chain to have a resilient supply chain, to mitigate the risk from such outbreaks and natural disasters.

If you are not sure what companies are in Wuhan then here is a guide to some of the major high tech companies located in the region.

Taiwan foundry TSMC said this week at a investor conference that despite the outbreak of the new coronavirus in China, their Q1 sales forecast remains unchanged and said that production at it’s plants in Nanjing and Shanghai remain normal.

Similarly Taiwan foundry UMC also said it expects no impact on Q1 revenue from the virus but if the issue prolongs there could be some impact. UMC reported its best quarterly profit in one-and-a-half years, with revenue jumping to US$127million in Q4 2019, due to strong demand for computer and communications chips. Other Taiwanese companies have also come out to say they see the impact of the coronavirus was limited.

Qualcomm said in it’s investor conference that the new coronavirus in China poses a potential threat to the mobile phone industry with a possible impact on manufacturing and sales.

In other news.

In 2019 leading original equipment manufacturers reduced their semiconductor spend by 11.9% on average according to Gartner. Apple took the top rank from Samsung, driven by its success in wearable products, namely Apple Watch and AirPods. Huawei retained the third position, having performed well through 2019 despite the US-China trade war. Apart from the slowing economy part of the reason for the reduced spend was lower memory prices which allowed companies to reduce the memory expenditure form 45% of their total spend to 36%.

SEMI reported that worldwide silicon wafer area shipments decreased 7% in 2019 but revenue remained above US $11billion.

Whilst NAND and DRAM volume is expected to be one of the growth areas in 2020, the outlook for the memory pricing is expected to be flat or maybe even down for DRAM. Also due to the price pressure, there seems little incentive to transition to new memory options in 2020.

Reuters is reporting that the US will meet this month to discussing further curbing technology exports to China and Huawei. Talks between high level officials are currently scheduled for February 28th.

Lam Research has selected the Batu Kawan Industrial Park in Penang, Malaysia as the location for a new advanced technology production facility. The new facility will be 700,000-square-feet at the initial phase with the opportunity to expand in the future. Construction is expected to begin in early 2020, with the first shipments by 2021.

ON Semiconductor Corporation has announced it is exploring the sale of it’s manufacturing facility in Oudenaarde, Belgium.

Irish fabless semi-conductor company Decawave, has announced it will be acquired by Qorvo. The acquisition will advance market penetration of IR-UWB and enable broad global adoption of this transformational technology. Decawave specializes in precise location and connectivity applications, whilst Qorvo is a leading provider of innovative RF solutions that connect the world.

Skyworks reported Q4 revenue grew more than 8% sequentially to US$896 million driven by smartphone sales. This was down 7.8% on Q4 a year ago as skyworks has been impacted by the US ban on sales to Huawei.

Osram reported a return to profitability in fiscal Q1 which ended in December, with revenue growing 5.5% to US$971million due to significant recovery in its semiconductor business. Looking ahead to fiscal 2020, Osram’s Managing Board confirmed its existing forecast for revenue to be between minus and plus 3 percent compared to the previous year.

February 8, 2020August 31, 2020

Rest in Peace Randy Smith (1959-2020)

Rest in Peace Randy Smith (1959-2020)
by Daniel Nenni on 02-08-2020 at 8:00 pm
Categories: General
7 Comments

The semiconductor industry lost another good one last week, my friend, co-worker, and longtime SemiWiki contributor, Randy Smith. Randy published sixty blogs on SemiWiki over the last eight years that have been viewed more than a half million times. That is quite a digital legacy, absolutely.

Like myself, and many other semiconductor professionals out there, Randy was a start-up enthusiast. We both loved the challenge, thrill, and rewards they promised. It’s a roller coaster ride for sure but definitely better than riding a carousel for 35 years.

Randy began his career in Silicon Valley in 1984. He started with Tangent Systems (TANCELL) which was then acquired by Cadence. Ten years later he joined Silicon Architects, followed by Silicon Valley Research, Gambit Automated Design, Artisan Components, TriMedia Technologies, Celestry Design Automation, Aprio Technologies, Sonics Inc, and consulted for many others.

Randy was also well traveled. It was really funny walking through a Tokyo subway and hearing Randy’s laugh before seeing him. Running into friends halfway around the world is a memorable experience. We also traveled together, the one I remember most was a trip to Russia. It was our first time traveling there and I remember him devouring Russian history books on the plane while I was struggling with Harry Potter. Once there, Randy was the best tour guide I have ever had. Seriously, he could consume an incredible amount of information in the shortest amount of time and replay it back so mere mortals like me could understand it.

Randy was also a talented musician and dedicated family man. Many times I was told he was not available due to family commitments and I greatly respected that. Unfortunately, he passed away while experiencing some serious financial challenges that his wife Anne must now sort out. For those of you who knew Randy or even if you didn’t and would like to help there is a gofundme page to help his family in this time of need.

February 7, 2020July 6, 2020

Good December but March variable due to Coronavirus

Good December but March variable due to Coronavirus
by Robert Maire on 02-07-2020 at 10:00 am
Categories: China, Semiconductor Advisors, Semiconductor Services

Trend remains positive for 2020 overall
New tools & EUV suggest better growth in 2020
Calendar 2019 ends on strong foundry note

KLAC reported revenues of $1.509B and EPS of $2.66 NonGAAP versus street of $1.48B and $2.58. Foundry (TSMC) was obviously the big driver of the quarter and into 2020 as well. Memory remains subdued though strengthening.

Wide Guide range due to Corona uncertainty
Managment was talking about a 3% to 5% haircut due to the Corona Virus in China but how that settles out seems very variable which resulted in a very wide guidance range depending upon the unknowable impact in the quarter. Guidance is for revenues from $1.325B to $1.525B and EPS from $2.04 to $2.82 versus street of $1.42B and EPS of $2.45, which is now in the exact middle of the wide guidance range.

The company is obviously usually much more of a very predictable performer so the wide range is a bit unsettling.

New tools and EUV add to 2020 outlook
Aside from the Orbotech acquisition KLA has new 5G and E Beam tools that will add to the upside potential in 2020. Obviously the move to EUV means more and better metrology which will certainly help KLAC.

In addition the company still expects an up year for China which has been its biggest growth market for a while now, this is despite the air pocket in the first half of 2020 from Corona.

Corona Light or Corona Heavy?
Its still too early to tell if the Corona fallout is primarily limited to Q1 or if the problems extend into Q2 or beyond.

Recently SEMI the semiconductor equipment trade organization canceled the Semicon China show scheduled for March and canceled the Semicon Korea show scheduled to start today.

While not a lot of orders are placed on the show floor any more it does underscore how business has ground to a virtual halt.

In our view, we think the impact will likely be on the heavy side and will likely extend into the second quarter given the rapidity of the spread of both the virus and more importantly the hysteria about it.

We would not be surprised if China’s semiconductor equipment purchases finally wind up being flat versus 2019.

While the current outbreak can be compared to other previous natural disasters the strength and momentum seems to be higher along with the heightened response.

Memory remains uncertain with DRAM still further out
While KLA is more of a poster child for foundry/logic, they still none the less sell a lot to the memory industry. We would be happier if we saw a stronger uptick in memory or a more broad based up tick that included DRAM.

We remain concerned that the strong buying season from TSMC will fade as they move into 5NM production for Apple’s fall release and that memory spend may not be enough to pick up the slack of slowing foundry/logic. Even though foundry/logic may be up for the year it is likely first half weighted.

The stocks are not helped by uncertainty
Uncertainty means risk and more risk means lower valuations. We saw this this as KLAC was up 5% during the trading day then gave it all back in the after market likely due to the wide guide range and Corona uncertainty hitting the stock.

We will likely see a bit of retrenchment here as the uncertainty takes its toll on a stock that has been on fire of late, which likely makes it even more vulnerable to a pull back.

Like many other things “this too shall pass”, but not before creating some problems.

Lam last week was not as conservative as KLAC about Corona’s impact but then again they have historically had much less exposure and history with China as compared to KLAC.

Given that Applied will report a month deeper into the Corona crisis, they will likely have a more up to date idea and they also have perhaps the longest history of doing business in China.

As a group, we think the overall semiconductor industry is vulnerable especially given the stock run ups in front of this uncertainty

We are not highly motivated to buy the stocks in the middle of all the news flows especially given that there aren’t any attractive values left. We prefer to watch the hysteria from the safety of the sidelines.

February 7, 2020January 12, 2021

AI Interposer Power Modeling and HBM Power Noise Prediction Studies

AI Interposer Power Modeling and HBM Power Noise Prediction Studies
by Mike Gianfagna on 02-07-2020 at 6:00 am
Categories: AI, Cadence, EDA, Events

I attended a session on 2.5D silicon interposer analysis at DesignCon 2020. Like many presentations at this show, ecosystem collaboration was a focus. In this session, Jinsong Hu (principal application engineer at Cadence) and Yongsong He (senior staff engineer at Enflame Tech) presented approaches for interposer power modeling and HBM power noise prediction. The application was AI-focused, but the modeling approaches presented have broad applicability.

First, a bit about Enflame Tech. They are a startup with R&D centers in Shanghai and Beijing, China. They are developing AI-training platform solutions, including deep learning accelerator SoCs, PCIe boards and a software stack, targeting cloud service providers and data centers.

Since this design is focused on AI training, there is a 8-hi HBM2 memory stack on board to store the training data. An ASIC is integrated with the HBM2 through a silicon interposer. The ASIC contains a single integrated hard macro PHY that has eight independent channels with a total DQ width of 1,024, and the total number of signals is 3,300+. The figure below illustrates the overall package.

Two critical elements of this project are the design and simulation of the interposer. With regard to signal integrity, the wire length between the HBM and PHY is carefully chosen, as longer lengths need stronger drivers. High-speed signals are routed on M1/M3, with the shielding layer on M2. All signal routing is designed with a wire length difference of ±0.15%. The optimized physical configuration includes the signal width, trace spacing and shielding pattern, as shown below.

The AI chip has lots of HBM dies to do parallel calculations, and due to the significant scale of the micro-bump and C4 bump, it provides a level of modeling difficulties for both physical design and simulation engineers. With regard to power modeling of the complete interposer design, the Cadence Cadence Sigrity XcitePI Extraction tool was used to extract the SPICE netlist model. Model post-processing can be performed to validate the Z-impedance, IR drop and time-domain power ripples, as shown below.

Power noise was critical to ensure the stability of the HBM bus, and it was also challenging for the current tools to handle the tremendous HBM nets’ system signal and power simulation at the same time. The DesignCon presentation proposed two innovative methodologies to predict HBM power noise, using the Cadence Sigrity SystemSI and System Explorer tools for system time-domain simulation. The voltage multiplying method and the current-induced method were used for further power noise predictions, and the figure below illustrates a typical scenario. (Note that the acronym “CMF” means “current multiplying factor”.)

The benchmark measurements were performed by a test chip mounted on a reference board, and the measurement result showed that simulation predictions can correlate quite well with the predicted data.

Lab measurement setup with test board

Simulated results with current-induced method

Measured results from lab

Above all, these power modeling and noise prediction techniques may have broad applicability to many different types of 2.5D HBM-based silicon interposer designs.