SemiWiki – Page 304 – The Open Forum for Semiconductor Professionals

RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)

June 17, 2021April 20, 2022

Alchip is Painting a Bright Future for the ASIC Market

I’ve spent most of my career in the ASIC business. In 2003, Gartner predicted the ASIC market would grow to $16.9B. During that time, there were a number of startups building ASICs, but the applications were a bit specialized and aimed at new markets. Consequently, there was a lot of risk to build a chip startup and many ASICs either never made it to tapeout or a perfectly good chip never found the market it was looking for. The massive cloud buildout, seemingly infinite hunger for bandwidth and the AI revolution has changed all that. Semiconductors, ASICs and even EDA are now topics that have found mainstream interest. Even the US Government seemed to have noticed. It actually feels fulfilling at some level that the rather obscure career in ASICs and EDA that I’ve pursued for my entire adult life is now of mainstream interest. A recent upbeat press release from Alchip made me smile. Alchip is painting a bright future for the ASIC market, and this kind of news feels great.

Alchip is a global provider of silicon design and production services in mainstream and advanced processes, including 7nm. The company is traded on the Taiwan and Luxembourg stock exchanges. It is headquartered in Taipei, with operations in Europe, North America, Japan, Korea, and China. Alchip is the real deal when it comes to a focused, dedicated ASIC supplier. You can find out more about Alchip on their SemiWiki page. The press release details comments recently made by James Huang, vice president, Alchip Technologies to industry executives. Mr. Huang has worked at Alchip for over 18 years, so he certainly knows something about the ASIC business.

In a presentation to industry executives, Mr. Huang pegged 2026 ASIC sales at $20 billion, up from what most analysts are pegging as a $10 billion market this year and reflecting the high-end of an anticipated 12% to 15% compound annual growth rate (CAGR). He went on to say that devices headed into networking applications will account for 45% of this year’s total market, while storage applications account for 35% and compute acceleration applications will account for the remaining 20 % of total, or $10 billion total available market (TAM). Mr. Huang estimated that North America represents the largest geographic market, while the pan-Asian region could experience the largest growth.

Mr. Huang went on to discuss the technologies that will drive this growth. Advances in heterogeneous packaging technology will be a critical piece. He explained that current 2.5D and emerging 3D packaging technology that bundles multiple “chiplets” that perform different functions would lead the charge. Mr. Huang reported that, according to Mordor Intelligence, 2.5D/3D ASICs will grow at a 35.3% CAGR between 2020 and 2025. This is spectacular growth. I am observing many of the same trends as Mr. Huang. In my view, the slowing of Moore’s Law has driven a new technology revolution around hyper-convergent design – the combination of multiple chips/chiplets and multiple technologies in a highly complex and sophisticated package.

Mr Huang predicted: “The ‘next-gen’ device that will lead industry growth will little resemble the current market leaders. They’ll be built on advanced processing technologies, at or below 3nm. Rather than a single IC, they will be integrated multi-chiplet devices in advanced 2.5D/3D CoWoS or InFO packages. They’ll will be high-power and high-frequency running at more than 400 Watts.”

Mr. Huang also provided a cautionary statement. The exponential leap in market size and functionality will require design capabilities significantly more robust than what is required today. Devices with billions of gates will require design resource investments that will represent an increase of three-to-four times, depending on complexity. As a long-time fan and participant in the EDA industry this made me smile.

Johnny Shen, president and CEO of Alchip also weighed in. “The ASIC company of tomorrow will be a very advanced technology organization. It will require a robust design methodology, flexible business model, best-in-class IP portfolio and advanced packaging technology expertise. This, as a matter of fact is the model upon which Alchip is being built today.” Having spent about half my career in the ASIC business, I couldn’t agree more with Mr. Shen. The ASIC business is NOT for wimps.

Alchip reveniue by technology node

To complete the picture, Alchip recently reported that advanced technology 12/7nm designs accounted for nearly 60% of the company’s first quarter revenue. They also showed a significant growth in these types of designs over the past three years. So, there’s on ASIC supplier’s view of the future. Alchip is painting a bright future for the ASIC market, and I believe this will be an inspiration to others.

Also Read:

Maximizing ASIC Performance through Post-GDSII Backend Services

Alchip at TSMC OIP – Reticle Size Design and Chiplet Capabilities

Alchip moves from TSMC 7nm to 5nm!

June 17, 2021November 21, 2022

Ferroelectric Hafnia-based Materials for Neuromorphic ICs

Ferroelectric Hafnia-based Materials for Neuromorphic ICs
by Raisul Islam on 06-17-2021 at 6:00 am
Categories: EMD Electronics, Intermolecular, Semiconductor Services
1 Comment

The ferroelectric effect in materials has been exploited to fabricate (fab) reliable Ferroelectric Random Access Memories (FRAM) Non-Volatile Memory (NVM) ICs for over 20 years. Recent years have seen have seen a breakthrough in discovering ferroelectric properties in Hafnium Oxide (HfO₂ or “hafnia”), a fab-friendly material unlike previous perovskite-based materials like Lead Zirconate Titanate (PZT). This has the potential to revolutionize on-chip memory technology and to enable next-generation technologies such as artificial synapses for compute-in-memory (CIM) type neuromorphic ICs.

Crystals are ordered solids, as opposed to amorphous solids like glasses and plastics. The characteristics of a crystal–electrical, mechanical, optical, etc.–change when atoms line up to form interlocking grids, and many materials can solidify into different crystal forms. Pure carbon can be structured to be conducting soft dark graphite or insulating hard transparent diamond. Some complex crystals have polar atoms spaced so that a switching external electric field causes an internal shift of some atoms in the crystal lattice. This creates an electrical charge dipole giving rise to ferroelectric effects as shown in Figure 1.

FIGURE 1: Ferroelectric effect in “orthorhombic Pca21” HfO2 crystals from movement of oxygen atoms (red) between 2 positions in lattice of hafnium atoms (grey). (Source: “Graphene bandgap induced by ferroelectric HfO2 substrate: a first-principles study,” Nemnes et al., Phys. Chem. Chem. Phys., 2019,21, 15001-15006)

PZT while used in ferroelectric memory devices is not fab friendly, and loses its ferroelectric properties when layers are very thin. Hafnia has been used as the storage capacitor in Dynamic RAM (DRAM) and as the gate dielectric in Logic ICs for many years due to its high dielectric constant and can maintain ferroelectric properties when ultra-thin. Typically, the ferroelectric phase of HfO2 is unstable. To stabilize the FE phase in HfO2, Zirconium (Zr) dopant has proven to be the most successful. As such, Hafnium Zirconium Oxide (HZO) has been one of the strongest FE material candidates for memory applications. Besides Zr, other dopants such as La, Y, Si, Gd have also been explored.

Material Deposition
Ferroelectric perovskites currently are deposited by sol-gel method or physical sputtering. However, these require high temperature anneals to achieve the ferroelectric crystal structure, but CMOS backend of line (BEOL) integration has a limited thermal budget of ~400°C. To achieve well controlled ultra-thin films in small, high density devices, advanced commercial IC fabrication relies upon atomic-layer deposition (ALD), specialty cleaning and surface treatments to ensure that all atoms line up where needed. Underlayers are prepared and cleaned to create optimal reaction surfaces. Then special ALD organometallic precursors are used to deposit desired materials one monolayers at a time.

ALD film composition and processes must be controlled to achieve the desired crystal orientation and inhibit the growth of all other thermodynamically possible orientations. Some precursors can deposit hafnia-based films with ferroelectric properties https://bit.ly/34AEFoJ but this is not always the case. With the right surface and the right process conditions, exposed surface atoms can provide a “template” to support the growth of the desired crystal orientation. The ferroelectric properties of HZO can also be improved by interface engineering, such as forming nanolaminates with distinct layers of HfO₂ and ZrO₂https://bit.ly/3wLF0Rt). Rapid Thermal Anneal (RTA) can also drive the transformation to the ferroelectric phase.

Design and Reliability Considerations for Ferroelectric Memory
Ferroelectric memories can be three types, (i) FeRAM – a one transistor – one capacitor type device where the information is stored by modulating polarization capacitance, (ii) FeFET – a transistor with ferroelectric material as a gate dielectric where the threshold voltage is modulated based on the polarization, (iii) FTJ – a tunnel junction that stores information by modulating the tunnel barrier based on the orientation of the electric dipole polarization. FeRAM and FeFET historically have been more popular. Nevertheless, FeRAMs have destructive read process, and FeFETs are three terminal devices where the cycling endurance is critically dependent on the gate dielectric/semiconductor interface. Most importantly, neither of these is a resistive switching device that is essential for realizing synaptic devices for some neuromorphic computing architectures.

FIGURE 2: (left) Sketch of brain neurons connected by a synapse and artificial synapse based on hafnium-zirconium-oxide (HZO) ferroelectric tunnel junction (FTJ), and (right) Spike-Timing Dependent Plasticity (STDP) curves for an HZO FTJ showing hysteresis curves that can encode analog levels of “learning”. (Source: ACS Appl. Electron. Mater. 2020, 2, 12, 4023–4033)

Neuromorphic computing can be broadly classified into two categories, (i) ones that aim to actively emulate human learning processes and behavior and (ii) ones that emulate the connectivity and information flow of the brain through artificial neural networks (ANN), but do not necessarily emulate human learning processes. One common embodiment of the former category is Spike-Timing Dependent Plasticity (STDP) that changes the weight of the synapse based on timing differences between the arrival of pre- and post-synaptic signals (See Fig. 2). In hardware implementations, the weight changes are stored in non-volatile memory devices like FTJ. ANN type computing is pervasive because it can be implemented in a CMOS hardware platform, and it has a flexible design methodology. Typical CMOS hardware is not adequate for storing and accessing the number of synaptic weights that are required for the state-of-the-art neural network models that rely on off-chip memory. Hence, a cross-bar array of analog non-volatile memory is used to enable CIM architecture which encodes the matrix-vector multiplication, a key component of both ANN learning and inference. [See Fig. 3].

Fig. 3 (a) Single layer perceptron with four inputs and two outputs. (b) General computational form for single layer ANN. (c) NVM crossbar array for realizing the matrix-vector multiplication shown in (b). Here, T = transistor, S = selector, R = resistor. (Source: Raisul Islam et al 2019 J. Phys. D: Appl. Phys. 52 113001)

FTJs with hafnia materials have the potential of becoming an ultra-low power memory for the CIM architecture, compatible with CMOS BEOL integration. A key remaining challenge is to maintain analog switching behavior as the FE domains get smaller with scaling. ALD deposition of inherently FE films can solve this problem by demonstrating FE behavior in ultra-thin films.

Just as thick PZT layers provide a foundation for reliable digital FRAM, thin HZO ferroelectric layers provide a foundation for ultra-low-power analog neuromorphic ICs. HZO monolayers hold information at the atomic level as artificial synapses to enable Artificial Intelligence (AI) and Machine Learning (ML) circuits as well as new Compute-In-Memory (CIM) architectures. HZO-based devices use “fab-friendly” materials such as TiN electrodes for low-cost and easy integration, enabling future cost-effective commercial fabrication of high-yielding neuromorphic chips.

Also Read:

Webinar: Rapid Exploration of Advanced Materials (for Ferroelectric Memory)

Executive Interview: Casper van Oosten of Intermolecular, Inc.

Integrating Materials Solutions with Alex Yoon of Intermolecular

June 16, 2021August 22, 2024

Silicon Photonics Solutions Address Bandwidth, Reach, and Power Challenges

Silicon Photonics Solutions Address Bandwidth, Reach, and Power Challenges
by Kalar Rajendiran on 06-16-2021 at 10:00 am
Categories: Events, Foundries, GlobalFoundries

A couple of weeks ago, I blogged on GlobalFoundries’ silicon technologies supporting automotive radar applications. This time it is on GlobalFoundries’ silicon photonics technology which expects to find adoption in a broad spectrum of applications. The blog is based on listening to a technology presentation made by Dr. Anthony Yu, VP Computing and Wired Infrastructure, GlobalFoundries, Inc. at Linley’s Spring Processor Conference. His presentation was titled “Silicon Photonics Solutions Address Bandwidth, Reach, and Power Challenges” and is from a foundry’s perspective for enabling silicon photonics adoption on a large scale.

Silicon Photonics is the use of lasers for transferring data at high speeds among computer chips. In other words, it is optical I/O for rapid transmission of data. As a technology, it has been around for quite some time. But it hasn’t gained mass adoption yet. Does that mean it will remain so forever? Or is it in waiting for the right time and killer applications to get popularized? History tells us never to write off promising technologies.

Some technologies that are ubiquitous today had rough starts. It may be hard to believe that the now pervasive blue tooth technology had a few hiccups before it found widespread use. And so did the venerable USB technology. It is ironic that USB was initially popularized by Apple. Remember that Apple was pushing a competing technology in the form of FireWire. But the success of iMac that included USB ports set the course for rapid broad adoption of USB.

And who can forget the famous tagline, “The Network is the Computer” coined back in the mid-1980s. That was a time when networking communications was at a nascent stage. Cisco was in its infancy. But Sun Microsystems recognized that networking was the future of computing and coined this tagline. And made strategic decisions accordingly. They took the risk of incorporating SerDes technology in their workstation ASICs for implementing high speed I/O. Their competitor Silicon Graphics took a different route, at least in the earlier days by going broad on their chip I/Os. They soon ran into I/O bound chips that made the die larger than needed. They solved this issue by adopting flip-chip technology. Both SerDes technology and Flip-chip technology were not new at that time but needed the boost from some companies/products to proliferate into broad and rapid adoption across the industry.

Of late, due to a number of factors, silicon photonics solutions seem closer to wide adoption than ever before. The factors being, slowing down of Moore’s law, rapid increase in chip development costs, reduced die yield rates in very advanced process nodes, etc., This is pushing chiplets-based implementation as an alternative to monolithic system-on-a-chip (SoC) necessitating lots of high-speed connectivity between the different chiplets that make up the system. Silicon photonics may be one way to implement these interconnects.

Applications and Trends Pushing Silicon Photonics Toward Broader Adoption

Three major trends of frictionless networking, virtualization and hierarchical AI accelerated during the first twelve months of the covid pandemic period. The applications behind these trends appear to be the ones that are likely to tap into silicon photonics solutions (refer to Figure 1). There are three reasons to believe the adoption will happen soon.

Heterogenous integration with optical interconnects becoming a serious alternative due to the fact that lithographic scaling is slowing down (Moore’s law slowing)
Explosive growth of data (in zettabytes) due to proliferation of mobile applications
Enormous consumption of electricity raising an existential threat flag. It is projected that if the growth of machine learning/artificial intelligence driven applications keeps up at the same rate as during the last year, they are expected to consume an amount equal to all electrical energy consumed today

Figure 1:

Markets that are currently being served by Silicon Photonics are the 100m to 10km data haul connectors of data centers, the 5G and the telecom markets. For the next wave of broader adoption, co-packaged optics is going to play a catalyzing role. Co-packaged optics means bringing the optics (which is typically in a face plate) very close to the ASIC (refer to Figure 2).

Figure 2:

GlobalFoundries’ Technology

Historically, photonics industry has been working with hybrid silicon technologies such as indium phosphide. GlobalFoundries has established large scale CMOS-based foundry capacity to successfully manufacture photonics IC and optical components without special processing steps and additional associated costs. Although this approach is not a match for the indium phosphide approach, the benefits far outweigh the drawbacks (Refer Figure 3).

Figure 3:

In addition to offering the cost-effective manufacturability benefit, GlobalFoundries is offering some differentiating technologies for OSAT players to accelerate development of standardized packaging for implementing co-packaged optics. These are copper pillars, copper receive pads, on-die laser attach and v-groove based fiber attach technologies.

Summary

Dr. Yu’s presentation explored areas for broader adoption of Silicon Photonics through an approach of integrating complex CMOS and optical component functionality into a single photonic integrated circuit. If interested in benefitting from a silicon photonics solution, I recommend you register and listen to Dr. Yu’s entire talk and then discuss with GlobalFoundries on ways to leverage their different offerings for developing your products.

Also Read:

Enabling Silicon Technologies to Address Automotive Radar Trends and Requirements

Machine Learning Applied to Increase Fab Yield

Foundry Fantasy- Deja Vu or IDM 2?

June 16, 2021March 16, 2022

Connecting System Design to the Enterprise

Connecting System Design to the Enterprise
by Bernard Murphy on 06-16-2021 at 6:00 am
Categories: Cadence, EDA

While systems design underpins the explosion in “smart everything”, it remains somewhat isolated from another explosion—the proliferation of tools for application lifecycle management (ALM). ALM tools are prevalent on the web, in the cloud and on our phones, to streamline product design and build, to track correspondence between requirements and design/test, customer relationship management and much more. Collectively this market is already well over $50B annually and growing fast because it centralizes and automates what matters to a business. Technology enterprises are already active in using these tools in program and requirements management. Software enterprises are now connecting these important applications to development and engineering operations (DevOps). Semiconductor enterprises are also starting to leverage this DevOps connection, thanks to an important boost from Cadence.

Why do we need this? First, to manage traceability

This all sounds like general goodness, but no one is going change the way they work for a nice-to-have capability. What is now motivating a switch, according to Matt Graham, product engineering director at Cadence, is increasing challenges in supporting traceability. You probably know of this expectation from ISO 26262 and other standards for mission-critical domains. Being able to trace from a requirement to design implementation and to the testing, which demonstrates correctness per the requirement.

The default way to handle this objective is through a requirements traceability matrix (RTM), typically a spreadsheet which correlates between multiple documents, such as a technical requirements doc and perhaps a business requirements doc. Connecting to an implementation plan and most importantly here, a test plan, both with status details. This exercise ensures that everything defined in requirements is implemented and tested. If the link is bidirectional, you can also verify that nothing has been added in implementation and test that wasn’t required.

This method is labor-intensive and error-prone. It obviously doesn’t scale well as more items are added, and it doesn’t age well. As a design progresses through late-stage changes and into derivatives, RTM accuracy deteriorates quickly. Also RTMs undermine agility. Sprints and iterative regressions all screech to a halt on manual matrix updates.

Connecting traceability to the verification plan

There’s no doubt that teams have built a lot of scriptware to automate parts of this update, but that path, too, has limitations. Which requirements management system(s) should you support—Doors, Jama, Jira? And which do your partners and customers support? A standard like ReqIF can help but that is mostly used for the unidirectional exchange between partners, making it difficult to leverage this path to add in-house value.

Cadence and OpsHub have partnered for several years now to build connections between the vManager Verification Management platform to meet objectives like requirements management. Objectives typically managed outside the immediate verification domain. Matt told me that about 18 months ago, this activity around traceability really picked up. (And he noticed more activity around bug tracking and revision control). The need to plug into industry-leading DevOps platforms and enabling bi-directional communication proved the value of this partnership. Stakeholders get timely information and updates, each in the tools and formats they want to see. Automation ensures there are no limits on scalability, granularity or currency of data.

OpsHub has been supporting software DevOps teams for many years, including several big banks and financial institutions. Jama Software is a partner and counts an impressive roster of semiconductor companies among their clients. Especially for requirements change management and reviews.

A big step along a longer road

This linkage can only benefit semiconductor development teams, their program management teams and their customers. By offering better support for all stakeholders through improved tie-offs between input requirements, status and delivery. Next, there are plenty more connections to make. OpsHub currently supports many other platforms including Atlassian Jira, Jama Connect, IBM Doors, Azure DevOps, Salesforce, PTC and multiple Broadcom products. I can’t wait to see what other enterprise-level functions start connecting to design.

You can learn more about OpsHub’s support for vManager HERE. You can learn more about vManager HERE.

Also Read

Keynote from Google at CadenceLIVE Americas 2021

Cadence adds a new Fast SPICE Circuit Simulator

Fuzzing to Validate SoC Security. Innovation in Verification

June 15, 2021June 30, 2021

“Kandou it”

“Kandou it”
by Lauro Rizzatti on 06-15-2021 at 10:00 am
Categories: IP

In another departure from my chip design verification “beat,” I took a look at Kandou and like what I learned.

Kandou from Lausanne, Switzerland, boasts “Kandou It” as its tagline and as it should be if Kandou’s USB-C multi-protocol retimer solution with USB4 support is inside next-gen laptops, notebooks, desktops, tablets and workstations unveiled at CES 2022.

Its recent news touts availability of production silicon samples of KB8001, the first product from the Kandou Matterhorn family of USB-C multiprotocol retimer solutions with USB4 support. That follows an earlier announcement that Kandou was developing a retimer solution.

Kandou also claims the Matterhorn family is the only commercially available USB4 retimer to work across all SoC platforms. (Hint: The only other currently available USB4 retimer comes from a large company in Santa Clara, Calif.)

Retimers are becoming a bigger deal these days. USB-C is used now in most electronics devices and retimers will be needed for many of USB-C’s USB4 high-performance applications, including those with SSD drives.

That’s why consumers, especially tech-savvy readers of Semiwiki, should be delighted with Kandou’s news. Your next-gen desktop, laptop or tablet will support faster data transfer between USB4-connected devices and higher resolution displays with lower power consumption if Kandou is inside the system.

Reading the news release, I learned KB8001 follows the USB-IF specification for USB4 and supports long-reach with no compromise on signal integrity, giving engineers greater flexibility for chip placement in their system designs. Of note, the retimer solution can be located up to approximately 16 inches (or 40 centimeters) away from the main host SoC using low-cost PCB materials with no compromise on signal integrity. One retimer manages signal reconditioning and larger trace loads and offers flexible placement for larger laptops and desktops. Kandou’s “no regret” design delivers reduced overall system and development costs, eliminating the need for balancing the compromises that redrivers bring.

Matterhorn’s architecture enables support for various source and sink orientation options. It also supports multiple protocols: USB4 Gen2 and Gen3 signaling at 20 and 40Gbps; USB 3.2 Gen 1 and Gen 2 Super Speed signaling at 5 and 10 Gbps; DisplayPort 1.4a at 8.1, 5.4, 2.7 and 1.62 Gbps x1, x2, x4; Thunderbolt 2 and 3 at 20.625 and 10.3125 Gbps. Matterhorn complies with relevant standards and is interoperable with leading hosts and devices utilizing USB4, Thunderbolt, USB3.2 and DisplayPort functionality.

As I continued reading the news release, I learned BOM costs are lower due to the lack of external serial memory required for retimer parameters, integrated DC blocking capacitors, and integrated pull-up and pull-down resistors on low-speed wires. The Autonomous Rx Equalization (ARxE) dynamically corrects for extreme channel characteristics providing a hardware- and software-independent solution that goes beyond the current USB-IF standards. On-chip diagnostics including Eye Scope functionality support easy debug during development and end-of-line testing for assured product quality.

The KB8001 chip has been thoroughly tested to verify interoperability with leading hosts and devices utilizing USB4, Thunderbolt, USB3.2 and DisplayPort functionality.

Kandou got started in 2011 developing IP and now has an extensive IP portfolio that’s licensed and shipping in volume since 2019. More impressive is its 360 patents (and growing) related to unique and improved chip-to-chip signaling techniques. That IP success prompted Kandou to expand its business model to include fabless chip development, the first chip being the Matterhorn KB8001 retimer. Its expertise in high-performance, low-power SerDes design enabled Kandou to address stringent requirements of the USB4 standard. Oh yes, the total available market for USB4 retimers could exceed $1 billion.

Dr. Amin Shokrollahi is Kandou’s founder and CEO. His journey from genius math wizard to academic to semiconductor entrepreneur is a standalone blog post I’ll save for another time. I’ll leave you with a tantalizing tidbit about Amin: He studied the problem of transmitting data on electrical wires and solved it using mathematics, not our traditional electrical engineering solutions, knowing math could make the difference.

From my perspective, Kandou is a semiconductor company to watch because it “Kandou it.”

Visit the Kandou website to learn more.

June 15, 2021June 17, 2021

Highlights of the TSMC Technology Symposium 2021 – Automotive

Highlights of the TSMC Technology Symposium 2021 – Automotive
by Tom Dillinger on 06-15-2021 at 6:00 am
Categories: Automotive, Events, Foundries, TSMC
1 Comment

At the recent TSMC Technology Symposium, TSMC provided a detailed discussion of their development roadmaps. Previous articles have reviewed the highlights of silicon process and packaging technologies. The automotive platform received considerable emphasis at the Symposium – this article specifically focuses on the automotive-related announcements.

As illustrated below, the forecasts of semiconductor content in automotive designs show considerable and extended growth.

Advanced driver assistance systems (Level 4/5 autonomy) will experience high adoption in upcoming models, with extensive sensor integration, requiring significant increases in computational throughput for image processing and decision control.

TSMC described a number of process technology enhancements, ranging from high-voltage power management to microcontroller functionality to image sensors to (5G) wireless vehicle communication to advanced digital performance, all specifically for the “automotive grade” environment.

Review of Automotive Grades

The demanding and varied applications for the electronic control units and sensors in an automotive system necessitate specific definitions of environmental and reliability qualification specifications – in short, these are represented as different grades. AEC-Q100 is an industry standard specification that defines the specific qualification procedures:

- AEC-Q100 Grades
  - - Grade 0: -40C to 150C (automotive, under the hood)
    - Grade 1: -40C to 125C (automotive)
    - Grade 2: -40C to 105C (industrial)
    - Grade 3: -40C to 85C (commercial)

BCD Technologies for Automotive

TSMC offers multiple families of BCD (Bipolar-CMOS-DMOS) technologies, in support of the different high-voltage domains within an automotive network, as illustrated below.

Continuing generational enhancements focus on reducing device on-resistance (Ron), to improve PMIC efficiency.

Embedded NVMs for automotive MCUs

Microcontrollers in automotive ECUs require embedded non-volatile memory blocks, for over-the-air (OTA) maintenance/feature updates. As the complexity of automotive electronic systems grows, MCUs will trend to newer process nodes for better PPA, and will require dense, high-reliability eNVM technology.

Key aspects of the eNVM reliability are the endurance cycle and data retention performance. The eNVM roadmap for the TSMC automotive platform is shown below.

At the N28 node, embedded flash memory is being qualified for Grade 0. Beyond the N28 node, magnetoresistive random access memory (MRAM) technology will be displacing eFlash. N22 MRAM is in high-volume production (Grade 1, 100K cycles, 10 years retention, and high-immunity to external magnetic field). N16 MRAM will be (Grade 1) qualified in 4Q22.

N5A

To address the computational requirement of (Level 4/5) data processing, TSMC is extending the production N5 process node to Grade 2 automotive qualification in 2022.

This N5A platform offering involves extending the design enablement support to Grade 2, from PDK models to TSMC library IP to aging/EM reliability analyses. Correspondingly, the TSMC OIP partners are working on extending their IP support to N5A, as well.

With regards to IP, the automotive platform is also required to demonstrate functional and electrical model quality plus safety features, through compliance with the ISO26262 standard, adhering to Automotive Safety Integrity Level (ASIL) specifications.

Clearly, the automotive platform is receiving significant R&D investment at TSMC, in anticipation of extended growth in the semiconductor MCU and sensor content in upcoming years. Increasing ADAS adoption and sales of EVs are driving a broad set of technology requirements, from PMICs to 5G RF wireless to high-end digital computation.

For more info on TSMC’s automotive platform, please follow this link.

-chipguy

June 14, 2021March 16, 2022

Keynote from Google at CadenceLIVE Americas 2021

Keynote from Google at CadenceLIVE Americas 2021
by Kalar Rajendiran on 06-14-2021 at 10:00 am
Categories: Cadence, EDA

Last week, Cadence hosted its annual CadenceLIVE Americas 2021 conference. Four keynotes and eighty-three different talks on various topics were presented. The talks were delivered by Cadence, its customers and partners.

One of the keynotes was from Partha Ranganathan, VP and Engineering Fellow from Google. His talk was titled, “May I have More Moore Please? Thinking Outside the Traditional Hardware Box.” Glancing at the agenda ahead of the conference, the “More Moore” part of the title caught my attention. For many decades, Moore’s law was doubling performance of devices and reducing costs every two years or so. Over the recent past, Moore’s law has started slowing, while the demand for performance increases has been growing rapidly. With so much talk about Moore’s law slowing down, what does Partha mean by “More Moore Please?”

What he presented was indeed out-of-the-box thinking and outside of the traditional hardware box as his talk title indicated. The following is a summary of what I gathered from his keynote.

Partha starts off by emphasizing that in addition to Moore’s law slowing down, the demand for performance has been growing very rapidly, increasing the severity of the gap. As examples to substantiate the claim, he references YouTube video uploads, which have been growing exponentially over time, emerging machine learning (ML) workloads demand that has been doubling every 3.5 months and cloud computing data traffic growth.

He then draws our attention to security challenges that add significant performance overhead on products and calls that negative Moore’s law. Having showcased the growing gap between performance provided (supply) and performance demand that traditional Moore’s law is struggling to close, he uses the rest of his talk to discuss ways to close that gap. In essence, he recommends a combination of efficient design of hardware, efficient use of hardware, and time incremental deployments of performance enhancements addressing a continuum of opportunities. Through this approach he suggests that more than Moore’s law kind of performance benefits could be derived at the system level.

Efficient Hardware Design

Custom silicon accelerators are simply hardware targeted to specific types of workloads and by taking this approach, the best solution in terms of performance, cost and power is achievable. But performance acceleration involves more than just silicon/hardware. That needs to involve the ecosystem made of firmware, drivers, compilers, debuggers/tracing/monitors, etc., We should look at the entire system that includes compute, memory, networking, and storage. Making acceleration usable requires system software, firmware, applications and hardware/software co-design.

Based on Google’s experiences, successful accelerator projects were those that focused not just on acceleration efficiency (reduced cycles) but also on what exactly was being improved and what impact that would have on the entire system and the user experience.

Efficient Use of Hardware

With workloads changing so very dynamically nowadays in terms of type and duty cycle, efficient use of hardware becomes very critical. The concept of disaggregating the total pool of hardware resources into compute, memory and storage and dynamically configuring them for the workloads that yield the best performance. This is where cloud computing, through its software-defined hardware, could be leveraged.

Time Incremental Performance Deployments

Moore’s law has three variables, performance, cost and timeline. The timeline was 2-year cycles for doubling of performance and halving of cost. We all have experience benefitting from continuous improvement cycles in the software industry where incremental enhancements are released on an ongoing basis through SaaS deployments. Thinking out-of-the-box and coming up with incremental enhancements in hardware acceleration delivered and deployed over shorter time intervals could be a way to close the performance supply-demand gap.

Continuum of Opportunities

Instead of focusing almost exclusively on quantum improvements to a small percentage of the whole set of opportunities, doing incremental improvements to a majority of the set could yield the same or even a better overall performance improvement. For example, instead of focusing just on the applications for performance enhancements, you should focus also on core libraries and systems infrastructure, which have a long tail.

Attack of the Killer Microseconds

Computer systems have traditionally been optimized for nanosecs tasks and millisecs tasks, the two extreme end task types. Nanosecs tasks at the hardware-level that includes pipelining, out-of-order execution, pre-fetching, etc. Millisecs at the system-level that includes task scheduling, context-switching and so on. There are a number of microsecs-type tasks that deserve to be looked at for acceleration. For example, a full, fast networking hop across a data center is one microsec. How much would acceleration of this hop yield in terms of overall system and workload performance? In today’s computing world, there are a number of microsecs-type tasks.

Cadence-Google Collaboration

Partha closes his keynote with references to some of the projects Google is collaborating with Cadence on. Those projects include:

Advanced-node engagements with foundries and on foundational IP
Co-design and custom silicon projects
New licensing models for software enablement for Google Cloud
Multi-physics modeling for system/thermal, next-gen packaging technology and chiplets

Also Read

Cadence adds a new Fast SPICE Circuit Simulator

Fuzzing to Validate SoC Security. Innovation in Verification

Cadence Extends Tensilica Vision, AI Product Line

June 14, 2021June 15, 2021

Highlights of the TSMC Technology Symposium 2021 – Packaging

Highlights of the TSMC Technology Symposium 2021 – Packaging
by Tom Dillinger on 06-14-2021 at 6:00 am
Categories: Events, Foundries, TSMC
2 Comments

The recent TSMC Technology Symposium provided several announcements relative to their advanced packaging offerings.

General

3DFabric^TM

Last year, TSMC merged their 2.5D and 3D package offerings into a single, encompassing brand – 3DFabric.

2.5D package technology – CoWoS

The 2.5D packaging options are divided into the CoWoS and InFO families.

CoWoS-S

The “traditional” chip-on-wafer-on-substrate with silicon interposer for die-to-die redistribution layer (RDL) connectivity is celebrating its 10th year of high-volume manufacturing.

CoWoS-R

The CoWoS-R option replaces the (expensive) silicon interposer spanning the extent of the 2.5D die placement area with an organic substrate interposer. The tradeoff for the CoWoS-R is the less aggressive line pitch for the RDL interconnects – e.g., 4um pitch on the organic, compared to sub-um pitch for CoWoS-S.

CoWoS-L

Between the silicon –S and organic –R interposer options, the TSMC CoWoS family includes a newer addition, with a “local” silicon bridge for (ultra-short reach) interconnect between adjacent die edges. These silicon slivers are embedded in an organic substrate, providing both high density USR connections (with tight L/S pitch) and the interconnection and power distribution features of (thick) wires and planes on an organic substrate.

Note that CoWoS is designated as a “chip last” assembly flow, with die attached to the fabricated interposer.

2.5D package technology – InFO

InFO utilizes (single or multiple) die on a carrier that are subsequently embedded in a reconstituted wafer of molding compound. The RDL interconnect and dielectric layers are subsequently fabricated on the wafer, a “chip-first” process flow. The single-die InFO provides a high-bump count option, with the RDL wires extending outward from the die area – i.e., a “fan-out” topology. As illustrated below, the multi-die InFO technology options include:

- InFO-PoP: “package-on-package”
- InFO-oS: “InFO assembly-on-substrate”

3D packaging technology – SoIC

The 3D packages are associated with the SoIC platform, which utilizes stacked die with direct pad bonding, in either face-to-face or face-to-back orientations – denoted as SoIC chip-on-wafer. Through silicon vias (TSVs) provide connectivity through a die in the 3D stack.

The SoIC development roadmap is illustrated below – as an example, N7-on-N7 die configurations will be qualified in 4Q21.

New Packaging Technology Announcements

There were several key announcements at this year’s Symposium.

maximum package size and RDL enhancements

The demand for a larger number of 2.5D die integrated into a single package drives the need for RDL fabrication across a larger area, whether on an interposer or the reconstituted wafer. TSMC has continued to extend the “stitching” of interconnects past the single exposure maximum reticle size. Similarly, there is a need for additional RDL layers (with aggressive wire pitch).

The roadmap for larger package sizes and RDL layers includes:

- CoWoS-S: 3X reticle (qualified by YE’2021)
- CoWoS-R: 45X reticle (3X in 2022), 4 RDL layers on the organic substrate (W/S: 2um/2um), in reliability qualification using an SoC + 2 HBM2 die stacks
- CoWoS-L: test vehicle in reliability assessment at 1.5X reticle size, with 4 local interconnect bridges between 1 SoC and 4 HBM2 die stacks
- InFO_oS: 5X reticle (51mm x 42mm, on a 110mm x 110mm package), 5 RDL layers (W/S: 2um/2um), currently in reliability assessment

The figure below illustrates a potential InFO_oS configuration, with logic die surrounded by I/O SerDes chiplets, in support of a high-speed/high-radix network switch.

- InFO_B (bottom)

The InFO_PoP configuration shown above depicts an InFO assembly with a DRAM module attached on top, with vias between the DRAM and the RDL interconnect layers.

TSMC is altering this InFO_PoP offering, to enable the (LPDDR DRAM) package assembly to be completed at an external contract manufacturer/OSAT, an option denoted at InFO_B, as shown below.

Correspondingly, TSMC has extended the “Open Innovation Platform” to include 3DFabric partners qualified for InFO_B final assembly. (Currently, the 3DFabric partner companies are: Amkor Technology, ASE Group, Integrated Service Technology, and SK Hynix.)

- CoWoS-S “standard architecture” (STAR)

A prevalent design implementation for CoWoS-S is the integration of a single SoC with multiple High-Bandwidth Memory (HBM) die stacks. The data bus width between the logic die and the HBM2E (2nd generation) stacks is very large – i.e., 1024 bits.

The routing and signal integrity challenges to connect the HBM stacks to the SoC through the RDL are considerable. TSMC is providing systems companies with several standard CoWoS-S design configurations to expedite engineering development and electrical analysis schedules. The figure below illustrates some of the different CoWoS-S options, ranging from 2 to 6 HBM2E stacks.

TSMC anticipates a high adoption rate of these standard design implementations in 2021.

new TIM materials

A thermal interface material (TIM) thin film is commonly incorporated into an advanced package, to help reduce the total thermal resistance from the active die to the ambient environment. (For very high power devices, there are commonly two TIM material layers applied – an internal layer between the die and package lid and one between the package and heat sink.)

Corresponding to the increased power dissipation of larger package configurations, the TSMC advanced packaging R&D team is pursuing new internal TIM material options, as depicted below.

advanced packaging (AP) manufacturing capacity expansion

In anticipation of increased adoption of the full complement of 3DFabric packaging, TSMC is investing significantly in expanding the advanced packaging (AP) manufacturing capacity, as illustrated below.

For more information on TSMC’s 3DFabric technology, please follow this link.

-chipguy

June 13, 2021June 15, 2021

Highlights of the TSMC Technology Symposium 2021 – Silicon Technology

Highlights of the TSMC Technology Symposium 2021 – Silicon Technology
by Tom Dillinger on 06-13-2021 at 6:00 am
Categories: Events, Foundries, TSMC

Recently, TSMC held their annual Technology Symposium, providing an update on the silicon process technology and packaging roadmap. This article will review the highlights of the silicon process developments and future release plans.

Subsequent articles will describe the packaging offerings and delve into technology development and qualification specifically for the automotive sector. Several years ago, TSMC defined four “platforms” which would receive unique R&D investments to optimize specific technical offerings: high performance computing (HPC); mobile; edge/IoT computing (ultra-low power/leakage); and, automotive. The focus on process development for the automotive market was a prevalent theme at the Symposium, and will be covered in a separate article.

Parenthetically, these platforms remain the foundation of TSMC’s roadmap. Yet, the mobile segment has evolved beyond (4G) smartphones to encompass a broader set of applications. The emergence of the “digital data transformation” has led to increased demand for wireless communication options between edge devices and cloud/data center resources – e.g., WiFi6/6E, 5G/6G (industrial and metropolitan) networks. As a result, TSMC is emphasizing their investment in RF process technology development, to address this expanding segment.

General

Here are some general highlights from the Symposium, followed by specific process technology announcements.

breadth of offerings

In 2020, TSMC extended their support to encompass 281 distinct process technologies, shipping 11,617 products to 510 customers. As in previous years, TSMC proudly stated “we have never shut down a fab.”

capacity

Current capacity in 2020 exceeds 12M (12” equivalent) wafers, with expansion investments for both advanced (digital) and specialty process nodes.

capital equipment investment

TSMC plans to invest a total of US$100 billion over the next three years, including a US$30 billion capital expenditure this year, to support global customer needs.

TSMC’s global 2020 revenue was $47.78B – the $30B annual commit to fab expansion certainly would suggest an expectation of significant and extended semiconductor market growth, especially for the 7nm and 5nm process families. For example, new tapeouts (NTOs) for the 7nm family will be up 60% in 2021.

US fab

TSMC has begun construction of a US fab in Phoenix, AZ – volume production of the N5 process will commence in 2024 (~20K wafers per month).

environmental initiatives

Fabs are demanding consumers of electricity, water, and (reactive) chemicals. TSMC is focused on transitioning to 100% renewable energy sources by 2050 (25% by 2030). Additionally, TSMC is investing in “zero waste” recycling and purification systems, returning used chemicals to “electronic grade” quality.

One cautionary note… Our industry is famously cyclic, with amplified economic upticks and downturns. The clear message from TSMC at the Symposium is that the accelerating adoption of semiconductors across all platforms — from data-intensive computation centers to wireless/mobile communications to automotive systems to low-power devices – will continue for the foreseeable future.

Process Technology Roadmap

N7/N7+/N6/N5/N4/N3

The figure below summarizes the advanced technology roadmap.

N7+ represents the introduction of EUV lithography to the baseline N7 process. N5 has been in volume production since 2020.

N3 will remain a FinFET-based technology offering, with volume production starting in 2H2022. Compared to N5, N3 will provide:

+10-15% performance (iso-power)
-25-30% power (iso-performance)
+70% logic density
+20% SRAM density
+10% analog density

TSMC foundation IP has commonly offered two standard cell libraries (of different track heights) to address the unique performance and logic density of the HPC and mobile segments. For N3, the need for “full coverage” of the performance/power (and supply voltage domain) range has led to the introduction of a third standard cell library, as depicted below.

Design enablement for N3 is progressing toward v1.0 PDK status next quarter, with a broad set of IP qualified by 2Q/3Q 2022.

N4 is a unique “push” to the existing N5 production process. An optical shrink is directly available, compatible with existing N5 designs. Additionally, for new designs (or existing designs interested in pursuing a physical re-implementation), there are some available enhancements to current N5 design rules and an update to the standard cell libraries.

Similarly, N6 is an update to the 7nm family, with increasing adoption of EUV lithography (over N7+). TSMC indicated, “N7 remains a key offering for the increasing number of 5G mobile and AI accelerator designs in 2021.”

N7HPC and N5HPC

An indication of the demanding performance requirements of the HPC platform is the customer interest in applying supply voltage “overdrive”, above the nominal process VDD limit. TSMC will be offering unique “N7HPC” (4Q21) and “N5HPC” (2Q22) process variants supporting overdrive, as illustrated below.

There will be a corresponding SRAM IP design release for these HPC technologies. As expected, designers interested in this (single digit percentage improvement) performance option will need to address increased static leakage, BEOL reliability acceleration factors, and device aging failure mechanisms. TSMC’s investment in the development and qualification of processes specifically optimized for individual platforms is noteworthy. (The last HPC-specific process variant was at the 28nm node.)

RF technology

The market demand for WiFi6/6E and 5G (sub-6GHz and mmWave) wireless communications has led TSMC to increase focus on process optimizations for RF devices. RF switches are also a key application area. Low power wireless communication protocols, such as Bluetooth (with significant digital integration functionality) are a focus, as well. Automotive radar imaging systems will no doubt experience growing demand. The mmWave applications are summarized in the figure below.

The two key parameters typically used to describe RF technology performance are:

device Ft (“cutoff frequency”), where current gain = 1, inversely proportional to device channel length, L
device Fmax (“maximum oscillation frequency”), where power gain = 1, proportional to the square root of Ft, inversely proportional to the square root of Cgd and Rg

The TSMC RF technology roadmap is shown below, divided into different application segments.

N6RF

The N6RF process was highlighted at the Symposium – a device performance comparison to N16FFC-RF is shown below.

The N28HPC+RF and N16FFC-RC processes also recently received enhancements – for example, improvements in the parasitic gate resistance, Rg, were highlighted. For low-noise amplifier (LNA) applications, TSMC is evolving their SOI offerings at 130nm and 40nm.

ULP/ULL Technologies

IoT and edge device applications are forecast to become more pervasive, demanding increasing computational throughput at very low power dissipation (ULP) combined with ultra-low leakage (ULL) static power dissipation for improved battery life.

TSMC has provided ULP process variants – i.e., operational functionality for IP at very low VDD supply voltage. TSMC has also enabled ULL solutions, with devices/IP utilizing optimized threshold voltages.

An overview of the IoT (ULP/ULL) platform and process roadmap is given below.

The N12e process node was highlighted by TSMC, integrating an embedded non-volatile memory technology (MRAM or RRAM), with standard cell functionality down to 0.55V (using SVT devices; low Vt cells would enable lower VDD and active power at higher leakage). Comparable focus has been made to reduce the Vmin and standby leakage current of N12e SRAM IP, as well.

Summary

At the Symposium, TSMC introduced several new process developments, with specific optimizations for HPC, IoT, and automotive platforms. RF technology enhancements are also a focus, in support of rapid adoption of new wireless communications standards. And, to be sure, although it didn’t receive much emphasis at the Symposium, there is a clear execution roadmap for the advanced mainstream process nodes – N7+, N5, and N3 – with additional continuing process improvements as reflected in the release of intermediate nodes N6 and N4.

For more information on TSMC’s digital technology roadmap, please follow this link.

-chipguy

Podcast EP24: ASIC Design at the Leading Edge

Podcast EP24: ASIC Design at the Leading Edge
by Daniel Nenni on 06-11-2021 at 10:00 am

Dan and Mike are joined by Graham Curren, founder and CEO of ASIC specialist Sondrel. Graham discusses the challenges of designing ASICs at the leading edge from a technology, design team and customer perspective. He explores where the real challenges are in building these types of chips and how Sondrel meets those challenges.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.