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Samtec Dominates DesignCon (Again)

Samtec Dominates DesignCon (Again)
by Mike Gianfagna on 01-23-2023 at 6:00 am

Samtec Dominates DesignCon Again

Many technical shows have anchor tenants. Those are the companies that can be counted on to have a substantial booth presence, be active in the technical program and just pump life into the event at every turn. Samtec is that company for many shows around the world. And soon it will be time for them to work their magic at DesignCon in Santa Clara. . This show has clearly benefited from Samtec’s presence and energy for quite a while. Read on to see how Samtec dominates DesignCon (again).

Before I get into the details, know that DesignCon will be held at the Santa Clara Convention Center from January 31 – February 2. The show is focused on chip, board, and systems design engineers. This is the intersection where Samtec lives, so you can begin to see why they are prominent at this show. You can head to Samtec’s show page here to receive a free Expo Pass and 20% discount for conference passes. Free stuff is a great way to start any show.

Let’s take a look at where Samtec will be at DesignCon.

Start Things Off at Tuesday’s Welcome Reception, Sponsored by Samtec

Begin at the welcome reception, courtesy of Samtec. The event is Tuesday, January 31 from 6-8 PM in the Hyatt’s Santa Clara Ballroom.  The theme focuses on a tribute to engineers’ contributions to space exploration. Lots of cool gear and stories.

Author Meet & Greet

Istvan Novak, Principal SI-PI Engineer at Samtec, has created a new edition of Power Distribution Network Design Methodologies, which includes selected DesignCon papers from the past. Stop by the Samtec booth (#939) on February 1 from 2:30-3:00 to meet Istvan. He will be joined by several other prominent authors who will talk about their latest books as well.  

Product Showcase

On Wednesday at 3PM Samtec technologists will showcase high-speed interconnects staged for 224 Gbps signaling. You can learn about their power connectors and considerations required for high-speed channels – signal integrity and power integrity.

Booth Demonstrations Wednesday and Thursday

Samtec will be presenting multiple demonstrations featuring products that will help you design systems at 112 Gbps, as well as set you up for 224 Gbps. The details aren’t available yet, but I’m told you can expect production demos at 112G and proof-of-concept demos at 224G. Samtec knows how to create eye-catching, impressive demos. Don’t miss this.

And Everywhere Else 

Samtec products will show up throughout the show floor. Be sure to stop by Rohde & Schwarz (Booth #1049) and Keysight (Booth #1039).

Technical Sessions Tuesday-Thursday

There is also a robust technical program at DesignCon. Samtec is all over that as well. Here is where you can see them:

Panel – PCIe 6.0: Challenges of Achieving 64GT/s with PAM4 in Lossy, HVM Channels

January 31 (Tuesday), 4:45 – 6:00 PM, Ballroom FPanelist: Steve Krooswyk, Senior Signal Integrity Design Engineer at Samtec

Successful PCIe Interconnect Guidelines for 8, 16, and 32 GT/s
February 1 (Wednesday) 9:00 – 9:40 AM, R&S Workshop, Room TBD
Speaker: Steve Krooswyk, Senior Signal Integrity Design Engineer at Samtec

112 Gbps PAM4 Front Panel Connectivity – Real World Implementation and Correlation
February 1 (Wednesday) 11:10 – 11:50 AM, R&S Workshop, Room TBD
Speakers: Greg Vaught, VNA Product Planning Engineer, Rohde & Schwarz & Matthew Burns, Technical Marketing Manager, Samtec

A Novel Approach to 224 Gb/s Reference Receiver Design Using Raised Cosine Response for Noise Mitigation
February 1 (Wednesday) 2:00 – 2:45 PM, Ballroom G
Co-Author: Rich Melitz, Samtec

Panel – What Users Need from Power Integrity Simulators
February 1 (Wednesday) 4:00 PM – 5:15 PM, Ballroom F
Moderator: Istvan Novak, Samtec

3D Connection Artifacts in PDN Measurements
February 2 (Thursday) 9:00 AM – 9:45 AM, Ballroom G
Co-Author: Istvan Novak, Samtec

Cascaded vs End-to-End Multi-Pin Interconnect Simulation Models
February 2 (Thursday) 11:15 AM – 12:00 PM, Ballroom H
Speaker: Robert Branson, Samtec

Envisioning the Future of Power Integrity through the Eyes of Experience
February 2nd (Thursday) 2:00 PM, Cadence Sponsored Session
Speaker: Istvan Novak, Samtec

Conclusion

There you have it. This is most of the places you can see Samtec at DesignCon. It promises to be a great show. You need to be there to see how Samtec dominates DesignCon (again).

 


Podcast EP138: The Impact of Using a Physically Aware NoC with Charlie Janac

Podcast EP138: The Impact of Using a Physically Aware NoC with Charlie Janac
by Daniel Nenni on 01-20-2023 at 10:00 am

Dan is joined by Charlie Janac, president and CEO of Arteris IP. Charlie’s career spans 20 years in multiple industries, including design automation, semiconductor capital equipment, nanotechnology, industrial polymers, and venture capital.

Charlie discusses the benefits of using network-on-chip, or NoC IP on several types of design projects. He also discusses the substantial benefits of using physical awareness for the NoC and how to set up this valuable capability.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interview: Stephen Fairbanks of Certus Semiconductor

CEO Interview: Stephen Fairbanks of Certus Semiconductor
by Daniel Nenni on 01-20-2023 at 6:00 am

Stephen Fairbanks headshot 1 1

Trained as a semiconductor Analog and RF Circuit Designer, Stephen Fairbanks has been designing and developing process-specific I/O and ESD libraries for 24 years. His foundational training began while attending Brigham Young University designing highspeed 32 GSPS data acquisition systems and RF interfaces for a time-of-flight mass spectrometer. Soon after, he joined Intel, where he became the lead developer of the ESD and I/O libraries for what was then Intel’s wireless, cellular, and mobile computing groups. He led the development of the I/O and ESD used on the initial generation and subsequent generations of wireless components for Intel Centrino chipsets and StrongARM cellular platforms. He was personally responsible for the ESD development and I/O support for three families of cellular communications processors and four families of handheld applications processors.

Leaving Intel in 2006, he became an ESD and I/O consultant, establishing SRF Technologies and Certus Semiconductor. Several of his most notable efforts were assisting companies to find ESD solutions for groundbreaking, first-generation technologies. These include but are not limited to ESD protection strategies on many of Qualcomm’s (Atheros) early generation RF front ends for cellular platforms; Inphi, Intel, Xilinx, and Freescale’s (NXP) first generation 10, 28, and 56 GBPS interfaces, and many of Synaptic’s early generation Touch-Screen Interfaces IC’s and Touch-Display IC’s.

Certus Semiconductor has the only commercially available production-proven high-voltage ESD solutions (-18V to 30V, including a 100V pk-to-pk RF Switch) in standard Low Voltage 3.3V, 2.5V, and 1.8V CMOS, for 40nm and below process nodes. These unique solutions have enabled several customers to interface NFC, high-voltage analog, and MEMS I/O’s directly, into low-voltage standard CMOS processes.

At Certus, Stephen has developed ESD process design rules, ESD libraries, and I/O libraries in logic, RF, mixed-signal, and high-voltage BCD processes at the 0.25um, 0.18um, 0.13um, and bulk-CMOS processes 90nm, 65nm, 45/40nm, 28nm, 22nm, 16nm, 12nm, 11nm, and 5/7nm processes. Stephen is familiar with several specialty processes, including HV BiCMOS, flash memory, SiGe, FD-SOI, SOS, and InP.

What is Certus Semiconductor’s backstory?

Certus Semiconductor began as a collaboration between myself, Freescale’s I/O and ESD team, and an ESD consultant, Markus Mergens of QPX. We started the business by putting together commercial I/O packages and marketing Freescale IP with SRF/QPX I/O and ESD custom solutions. When NXP acquired Freescale, the collaboration ended. I maintained the rights to the Certus Semiconductor brand and continued building the business under SRF Technologies. We have expanded our IP offerings to include I/O libraries as well as ESD solutions in many foundries, from 180nm to 11nm, with current R&D at smaller nodes.

What makes Certus’ I/O and ESD solutions unique?
Several features make our solution unique and appealing to our customers. Certus’ complete custom libraries target robustness, noise, distortion, low capacitance, increased ESD, and more. We offer smaller ESD footprints, removing the need for a special mask layer and saving money per wafer. Our low-capacitance ESD enables RF and high-speed digital I/O’s as well as extreme ESD up to 16kV and radiation hardening can also be achieved. We have 3.3V – 5V digital and analog solutions in native 1.8V processes and offer >20V switches using standard low-voltage CMOS technology, allowing for the direct integration of high-voltage analog, sensors, RF, and MEMS. I could continue listing the features that make Certus’ I/O and ESD solutions unique. However, the most important aspect is we tailor our I/O libraries to help our customers differentiate their products in their specific space and our solutions are the highest performance in the industry. Our primary goal is to give our customers a performance and cost advantage over their competitors.

What market segments benefit the most from Certus’ IP?
We have customers across the whole gambit of the industry. From video/audio chips, FPGA, MEMS, mobile phone chips, image processors, ASICs, automotive, sensors, and virtual reality, we offer the entire industry unique I/O and ESD solutions. Consumer electronics benefit from our exceptional ESD protection, smaller GPIO footprints, higher speeds, and lower power, all of which are cost conscious. We offer the Industrial electronics segment benefits from the ESD protection we can provide and the increased robustness, reliability, and feature sets. Regarding automotive, the benefits include increased robustness and higher ESD and voltage tolerances. The Aerospace sector benefits from our solutions’ increased robustness and reliability, high temperature, and radiation-hardened capabilities.

Why should companies choose Certus’ solutions?
If a company has no special requirements, it should use foundry IP. From my experience, that is often not the case, and companies are looking for specific features. If you are looking for features that foundry IP does not offer, such as increased performance, smaller area, or specific advantages over competitors (leakage, capacitance, noise, etc.), our solutions provide these features and more. Many times, we have yet to determine the exact product a customer is looking for, but through engagement, we figure out what our customers need and how we can best optimize their solutions. Additionally, through close interaction with our customers, we brainstorm new features they may not have considered an option, that helps expand their product’s capabilities.

What makes Certus stand out against its competitors?
We offer designs that our competitors do not have. Our I/O performance is addressed by our multi-protocol GPIO that supports various standards with extended specifications across multiple voltages, along with our specialized high-speed die-to-die interface solutions. Our solutions strip away unnecessary features and deliver better ESD performance in a smaller footprint. We optimize power by offering I/O’s that can operate at different voltages selectable by the system, we create dedicated I/O’s tailored for low-power operation. Robust ESD performance is challenging for many companies. ESD engineers founded Certus, and not only do we address standard ESD requirements such as HBM and CDM, we also provide on-chip solutions for standards such as system-level IEC 6100-24-2 and Cable Discharge Events.

Many of our competitors only offer ESD solutions and do not offer entire I/O libraries. Even those who do provide full I/O libraries do not work with their customers as we do. We work hand in hand with our customers and tailor our libraries to meet their needs. We aim to ensure our customers have the best I/O library to meet their needs. We take pride in engaging with our customers as though we were part of the internal I/O and ESD development teams. Finally, we have created a library of industry leading functions at leading nodes which allows us to quickly customize and meet customer’s requirements.

What do the next 12 months have in store for Certus?
We look to grow our business and partnerships over the next 12 months. We have added to our executive staff to expand our market focus and have increased our analog design capabilities. We are considering expanding into the analog design space as we have several customers with analog design needs. Additionally, we are strengthening our partnership with GlobalFoundries and several others. As we grow, we look to continue improving our existing IP and develop new solutions for smaller process nodes. In 12 months, we aim to be the go-to provider for custom I/O and ESD solutions.

How do customers engage with Certus?
We enjoy working closely with our customers and look forward to engaging with other forward-thinking companies. Contact info@certus-semi.com or visit us at www.certus-semi.com to get started!

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ATSC 3.0: Sleeper Hit of CES 2023

ATSC 3.0: Sleeper Hit of CES 2023
by Roger C. Lanctot on 01-19-2023 at 10:00 am

ATSC 3.0 Sleeper Hit of CES 2023

Ten years ago the Open Mobile Video Coalition was touting its plans to deliver free over-the-air television to mobile devices and automobiles. At the time, OMVC was seen as the realization of a dream of delivering video to cars – front seat and back.

The dream didn’t last long and the plans for ATSC M/H brought to the market by the OMVC died and with them the hopes for delivering a shot in the arm to the moribund automotive aftermarket. Those dreams are now being realized with the onset of ATSC 3.0 from the Advanced Television Systems Committee which exhibited at the Consumer Electronics Show – CES 2023 – last week.

The new standard, also known as NextGen TV, offers a host of enhanced experiences including support for HEVC for video channels up to 2160p 4K resolution at 120 frames per second, wide color gamut, high dynamic range, Dolby AC-4, and MPEG-H 3D audio, datacasting, enhanced public alerts, targeted advertising, and mobile television support. The technology also offers the prospect of enhanced positioning technology to support vehicle navigation and autonomous driving.

Perhaps even more important, though, is the key role the automotive industry is likely to play in the ongoing and widespread adoption of ATSC 3.0 in the U.S. and a handful of other geographies globally. Since the average television consumer is unlikely to ask for ATSC 3.0 in their next television set, it is most likely that auto makers will be in position to drive adoption and awareness of the new tech. (For home TV reception broadcasters will continue to support both the current ATSC 1.0 and the new 3.0 standards.)

With larger vehicles arriving in the U.S. market creating opportunities for both rear and front-seat entertainment, ATSC 3.0 presents a unique fore market and aftermarket opportunity. Car makers – most notably Hyundai, likely to be the first – will accelerate plans to introduce ATSC 3.0, while installers will be looking for aftermarket offerings – which are growing in number.

ATSC 3.0 arrives just as the likes of Kenwood/JVC, Alpine, Pioneer, Kicker, and other aftermarket players decamped from CES 2023 in favor of KnowledgeFest in February, according to the CEOutlook newsletter. The automotive aftermarket was hit hard once auto makers began building large-screen infotainment systems into their cars along with navigation and smartphone integration.

ATSC 3.0 may be a yawn for buyers of new digital televisions for their homes – but it represents a revelation for in-car solutions. The technology is particularly attractive for auto makers because it is suitable for datacasting of software updates – a solution rapidly sweeping the industry in the context of vehicles increasingly defined by large software portfolios.

ATSC 3.0 signals are already available to two thirds of the continental U.S. population focused around major metropolitan areas with nationwide coverage in sight by 2025. The technology offers a first-time experience for drivers and their passengers carrying, as they will, enhanced audio and video, local emergency communications, positioning assistance, and software updates. And, best of all, it is free. More importantly, it has already been tested in Michigan and elsewhere, proving the technology is robust and market ready.

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ZoneCast Blast Misses Its Mark

ZoneCast Blast Misses Its Mark
by Roger C. Lanctot on 01-19-2023 at 6:00 am

ZoneCast Blast Misses Its Mark

On my flight to Las Vegas for the annual Consumer Electronics show I dug in to Jeff Smulyan’s autobiographical “Never Ride a RollerCoaster Upside Down – The Ups and Downs and Reinvention of an Entrepreneur.” As CEO, Chairman, and Founder of Emmis Communications Smulyan has had a front row seat to the evolution of the electronics and broadcast industries. Reading the book is a great companion to one’s CES experience – where technology is always in flux and where, in years past the likes of Sirius Satellite Radio and XM duked it out from dueling on-the-showfloor booths before burying the hatchet and merging to become SiriusXM.

CES 2023 has also become the nexus of automotive innovation with multiple car companies in attendance and new tech announcements galore. In particular, multiple exhibitors are showing off their visions of in-car experiences including new audio and video technology, virtual reality, and clever interfaces.

Radio has always been a focal point for automotive innovation and this CES is no exception as Xperi will be showing off its DTS AutoStage technology which is now deployed in cars from Mercedes-Benz, Tesla, and Hyundai – with more to come. Xperi has led the charge to global adoption of digital radio technology which is transforming radio broadcasting and in-vehicle reception experiences.

Digital radio has unlocked radio’s potential for expanding its audience by enabling narrowcasting – more targeted broadcast content intended for different and very specific audiences. Whether via DAB or HD Radio, broadcasters are leveraging narrowcasting to increase the reach of their signals and content.

This development is only the latest iteration along radio’s evolutionary path to expand and grow its already dominant reach. The process began with the onset of FM technology which brought with it the concept of targeting specific audiences ultimately leading to broadcasters focusing on categories such as “adult contemporary” or “urban” music – since FM tended to be music-centric as the sound quality was so superior to AM, which became the home of talk radio – as noted by Smulyan.

In an age of digital advertising, though, radio has been centered around the “broad” in broadcasting. If you advertise on a radio station, you send the same message to the entire geographic footprint of the station’s signal. This is especially problematic if you are a politician not wanting to “waste” money on ads sent to listeners who were not constituents. Of course, this also manifests as traffic reports for jams occuring on the opposite side of town from particular listeners.

Enter, ZoneCasting from GeoBroadcast Solutions. ZoneCasting – now under review by the Federal Communications Commission, offers the potential for radio broadcasts to be geographically segmented to serve particular regional audiences with highly relevant news, weather, sports, content, traffic, and advertising. Broadcasters are interested but perhaps skeptical.

Enter the National Association of Broadcasters and large broadcast industry players like iHeartMedia. The NAB and iHeartMedia have expressed outright hostility to the new technology. It’s worth noting that Smulyan was working in the forefront of the radio industry when FM arrived and he immediately grasped the power and importance of audience segmenting.

Smulyan details his experiences and experiments with audience targeting with religious stations and, of course, WFAN – all sports. But targeting audiences with specific content types does not achieve the ultimate objective of most advertisers in a post-digital world.

Every other advertising medium enables highly specific geographic and demographic targeting of audiences – every platform other than radio, that is. ZoneCasting offers the prospect of opening the door to the next essential evolution of radio – introducing more focused geographic targeting of broadcast signals – without any change in receiving equipment.

I published a commentary several months ago in RadioWorld in support of ZoneCasting, regarding which the FCC has been accepting comments from interested parties as it presumably prepares to make a regulatory finding. I very quickly ran into the objections of the NAB.

I suppose I should feel flattered that the National Association of Broadcasters’ Chief Legal Officer and Executive Vice President of Legal Affairs Rick Kaplan saw fit to attack me in a guest RadioWorld posting for my support of GeoBroadcast Solution’s ZoneCasting technology – which will allow broadcasters to segment their signals to address different regional audiences and advertisers. Kaplan takes me to task for my “misguided” and “misleading” insights regarding GeoBroadcast Solution’s ongoing testing in Jackson, MS, and San Jose and San Francisco – with WRBJ and KSJO, respectively, among other tests.

Kaplan claims that ZoneCasting’s technology will create intolerable – to listeners – interference and interruptions in signals, something that would have been or that he claims has been shown from presumably “unskewed” research. Most revealing of all, though, aside from Kaplan’s mischaracterization of the results and the make up of those and other tests of ZoneCasting tech – flawed and biased in his estimation – is his expressed concern that ZoneCasting will segment the targeted audiences providing a justification for lower advertising rates overall.

This is the nub of Kaplan’s assertions: “ZoneCasting would have a negative effect on broadcasters’ advertising revenue. While broadcast radio’s unique appeal to advertisers is the ability to reach a wide audience in a local market, ZoneCasting would diminish that advantage by splintering listenership. ZoneCasting would depress advertising rates, as ad buyers leverage the availability of cheaper ads to demand lower rates from stations that choose not to deploy ZoneCasting and lead to a race to the bottom.”

This is classic fear, uncertainly, and doubt – FUD. ZoneCasting will actually open doors to new advertising and new advertisers. It will expand the market – like selling pizza slices instead of the entire pizza.

The results of ZoneCasting’s testing are in from reputable technicians demonstrating the efficacy of the technology – which, in different forms of FM boosting, has already seen widespread use. The NAB’s objections appear to revolve around the vested interests of the existing dominant players in the market. For large industry players ZoneCasting is indeed a risk and a vulneratility.

We have seen this resistance to technology and innovation before in the broadcast industry. Smulyan led the charge with NextRadio technology, seeking to accelerate the digitalization of radio and leverage the Internet to make radio searchable and content more discoverable. At that time, iHeartMedia was there to stand in the way of progress, just as they are today.

ZoneCasting represents the future of radio broadcasting. Whether GeoBroadcasting can overcome the resistance and opposition of parties vested in older technology remains to be seen. But to make real progress we do need to stop the spread of misinformation from those who ought to know better and are trusted with the future of the industry.

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2022 Retrospective. Innovation in Verification

2022 Retrospective. Innovation in Verification
by Bernard Murphy on 01-18-2023 at 10:00 am

Innovation New

As usual in January we start with a look back at the papers we reviewed last year. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome. And don’t forget to come see us at DVCon, first panel in the morning on March 1st 2023 in San Jose. Bring your own favorite ideas to share with us!

The 2022 Picks

These are the blogs sorted by popularity. We averaged a little over 10K hits per blog, an encouraging sign that you continue to enjoy this series. As usual the hottest blog was the retrospective, very closely followed by hazard detection using Petri Nets. The latter scored significantly above the average, suggesting we should invest more time in this topic through the coming year. Memory consistency checking, advances in coverage and security also ranked high. We’ll follow your interests by reviewing more papers on these topics through 2023.

2021 Retrospective. Innovation in Verification

Hazard Detection Using Petri Nets. Innovation in Verification

Post-Silicon Consistency Checking. Innovation in Verification

Dynamic Coherence Verification. Innovation in Verification

ML-Based Coverage Refinement. Innovation in Verification

Symbolic Trojan Detection. Innovation in Verification

Refined Fault Localization through Learning. Innovation in Verification

Validating NoC Security. Innovation in Verification

Ant Colony Optimization. Innovation in Verification

Formal at System (July)  Level. Innovation in Verification

Test Ordering for Agile. Innovation in Verification

Stalling to Uncover Timing Bugs. Innovation in Verification

Paul’s view

A third year of blogging on innovation in verification, and I’m still really enjoying it. I truly believe verification is essentially the infinite problem: if you double the gate count you square the state space, and verification is a problem of covering the state space. There is no such thing as being “done”, there are always more devious bugs to be found if time and budget permit. I am grateful to all those of you in academia and industry who continue to research, innovate, and publish your works. The need and opportunity is definitely there!

Looking back on 2022 it was a year of blogging about cool algorithms. I learned about using Ant Colony Optimization in model checking (link). I read two papers that used genetic programming to improve test quality – one on increasing coverage of cross-domain FIFO stalls in big GPUs (link) and another on biasing random instruction generators to produce more memory race conditions (link).

Then there were three papers leveraging neural networks to improve productivity – to predict test failures and test coverage (link), to automatically root cause bugs (link), and to prioritize which tests to run and in what priority order (link).

We also blogged about a neat formal method for abstracting a design to the system level using temporal logic assertions (link), and I had a wonderful walk down memory lane back to my PhD days with a paper on using Petri nets to detect hazards in asynchronous interconnect (link).

Lastly, we zoomed in on a few papers applying formal methods to security verification – on one Trojan logic detection (link) and the other on NOC security (link).

Stepping back from our blog and looking to our industry at large, AI-driven verification and system level verification continue to stand out as big trends. 8 of the 11 papers we covered last year fall under these two big buckets. Here’s looking forward to another fun year of blogging on some more innovations in verification!

Raúl’s view

This is my second year with the Verification Blog and, if nothing else, I have learned a lot (and I hope so did you!) In 2021 the main themes (which of course overlap) we encountered in our random walk included higher levels of abstraction (power side channel leakage, memory consistency at the RTL, Instruction-Level) as well as specific verification aspects such as how to detect flipped Flops and Concolic Testing. We also covered papers on ML/NN (obligatory).

These themes continued to be prevalent in 2022. In the realm of higher levels of abstraction, we explored hazard detection using Petri nets (August, the most popular post, I wonder if the interest was sparked by Petri Nets or hazards/synchronous systems?), the equivalence of higher-level abstraction and RTL (July), and formal properties for NOC security (December). We also looked at how machine learning is being applied to a wide range of verification challenges, including covering hard-to-reach branches (April), fault localization in software (May), and test case selection and prioritization for agile software development (September). Other notable topics we covered included IBM’s Threadmill for post-silicon testing (October), memory consistency verification using genetic algorithms (February), Trojan detection (March), model checking with ant colony optimization (November), and FIFO stall verification (June).

In addition to technical merit and marketability, we also began considering citations and follow-up work. While our sample of two dozen papers is by no means exhaustive, our goal is to give readers a sense of the diverse range of approaches used in verification. And, let’s be honest, where else can you learn about stalling FIFOs, delve into Petri nets, and discover that ants are more effective when they carry food pheromones?


IEDM 2022 – Imec 4 Track Cell

IEDM 2022 – Imec 4 Track Cell
by Scotten Jones on 01-18-2023 at 6:00 am

2022 IEDM Presentation Session23 2 VictorVega Page 03

At the IEDM conference in December 2022, Imec presented “Semi-damascene Integration of a 2-layer MOL VHV Scaling Booster to Enable 4-track Standard Cells,” I had a chance to not only read the paper and see it presented, but also to interview one of the authors Zsolt Tokie.

Logic designs are built up by standard cells such as inverters, NAND gates, scanned flip-flips and other cells. The width of a standard cell is some number of contacted poly pitches (CPP) depending on the cell type and whether the cell has a single or double diffusion break, for example a 2-input NAND gate will be 3CPP wide for single diffusion break and 4CPP wide for double diffusion break. The height of a standard cell is characterized by the metal 2 pitch (M2P) multiplied by the tracks (number of M2P).

As it has become increasingly difficult to scale CPP and M2P, design technology co-optimization (DTCO) has become increasingly important in scaling with techniques such as reducing the tracks. Currently minimum cells are generally 6-tracks with some 5-track cells emerging. In this paper Imec discusses routing techniques to enable a 4-track cell.

Figure 1. presents the Imec roadmap from 9-tracks down to 4-tracks.

Figure 1. Imec scaling roadmap.

Before getting into the routing techniques described here, I wanted to touch briefly on other requirements for cell height scaling, simply talking about M2P and tracks ignores the underlying device structure. The cell height must fit the n and p FETs, n-to-p spacing and boundary widths. The transition from FinFETs to Horizontal Nano Sheets (HNS) provides scaling of the n and p FETs by switching from multiple fins taking up horizontal space to a stack of nano sheets in the vertical direction. Techniques such as forksheets (FS) and buried power rails (BPR) are additional options Imec is developing to address the device height, for example BPR can replace wide metal-2 power rails with tall-thin power rials in the substrate reducing boundary widths, and forksheets can reduce n-to-p spacing. Irrespective of the particular techniques employed the devices must be interconnected.

Leading edge processes have seen the introduction of middle-of-line interconnect layers under the metal-1 layer, these additional layers are typically referred to as Metal 0 (M0) or Mint in Imec’s terminology. To get to a 4-track cell a single M0 layer is not sufficient to interconnect the device. In this work an M0A and M0B are added underneath Mint and in a novel process architecture Mint is used as a mask to perform a tip-to-tip cut in M0B.

Mint connects down to M0B through a via VintB and down to the gate contact through VintG. M0B connects to source drains through Via V0A down to M0A.

Figure 2 illustrates the congestion in a 4-track cell with Mint and Figure 3 illustrates the addition of M0B and M0A.

Figure 2. Congested Cell with Mint only.

Figure 3. Congestion Fixed with addition of M0B and M0A.

To achieve the required tight tip-to-tip spacing a self-aligned cut is used for M0B where Mint acts as the mask, this requires a subtractive metallization process. The metallization utilized here is ruthenium (ruthenium can be dry etched unlike copper) deposited using the semi damascene technique, see figure 4.

Figure 4. Semi-Damascene.

The self-aligned M0B cut is illustrated in figure 5.

Figure 5. M0B Self-Aligned Cut.

By adding two layers and using a self-aligned cut and a 4-track cell can be interconnected. Provided the underlying device structure can also achieve the required scaling this interconnect scheme provides a path to 4-track cells and continued scaling.

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IEDM 2022 – TSMC 3nm

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Application-Specific Lithography: Sub-0.0013 um2 DRAM Storage Node Patterning

Application-Specific Lithography: Sub-0.0013 um2 DRAM Storage Node Patterning
by Fred Chen on 01-17-2023 at 10:00 am

Application Specific Lithography 1

The pursuit of ever smaller DRAM cell sizes is still active and ongoing. DRAM cell size is projected to approach 0.0013 um2 for the D12 node. Patterning challenges are significant whether considering the use of DUV or EUV lithography. In particular, ASML reported that when center-to-center values reached 40 nm, single patterning would not be recommended even for EUV [1]. In this article, we will show that for the 12nm DRAM node and beyond, capacitor center-to-center is expected to go below 40 nm, therefore requiring multipatterning.

DRAM cell layout for Storage Capacitors

Storage capacitors are arranged in a hexagonal array (Figure 1). The active area design rule is determined by the bit line pitch and word line pitch [2].

Figure 1. Storage nodes (yellow) on a DRAM cell grid. BLP=bit line pitch, WLP=word line pitch.

A 38 nm bit line pitch and 33 nm word line pitch would lead to a center-to-center of 38 nm and a pitch of 32.9 nm between diagonals, for a cell size of 0.001254 um2 and just under 12 nm active area design rule.

For a 0.33 NA EUV system, the hexagonal array would use a hexapole illumination, where each pole produces a three-beam interference pattern (Figure 2). The four quadrant poles produce a different pattern than the other two horizontal poles. This leads to two separate dose components with separate stochastics. These are added in the final, composite pattern.

Figure 2. Hexapole illumination for DRAM storage pattern consists of 4 quadrant poles (grey) and two horizontal poles (yellow). Depending on the illumination direction, the resulting three-beam interference pattern has a specific orientation.

Due to substantial absorbed photon shot noise at the feature edge, the stochastic effect on pattern placement error is significant, as already disclosed in Ref. 1, easily exceeding a 1 nm overlay spec. The lower absorbed dose appears to be obviously worse (Figure 3).

Figure 3. Stochastic placement error (X only) of central pillar in 38 nm x 66 nm unit cell (word line pitch = 33 nm), with the expected hexapole illumination in a 0.33 NA EUV system. Here a series of 25 different instances is shown for two absorbed doses.

Going to 0.55 NA adds the issue of severely reduced depth of focus. An NA of 0.55 would result in a 15 nm defocus leading to >50-degree phase shift between the innermost and outermost diffraction orders (Figure 4), which severely reduces the image contrast due to fading [3].

Figure 4. 15 nm defocus on a 0.55 NA EUV system leads to a >50-degree phase shift between the innermost and outermost diffraction orders.

Thus, it is likely the storage node pattern needs to formed from two crossed line patterns (Figure 5). Each crossed line pattern can be formed by a EUV single exposure or by DUV SAQP (self-aligned quadruple patterning). Both options are single-mask processes. The SAQP process is more mature (having long preceded EUV) and free from the secondary electron stochastic concerns of EUV [4], so it should be preferred. Still, for the SAQP case, the spacer lines must be well-controlled both in terms of placement and linewidth roughness [5].

Figure 5. The storage node pattern can be formed by the intersection of two crossed line patterns.

Instead of line-type SAQP, a 2-D spacer honeycomb patterning was also demonstrated by Samsung [6], utilizing a single mask with a starting honeycomb pattern, instead of two masks with starting line patterns.

While the case above considered 38 nm bit line pitch and 33 nm word line pitch, it applies also to the case where the pitches are swapped (33 nm bit line pitch and 38 nm word line pitch), due to the hexagonal symmetry.

References

[1] W. Gao et al., Proc. SPIE 11323, 113231L (2020).

[2] F. Chen, Trigonometric Relationship Among DRAM Cell Pitches, https://www.youtube.com/watch?v=Oq6b-6iw6Zk

[3] J-H. Franke, T. A. Brunner, E. Hendrickx, J. Micro/Nanopattern. Mater. Metrol. 21, 030501 (2022).

[4] F. Chen, Secondary Electron Blur Randomness as the Origin of EUV Stochastic Defects, https://www.linkedin.com/pulse/secondary-electron-blur-randomness-origin-euv-stochastic-chen/

[5] N. Bae et al., Proc. SPIE 11615, 116150B (2021).

[6] J. M. Park et al., IEDM 2015.

This article first appeared in LinkedIn Pulse: Application-Specific Lithography: Sub-0.0013 um2 DRAM Storage Node Patterning

Also Read:

Secondary Electron Blur Randomness as the Origin of EUV Stochastic Defects

Predicting EUV Stochastic Defect Density

Electron Blur Impact in EUV Resist Films from Interface Reflection


Alphawave IP is now Alphawave Semi for a very good reason!

Alphawave IP is now Alphawave Semi for a very good reason!
by Daniel Nenni on 01-17-2023 at 6:00 am

datacenter technology sq

The semiconductor ecosystem has been full of interesting twists of late and Alphawave has been a company to watch since the very beginning. Alphawave came out of stealth mode in early 2019 as the world’s first IP company focused on multi-standard connectivity (SerDes) IP solutions. The importance of SerDes had been understated prior to Alphawave (my opinion) but clearly that is no longer the case. The recent twist is the company’s name change which most of us saw coming after the OpenFive acquisition:

“Announced a new brand, Alphawave Semi, which reflects our ambition to build the leading vertically integrated semiconductor company focused on connectivity solutions. Our new identity preserves the Alphawave brand that our customers have come to depend upon and trust. With Alphawave Semi we expand our capabilities to service our customers – with a portfolio of connectivity IP, custom silicon, and connectivity products.”

This name change is important but let’s start from the beginning. Alphawave’s founders had previously worked together for many years across several different companies:

Tony Pialis co-founded Alphawave in 2017 and has since served as its President and Chief Executive Officer. Prior to Alphawave, Tony cofounded Snowbush Microelectronics which is currently part of Rambus and V Semiconductor which is part of Intel.

Jonathan Rogers co-founded Alphawave in 2017 and has since served as its Senior Vice President of Engineering. He was Director of Design Engineering at V Semiconductor and Gennum. He was also the Director of IP Development and IC Designer at Snowbush Microelectronics Inc.

Raj Mahadevan co-founded Alphawave in 2017 and has since served as its Senior Vice President of Operations and Chief Operating Officer. Prior to Alphawave he co-founded V Semiconductor Inc. where he was a Director and also Snowbush Microelectronics Inc.

Alphawave came to SemiWiki at the end of 2020 when I did the CEO interview with Tony. I immediately knew that this company would be one to watch and it has not disappointed. Since then we have published 12 articles and two podcasts garnering more than 200k views and listens which is a big number.

After listing on the London Stock Exchange AlphaWave acquired OpenFive, the ASIC division of SiFive, which I wrote about here: Alphawave IP and the Evolution of the ASIC Business.

“With OpenFive, Alphawave now competes in the multibillion dollar ASIC business with the likes of Marvel, who acquired the ASIC business from GF and eSilicon, and Broadcom who has the Avago/LSI Logic ASIC business.

You will also see Alphawave come out with standard products (my opinion) like Marvel and Broadcom putting them in the chip big leagues. Thanks to OpenFive, Alphawave expects to hit $500M in 2024 and I expect them to hit $1B not long after that. Yes, this acquisition is that good and I am sure there are more acquisitions to follow.”

With the name change from Alphawave IP to Alphwave Semi the march to IC products (custom silicon) will begin, absolutely.

John Lofton Holt, Executive Chairman of Alphawave:
“Today we announced a new brand for our company, Alphawave Semi, which reflects our ambition since IPO – to build the leading vertically-integrated semiconductor company focused on connectivity solutions. We are committed to generating shareholder value and we are confident that all of our stakeholders will be rewarded as we successfully execute our long-term strategy and continue to deliver for our customers.”

Tony Pialis, President and Chief Executive Officer of Alphawave:
“We are building a leading connectivity business on the foundations of our high-performance IP. Our focus is on executing our vision with an expanded connectivity portfolio addressing more of our customers’ connectivity needs. With a team of almost 700 employees, we are excited about the opportunities ahead and the long-term potential of the business.”

About Alphawave Semi
Alphawave Semi is a global leader in high-speed connectivity for the world’s technology infrastructure. Faced with the exponential growth of data, Alphawave Semi’s technology services a critical need: enabling data to travel faster, more reliably and with higher performance at lower power. We are a vertically integrated semiconductor company, and our IP, custom silicon, and connectivity products are deployed by global tier-one customers in data centers, compute, networking, AI, 5G, autonomous vehicles, and storage. Founded in 2017 by an expert technical team with a proven track record in licensing semiconductor IP, our mission is to accelerate the critical data infrastructure at the heart of our digital world. To find out more about Alphawave Semi, visit: awavesemi.com

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High-End Interconnect IP Forecast 2022 to 2026

Integration Methodology of High-End SerDes IP into FPGAs

Die-to-Die IP enabling the path to the future of Chiplets Ecosystem

 


Where there’s Smoke there’s Fire: UCTT ICHR LRCX AMAT KLAC Memory

Where there’s Smoke there’s Fire: UCTT ICHR LRCX AMAT KLAC Memory
by Robert Maire on 01-16-2023 at 10:00 am

Stock Market on Fire

-UCTT & ICHR both pre announce ugly QTR & blame memory
-LRCX is the memory “poster child” & most impacted
-This is on top of China & Economic issues & memory specific
-Clearing out inventory is a sign of expected slow recovery

UCTT & ICHR pre-announce ugly quarters

Both UCTT & ICHR that are big suppliers to both Lam and Applied, pre-announced a sharp drop in business and seem to indicate it isn’t just a one and done but longer term issue. Both said that memory related business was the main cause of the miss. Lam is obviously the most memory centric of the equipment OEM’s

That flushing sound is inventory

It sounds like OEMs are flushing inventory and orders for new inventory to reduce their exposure (as they should) . This reduction sounds larger and more severe than prior, short lived downturns or pauses in the industry. This seems to suggest that OEMs are expecting a longer, deeper downturn than in recent past-not just a brief pause.

Sub suppliers are the end of the whip but all on the whip are impacted

Sub suppliers such as UCTT & ICHR are near the end of the whip and thus most volatile but others further up the chain will get hit given the level of impact we see at this part of the food chain.
The chain is: Consumer, Product OEMS, Samsung/Inte/TSMC, equipment OEMS, sub suppliers & raw parts suppliers.

LRCX sounds like a “short”

Lam is the most impacted by the memory industry and is one of the biggest customers of both UCTT & ICHR that just missed badly, likely due to a lot of Lam cancelations. Lam supplies both Samsung and Micron.
This is a lot of smoke surrounding Lam which usually indicates a fire.

Negative news will be obscured by goods in field & backlog

Lam had previously reported billions of dollars of almost finished product sitting in crates in the field waiting on parts or completion. Those dollars sitting in crates and a longer than usual order backlog will obscure the actual drop in business that the company is experiencing especially at the bottom line as much will come in at high margin.

The question to ask and be answered on the conference call is what business would look like without all that built in buffer that softens the initial blow.
The main problem is that the buffer will get used up relatively quickly.
This suggests that Lam will not likely miss the quarter as it can manage through this buffer but forward guide on business may not be as strong.

Other sub suppliers that may have issues

AEIS, Advanced Energy, is, at its core a sub supplier of power assemblies to the semiconductor equipment industry and even though more diversified than UCTT & ICHR will get hit as their semi equipment business is higher margin business. MKSI started out as a sub-supplier but has diversified so much that the impact will be minimal.

AMAT & KLAC to a lesser extent

AMAT & KLAC are not nearly as impacted by memory as Lam but still are, as no one in the business can avoid it. KLA’s backlog is second only to ASML so they should weather this the best of the three with AMAT somewhere between.

The stocks

We find it amusing and typical of Wall St that there are many Strong buys and Buys on LRCX with a couple of market performs but no Sells? Yes, the very long term secular view remains very positive but why own it if its going down and likely to report a poor outlook. I can buy back in later at a cheaper price and catch the long term upside. Everyone is talking about WFE being down 20% or more with memory significantly worse than that. We seem to be in a triple whammy of China, the economy and memory and most analysts remain with buy ratings. We are in the middle of a cloud of smoke but no one is yelling “fire”.

About Semiconductor Advisors LLC‌

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

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