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Accellera Update at DVCon 2023

Accellera Update at DVCon 2023
by Bernard Murphy on 03-16-2023 at 6:00 am
Categories: Accellera, EDA, Security

logo accellera min

I have a new-found respect for Lu Dai. He is a senior director of engineering at Qualcomm, with valuable insight into the ground realities of verification in a big semiconductor company. He is on the board of directors at RISC-V International and is chairman of the board of directors at Accellera, both giving him a top-down view of industry priorities around standards. Good setup for a talk with Lu at DVCon’23, to get an update on Accellera progress over the last year. The executive summary: work on a CDC standard is moving fast, there are some updates to IP-XACT (IEEE returning the standard to Accellera for update), IPSA (the security standard) is now moving towards IEEE standardization, and safety and UVM/AMS are still underway.

Lu also talked a little about Accellera/IEEE collaboration. Collaboration is valuable because IEEE standards are long cycle (5-10 years) and ultimately definitive in the industry, whereas Accellera can iterate faster to a 90% convergence in a smaller group, leaving the last 10% for IEEE cleanup. Obviously valuable when a standard is first released but also in updates. On major updates IEEE often returns control to Accellera for spec definition/agreement. When ready, Accellera passes the baton back to IEEE and the Accellera working group folks join the IEEE working group for a smooth transition.

PSS

PSS is gaining significant traction for system level testing, witness applications from most tool vendors. Active standard development is now on the proposed 2.1 release. The big news here is that they are dropping support for C++. Apparently, the demand for C++, originally thought to be a good idea (maybe for SystemC?), just isn’t there. Demand for C support continues strong, however. Since this is a big change, the working group isn’t yet sure if they should rename the release 3.0. Still in debate.

There are other plans for 2.1/3.0, including more on constrained random control coverage. Lu didn’t want to share more than that. I bet as a verification guy he knows more, so probably still under wraps.

Functional safety and security standards

The objective of these standards is similar, to ensure interoperability between different vendor solutions, from IP level design up to SoC level design. And in the case of safety, to enhance propagation of constraints/ requirements from OEM/Tier1 needs down to the design, and constraints added in the design back up to the ultimate consumers of the functionality. (Perhaps that principle will also apply at some point to security standards, but I guess we need to walk before we can run.)

IPSA is underway to IEEE standardization as mentioned earlier. The functional safety standard is still in development. Lu told me that he expects a white paper update around the middle of the year, followed soon after by a draft standard.

CDC and IP-XACT

The goal for CDC is to standardize constraints and other meta-data between vendor platforms. Lu made the interesting point that all the vendor CDC products do a good job, but interoperability is a nightmare. That is important because no tool can do full chip CDC on the big designs. The obvious answer to the full chip need is hierarchical analysis, but IPs and subsystems come from multiple internal and external suppliers who don’t necessarily use the same CDC tools.

CDC products are mature and users have been complaining long enough that the working group apparently knows exactly what they have to do and have set an aggressive schedule for their first release. Lu expects this one to cycle fast. There might be some deficiencies in the first release, such as a lack of constructs for re-convergent paths, but the bulk of the constraints should be covered.

For IP-XACT, Lu expects most updates to be in reference models and documentation. In a quick scan through slides from the DVCon tutorial, I saw several improvements to register map and memory map definitions. I wouldn’t be surprised if this was also in part a response to divergences between vendor solutions. Or perhaps too many vendor extensions? I also saw support for structured ports for cleaner mapping from SystemVerilog for example.

UVM AMS

This standardization effort is a little more challenged. The standard depends on progress both in UVM and in SystemVerilog AMS extensions. For UVM, the working group has made pretty good progress. More challenging has been syncing with IEEE on AMS SystemVerilog language requirements. This appears to be an administrative rather than a technical problem. System Verilog, IEEE 1800, is an established standard and IEEE updates such standards every 5 or 10 years. The working group AMS proposals for System Verilog were maybe a little too ambitious for IEEE deadlines and a scale down effort took long enough that it missed the window.

I’m sure no-one wants to wait another 5 years, yet vendors are unlikely to update their support until they know the standard is official. Lu tells me there are a number of ideas in discussion, including using the 1880.1 standard, originally intended for AMS but never used. We will just have to wait and see.

Membership and Recognition

Lu had an interesting update here on growing participation from Chinese companies. China has participated actively for standards like 4G and 5G, but EDA/semiconductor company participation in standards has not been a thing. Until this year.

Lu’s read is that Chinese companies take the long view. Embargos come and go but design must continue. Those companies will have to work within a standards-compliant ecosystem, so they feel need to be active in understanding and helping define standards.

Huawei has been an associate member for a while. New associate additions in EDA include Univista and X Epic. A semiconductor associate addition is ZEKU, Oppo’s semiconductor subsidiary. If you’re not familiar with Oppo, their product line includes Vivo smartphones, very popular in India and Europe and now starting to appear in the US.

Also of note, in this DVCon, Accellera honored Stan Krolikoski by establishing an annual scholarship for EE/CS undergrads. Lu acknowledged, this has an additional benefit in promoting coursework on standards at the undergraduate level. Accellera also presented the Technical Excellence award posthumously to the late Phil Moorby of Verilog fame. Well deserved.

Lots of good work, more good stuff to anticipate!

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Sino Semicap Sanction Screws Snugged- SVB- Aftermath more important than event

Sino Semicap Sanction Screws Snugged- SVB- Aftermath more important than event
by Robert Maire on 03-15-2023 at 10:00 am
Categories: China, Lithography, Semiconductor Advisors, Semiconductor Services
2 Comments

China Chip Embargo

-Reports of further tightening of China SemiCap Restrictions
-Likely closing loopholes & pushing back technology line
-Dutch have joined, Japan will too- So far no Chinese reaction
-SVB is toast but repercussions may be far worse

Reports of tightening semiconductor sanctions on Friday

It was reported byBloomberg of Friday that the Biden administration was further tightening restrictions on semiconductor equipment that can be sold to China.

It was also reported that the number of tools needing a license, which would likely not be granted , could double. And all of this could happen in a couple of short weeks by April 1st (no joke!)

If we take this at face value, we could take the impact previously reported by companies and basically double it. It could potentially be even worse as if the rules push the technology barrier further into past technology nodes, it is likely that both more customers as well as more equipment types will be covered by the sanctions.

Closing loopholes and work arounds

One of the issues with current sanctions is that there are some loopholes and work arounds that need to be stopped. It is not 100% clear that stopping EUV stops the Chinese at 14NM. With pitch splitting and multiple patterning and a number of unnatural acts and tricks you can coax some limited , low yielding wafers below prior limits.

This suggests that you have to push the limits back deeper into past technology nodes in order to reduce the ability to do a work around or other trick even if low yielding.

Our best guess is that this likely will push back a substantial portion of technology into the age of DUV and 193 immersion technology. On the lithography side, this is relatively clear but on metrology and dep and etch it will be a bit harder to define.

Concerns of re-labeling and altered specifications

One of our chief concerns about the sanctions is that much of the definition of what could and could not be sold rested with the equipment manufacturers.
Could an equipment manufacturer just re-label an existing tool or de-rate its true specifications in order to get an export license? Or better yet, just change the software to neuter the tool with the software fix to re-enable it being easy to implement or sell later. Tesla sells cars with the same battery pack that are software limited to reduced mileage but can be upgraded later through a software switch.

Metrology tools which have a higher software component than dep, etch or litho tools have had many different software options and “upgrades” available that enhanced performance with little to no change in the hardware.

We were concerned a bit by Applied saying that it had $2.5B of impact but said it was working to reduce the impact to only $1.5B by “working” with the customer. How exactly does that work? Could tools have be de-rated, re-labeled just have their specs reduced?

Just drop the hammer and restrict China to 8 inch tools

In our view, the easiest, simplest, most fool proof way of limiting technology is to limit tools sold to 8 inch (200MM) tool sets. That immediately pushes China back to 193 dry litho tools as ASML never made 8 inch immersion tools.
That would cause a relative hard stop at 90NM which would be hard to get around even with multiple patterning and pitch splitting.

Its pretty easy to tell a 200MM tool from a 300MM tool so harder to re-label or derate more advanced tools. Most of the fabs in China are 200MM anyway and most consumer applications can use that generation of device with smart phones and PCs being the exception. Older tools have been selling like hotcakes anyway as noted by Applied in their just reported quarter where 50% of business was non-leading edge (maybe not 8 inch).

China hasn’t responded to the October sanctions so tighten the screws further

We think one of the reason’s the administration is acting now is that there has been essentially no response from China to the October sanctions so why not go ahead and tighten them further given that there seemed to be little chance or ability to respond.

Its not like China has helped us out with the Ukraine/Russia issue and seems to be helping out Russia more, so why be nice. Of course it ratchets up Taiwan issues even further but its not like that has been improving in any event.

Will third parties exit China?

We can only imagine that some of the tightening is aimed at companies like Samsung, or SK or even Intel that have operations in China. The newer sanctions may restrict even more the ability to sell into non-Chinese semiconductor operations located in China.

We would also imagine that the administration has to make sure we don’t see “straw” buyers of tools or cross shipping from third countries. This could help push more fabs back to the US or maybe to India or Europe. These are all good things given the huge percentage of fabs and spend that have been concentrated in China over the last few years

The Dutch have joined the blockcade, Japan will follow suit

It was also announced last week that the Dutch have officially joined the blockade of China. Even though everyone instantly thinks of ASML, we would remind everyone that ASMI , the long lost father of ASML, makes critical ALD tools that are used in many advanced and multiple patterning applications. Adding them to the blockade makes things even more difficult.

Japan has already been doing a “soft” blockade by not trying to replace American tools not shipping to China. In our view its only a short matter of time before they officially join the bandwagon. At that point its all over. There will not be a lot that could be done to get around the three top makers of semiconductor tools all banding together. It would be decades, even with blatant rip-offs, copying and thefts before China could get even a fraction of the tools needed.

SVB- An old fashioned run on the bank in an internet app generation
The overnight implosion of Silicon Valley Bank overwhelmed the news about the new China sanctions, and for good reason. After reading through most of the information that has come out it appears that it is not a heck of a lot more than an old fashioned “run on the bank” or liquidity crisis. This is certainly not reassuring nor is it meant to be, in fact the probability of it happening to other banks is quite high and we have already seen at least one other bank, Signature Bank follow in the implosion of SVB.

Run on the bank

Banks obviously invest and lend out deposits such that only a small fraction of deposited cash is available at any one time for withdrawal and transfer. SVB with $200B plus in assets saw $42B in cash walk out the door in one day, Thursday (over 20% of deposits) such that they were negative $1B at end of day. There aren’t many banks today that could lose 20%+ of their assets in a single day and its amazing that SVB actually did.

This was essentially all depositor panic as the bank couldn’t liquidate assets fast enough to keep up and was forced to try to fire sale and sell stock as well to raise funds.

This was not because as some politicians said it was a tech bank or some sort of tech conspiracy. It was not like the S&L crisis of years ago where investments went bad and the bank simply did not have enough underlying money due to mismanagement. In the S&L crisis, depositors on got back 50 cents on the dollar of non-FDIC money. It is expected that SVB depositors will get 100% because the assets are actually there and worth something when properly, slowly liquidated.

The fed has said Sunday that everyone will get their money.

We would lay more of the blame with the velocity and “twitchiness” of money, and banking apps which is further amplified by lightning fast VC money and tech investors/depositors under pressure.

To unpack that statement we would first point to the fact that with internet apps and access we can move enormous amounts of money easily and without any friction for little more than a whim. With my phone I can move substantial money between multiple banks and brokerage firms without thinking. I don’t have to get in my car and drive down to the bank and wait in line. So the ability for a bank to lose 20% or more of deposits in one day has been enabled by technology ease.

Banks have been paying half a percent when I can and did move my money to get 4% or better elsewhere and it just took me a few clicks.

Secondarily, people have the attention span of a ferret on speed as well as the associated overly rapid reaction, weather to a real or perceived threat. When rumors of SVB started, it was transfer my money first, ask questions later.

There apparently were social media posts in the VC community about SVB issues. In addition Peter Thiel withdrew all his money just before the collapse. We are sure word of all this ran through the VC and tech community in the valley way faster than a wildfire and at internet speeds. This community runs at light speed anyway and obviously has the ability to move money at light speed. Tech has been both under pressure and concerned a lot about money of late which was further tinder for the wildfire and tsunami of money flow.

Basically some sparks started a hyper-speed chain reaction in an already stressed, twitchy, tech community that reacted too quickly for the bank to respond.

The result is SVB – “Silicon” Valley Bank is dead. SVB certainly did take risks and was not as diversified as other banks but that was not the root cause of the issue. Nor was it simple failed investments. They are not 100% clean either with rumors of last minute bonuses and insider stock sales.

SVB will leave a gaping hole in the valley. They did deals others wouldn’t touch. They earned a lot of fierce loyalty from tech companies that remembered who helped them when they were struggling. It is the loss of an icon and the name “Silicon” likely has special resonance for semiconductor related companies who started and still live in the valley. Its a knife in the heart of the tech industry.

But it could easily happen to other banks. Could Chase or Citibank tolerate an exodus of 20% of their depositors in one day? Chase has $3.6T in assets. Could they even come close to having $720B in assets fly out of their servers in the blink of an eye in a day? I very much doubt it. The fiberoptic cables linking them to other recipient banks would melt.

There are no laws or restrictions in existence today that would prevent a repeat of SVB and would prevent a lightspeed fueled, social media catalyzed run on a bank in an exposed sector.

SVB’s bigger issue is collateral damage

SVB is dead and soon to be buried. The FDIC will clean up the mess and bury the body and everybody will get on with business. But in the meantime there will be a parade of companies who are exposed to SVB who will put out press releases of how they are or aren’t impacted. Starting with half a billion at Roku. There will without doubt be a lot of chip and chip equipment companies exposed. We will probably live through a week of press releases and public assurances and telling people to remain calm.

It certainly just exposes how vulnerable things are.

The stocks

The thought of new China sanctions that could double the impact of the loss of China sales and should weigh on the stocks if anyone can get past the SVB news.

Its obviously highly negative for the entire semiconductor equipment group.

We have been saying for some time now that we were not at the bottom and there was still downside and this is yet another example of it.
And don’t forget….memory still sucks….

Add to the new China sanctions the SVB issue, which luckily happened in front of a weekend and you are setting up the upcoming week to look ugly and volatile despite all the well meaning assurances.

A couple of more Signature Banks or Rokus and it could get a lot uglier.
We won’t know the full extent of the fallout of either the new China sanctions nor the SVB fallout for some time. SVB will likely resolve more quickly as the fed has to quell panic. The new China sanctions will take some time to be announced then disseminated and analyzed. Its likely we won’t get an idea about the new impact on semiconductor equipment companies until they start to announce Q1 results in April.

As we have said for quite a while now, we remain highly cautious/negative on the group as a whole and feel that much of this news may cause the recent rally to reverse or at the very least slow. We had suggested that the rally was a dead cat bounce or false bottom and this is likely the evidence that supports that.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

‌Report from SPIE- EUV’s next 15 years- AMAT “Sculpta” braggadocio rollout

AMAT- Flat is better than down-Trailing tool strength offsets memory- backlog up

KLAC- Weak Guide-2023 will “drift down”-Not just memory weak, China & logic too

Hynix historic loss confirms memory meltdown-getting worse – AMD a bright spot

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Scaling the RISC-V Verification Stack

Scaling the RISC-V Verification Stack
by Bernard Murphy on 03-15-2023 at 6:00 am
Categories: Breker Verification Systems, EDA, IP, RISC-V
1 Comment

RISC V verification stack

The RISC-V open ISA premise was clearly a good bet. It’s taking off everywhere, however verification is still a challenge. As an alternative to Arm, the architecture and functionality from multiple IP providers looks very competitive, but how do RISC-V providers and users ensure the same level of confidence we have in Arm? Arm run 1015 cycles of verification per core, with years of experience baked into core and system level regression suites. Equally problematic is verifying the custom instructions you can add in RISC-V. How can a core or system builder measure up to the Arm-level of confidence? A part of the answer, according to Breker, is much higher levels of automation. Makes sense, but what can be automated? Breker start with a verification stack, with layers from early liveness testing in IPs all the way up to system level performance and power profiling.

Core Verification – Part I

Maybe you don’t think you need help testing a RISC-V core, but if you’re just starting out with this architecture, or you’d like to accelerate test suite development (test suite generation is the biggest time hog in the 2022 Wilson survey on verification), or you’d just like to add an independently generated suite of tests to make sure you covered all the bases, Breker’s FASTApps might be worth a look.

Remember how the Breker technology works. Building on one or more PSS (or UVM)-compliant test scenario models, the technology generates usage-centric graphs, then automatically builds a suite of test cases as paths traced through those graphs. These include stimulus, coverage models and expected results. Scenarios can be single-threaded or multi-threaded, even on a single core. The Apps are a layer over this fundamental test synthesis capability. These build important tests for load store integrity, random instruction testing, register-to-register hazards, conditionals and branches, exceptions, asynchronous interrupts, privilege level switching, core security, exception testing (memory protection and machine-code integrity), virtual memory/paging and core coherency.

A noteworthy point here is that custom instructions added to the core become new nodes in these graphs. When you synthesize test suites, custom instructions are added naturally to test suites during scenario development. They will be covered as comprehensively as any other instruction, to the extent possible given the nature of those instructions.

Tests developed through the Breker technology are portable across simulation, emulation, and prototyping platforms and from IP verification to system level verification, maximizing value in the overall test plan. They even have a UVM handle for those allergic to PSS 😊.

SoC Verification

The same approach can be extended to system-level verification apps, here the upper 3 levels of the stack. Breker is already well-known for their dynamic coherency verification, a major consideration at the system level. To this they have added dynamic power management checking. Think of the state machine for a power domain controlling startup and shut down. That can be mapped to a graph, then graphs for each such domain can be squashed together, allowing test synthesis to explore all kinds of interesting scenarios across power switching.

For security verification, scenarios can be defined to test that access to different parts of the memory map. At a more detailed level, test suites can cover system level interrupts, typically even more layered, complex and asynchronous than at the IP level. More possibilities, tests for atomic instructions, in the presence of interrupts for example. System memory virtualization and paging tests. And so on.

What about performance bottlenecks, in the network, in interrupt handling, in external memory accesses, in all the places performance can be dragged down? The best way to attack this problem is by running a lot of synthetic tests concurrently. Like all those tests Breker built for you. That’s a great way to increase confidence in your coverage.

Core Verification – Part II

Core developers know how to deliver coverage for the first 4 levels in the stack, but how do they test system-level correctness, the upper 3 levels? Improving coverage here is just as important. Arm especially has excelled at delivering high confidence for integration integrity. If your RISC-V is being developed in parallel with a system application and use cases, obviously that system will be at least one of your platforms. If you don’t yet have a system target or you want to extend system testing further, you might consider the OpenPiton framework from Princeton. This is a framework to build many-core platforms, offering an excellent stress test for RISC-V system verification.

Running system integrity tests against a core isn’t overkill. I attended a talk recently touching on issues found in system software. Software that has been proven to work correctly on a virtual model of hardware often uncovers bugs when run on an emulated model. A significant number of those bugs are attributable to spec ambiguity, where the virtual model developer and the hardware developer made seemingly harmless yet different decisions.  Difficult to point a finger at who was at fault, but either way expensive disconnects emerge late in design. The Breker solution also allows firmware to be executed early in the verification process, on designs where the processor has not yet been incorporated. You might not catch all these problems in the upper 3 layers of the verification stack, but robust system testing will catch more than you would otherwise.

Worth it?

I really like the approach. No verification technology can do more than dent the infinite verification task, but some can do it more intelligently than others, especially at the system level. Breker provides an intuitively reasonable way to scale the RISC-V verification stack with meaningful coverage. Some blue-chip and smaller customers of Breker also seem to think so. Among customers willing to be cited, Breker mentions both the GM of the SiFive IP business unit and the CEO of Nuclei technology (a RISC-V IP and solution provider). You can learn more about Breker FASTApps HERE.

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JESD204D: Expert insights into what we Expect and how to Prepare for the upcoming Standard

JESD204D: Expert insights into what we Expect and how to Prepare for the upcoming Standard
by Daniel Nenni on 03-14-2023 at 10:00 am
Categories: Comcores, Events, IP

JESD204D SemiWiki Image

Join our upcoming webinar on JESD204 and get insights into what we predict the upcoming JESD204D standard will contain, based on many years of  experience working with JESD204.

Our expert speaker, Piotr Koziuk, has over a decade of experience with JESD204 standards and is a member of the JEDEC Standardization Committee. He will share his prediction of what could be the features of the JESD204D and explain potentially how the new architecture will improve the Bit Error Rate (BER) through Reed Solomon Forward Error Correction (RS-FEC) and new framing and data encoding patterns.

Also briefly touch upon eXtreme Short Reach (XSR) for Die-to-Die or 2.5D Chip-to-Chip stacking applications originating from the underlying 112G OIF Serdes Specifications and cover how the standard will potentially target various reach classes for PAM4 and NRZ encoding and the higher line rates.

Don’t wait to register for this must-attend webinar, happening on April the 11th and 12th.

Register for April 11 th – 11 AM EAST, 8 AM PST – USA

Register for April 12 th – 5 PM China Time, 6 PM Japan & Korea

About Comcores
Comcores is a Key supplier of digital IP Cores and solutions for digital subsystems with a focus on Ethernet Solutions, Wireless Fronthaul and C-RAN, and Chip to Chip Interfaces. Comcores’ mission is to provide best-in-class, state-of-the-art, quality components and solutions to ASIC, FPGA, and System vendors. Thereby drastically reducing their product cost, risk, and time to market. Our long-term background in building communication protocols, ASIC development, wireless networks and digital radio systems has brought a solid foundation for understanding the complex requirements of modern communication tasks. This know-how is used to define and build state-of-the-art, high-quality products used in communication networks.

To learn more about this solution from Comcores, please contact us at sales@comcores.com or visit www.comcores.com

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Scaling AI as a Service Demands New Server Hardware

Scaling AI as a Service Demands New Server Hardware
by Bernard Murphy on 03-14-2023 at 6:00 am
Categories: AI

NLP min

While I usually talk about AI inference on edge devices, for ADAS or the IoT, in this blog I want to talk about inference in the cloud or an on-premises datacenter (I’ll use “cloud” below as a shorthand to cover both possibilities). Inference throughput in the cloud is much higher today than at the edge. Think about support in financial services for fraud detection, or recommender systems for e-commerce and streaming services. Or the hot topic of our time – natural language systems driving chatbots and intelligent virtual assistants, such as ChatGPT. We know that inference, like training, runs on specialized systems: deep learning accelerators (DLAs), built on GPUs, DSPs or other custom hardware based on ASICs or FPGAs. Now we need that capability to serve very high demand, from banks, streaming services, chatbots and many other applications. But current cloud infrastructure is not ready.

Why is Cloud Inference not Ready?

There are already multiple DLA technologies in production use, each offering different strengths. How does a cloud provider simplify user access to a selection of options? DLAs aren’t conventional computers, ready to just plug into a cloud network. They need special care and feeding to maximize throughput and value, and to minimize cost and complexity in user experience. Cloud clients also don’t want to staff expert teams in the arcane details of managing DLA technologies. Providers must hide that complexity behind dedicated front-end servers to manage the interface to those devices.

Scalability is a very important consideration. Big training tasks run on big AI hardware. Multiple training tasks can be serialized, or the provider can add more hardware if there is enough demand and clients are willing to factor the training costs into their R&D budgets. That reasoning doesn’t work for high volume, high throughput inferencing. Inference based on technologies like ChatGPT is aimed at high demand, low margin services, accounted for in client cost of sales. Training supercomputers can’t meet that need given their high capital and operating costs. Supercomputers are not an affordable starting point for inference clients.

High volume demand for general software is handled by virtualization on multi-core CPUs. Jobs are queued and served in parallel to the capacity of the system. Cloud providers like AWS now offer a similar capability for access to resources such as GPUs. You can schedule a virtual GPU, managed through a conventional server offering virtualization to multiple GPUs. Here we’re talking about using these virtual GPUs as DLAs so the server must run a big stack of software to handle all complexities of interfacing between the cloud and the inference back-end. This CPU-based server solution works but also proves expensive to scale.

Why CPU-Based Servers Don’t Scale for Inference

Think about the steps a CPU-based server must run to provide inference as-a-service. A remote client will initiate a request. The server must add that job to the queue and schedule the corresponding task for the next available virtual machine, all managed through a hypervisor.

When a task starts the virtual machine will first download a trained model because each new task needs a different trained model. A target DLA will be selected; the model will then be mapped to the appropriate DLA command primitives. Some of these will be supported directly by the accelerator, some may need to be mapped to software library functions. That translated model is then downloaded onto the DLA.

Next, large data files or streaming data – images, audio data or text – must be pipelined through to drive inferencing. Image and audio data often must be pre-processed through appropriate codecs. Further, DLAs have finite capacity so pipelining is essential to feed data through in digestible chunks. Results produced by the DLA will commonly require post-processing to stitch together a finished inference per frame, audio segment or text block.

Production software stacks to serve inferencing are very capable but demand a lot of software activity per task to initiate and feed a DLA, and to feed results back. The overhead per virtual machine per task is high and will become higher still under heavy loads. Worse yet inferencing traffic is expected to be high throughput with low turn-around time times from request to result. High demand puts higher loads on shared services, such as the hypervisor, which becomes visible in progressively slower response times as more tasks are pushed through.

An Architecture for a Dedicated AI Inference Server

A truly competitive alternative to a general-purpose server solution must offer significantly higher throughput/lower latency, lower power, and lower cost, through the path from network interface to the sequencing function, codecs and offload to AI engines. We know how to do that – convert from a largely software centric implementation to a much more hardware centric implementation. Function for function, hardware runs faster and can parallelize much more than software. A dedicated hardware-based server should be higher throughput, more responsive, lower power  and lower cost than a CPU-based server.

NeuReality, a startup based in Israel, has developed such an AI server-on-a-chip solution, realized in their NR1 network-attached processing unit (NAPU). This hosts a network interface, an AI-hypervisor handling the sequencing, hardware-based queue management, scheduling, dispatching, and pre- and post-processing, all through embedded heterogeneous compute engines. These couple to a PCIe root-complex (host) with 16-lane support to DLA endpoints. The NAPU comes with a full hardware-accelerated software stack: to execute the inference model on a DLA, for media processing and to interface to the larger datacenter environment. The NR1-M module is made available in multiple form-factors, including a full-height single width and full-height double-width PCIe card containing a NR1 NAPU system-on-chip connecting to a DLA. NR1-S provides a rack-mount system hosting 10 NR1-M cards and 10 DLA slots to provide disaggregated AI service at scale.

NeuReality has measured performance for NR1, with IBM Research guidance, for a variety of natural language processing applications: online chatbots with intent detection, offline sentiment analysis in documents, and online extractive Q&A. Tests were run under realistic heavy demand loads requiring fast model switching, comparing CPU-centric platforms with NR-based platforms. They have measured 10X better performance/$ and 10X better performance/Watt than comparable CPU-server-based solutions, directly lowering CAPEX and OPEX for the cloud provider and therefore increasing affordability for client inference services.

These are the kind of performance improvements we need to see to make inference as a service scalable. There’s a lot more to share, but this short review should give you a taste of what NeuReality has to offer. They already have partnerships with IBM, AMD, Lenovo, Arm, and Samsung. Even more impressive, they only recently closed their series A round! Definitely a company to watch.

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MIPI D-PHY IP brings images on-chip for AI inference

MIPI D-PHY IP brings images on-chip for AI inference
by Don Dingee on 03-13-2023 at 10:00 am
Categories: AI, IP, Mixel

Perceive Ergo 2 brings images on-chip for AI inference with Mixel MIPI D-PHY IP

Edge AI inference is getting more and more attention as demand grows for AI processing across an increasing number of diverse applications, including those requiring low-power chips in a wide range of consumer and enterprise-class devices. Much of the focus has been on optimizing the neural network processing engine for these smaller parts and the models they need to run – but optimization has a broader meaning in many contexts. In an image recognition use case, the images must come from somewhere, usually from a sensor with a MIPI interface. So, it makes sense to see Perceive integrating low-power MIPI D-PHY IP from Mixel on its latest Ergo 2 Edge AI Processor, bringing images on-chip for AI inference.

Resolutions and frame rates on the rise

AI processors have beefed up to the point where they can now handle larger images off high-resolution sensors at impressive frame rates. It’s crucial to be able to run inferences and make decisions quickly, keeping ahead of real-time changes in scenes. In view of this, Perceive has put considerable emphasis on the image processing pipeline in the Ergo 2.

 

 

 

 

 

 

Ergo 2 Edge AI Processor system diagram, courtesy Perceive

Large images with a lot of pixels present a fascinating challenge for device developers. In a sense, image recognition is a misnomer. Most use cases where AI inference adds value call for looking at a region of interest, or a few of them, with relatively few pixels wrapped inside a much larger image filled with mostly uninteresting pixels. Spotting those regions of interest sooner and more accurately determines how well the application runs.

The Ergo 2 image processing unit has dual, simultaneous pipelines that can isolate interesting pixels, making it easier for AI models to handle perception. The first pipeline supports four regions of interest in a max image size of 4672 x 3506 pixels at 24 frames per second (fps). The second pipeline can target a single region in a 2048 x 1536 pixel image coming in at 60 fps. The IPU also handles image-wide tasks like scaling, range compression, rotation, distortion and lens shading correction, and more.

Lost frames can throw off perception

Excessive noise or jitter in these fast, high-resolution images can lead to frame loss due to data errors. Lost frames in an image stream can impact the accuracy of inference operations, leading to missed or incorrect perceptions. Reliable image transfer that holds up to challenging environments is a necessity for accurate perception at the edge.

A defining feature of the Mixel MIPI D-PHY IP is its clock-forwarded synchronous link that provides high noise immunity and high jitter tolerance. In the Ergo 2, three different MIPI IP solutions are at work: a four-lane CSI-2 TX, a two-lane CSI-2 RX, and a four-lane CSI-2 RX. Each IP block integrates a transmitter or receiver and a 32-bit CSI-2 controller core. Links run up to 2.5 Gbps, with a typical eye pattern shown next.

First-pass success makes or breaks smaller chips

A flaw appearing in a large SoC isn’t fun, and a redesign can be expensive. However, a bigger SoC project tends to have a bigger design team, a longer schedule, and a bigger budget. On a smaller chip, a bust can kill a project in its tracks, with debug and re-spin costs quickly escalating to more than the initial development cost.

Although first-pass success isn’t a given in the semiconductor business, Perceive was able to achieve that with the Mixel IP. Mixel supported Perceive with compliance testing, enabling the full-up integrated design to endure rigorous MIPI interface characterization before the SoC moved to high-volume production. Mixel MIPI D-PHY IP contains pre-driver and post-driver loopback and built-in self-test features for exercising transmit and receive interfaces.

The result for Perceive of integrating Mixel’s MIPI D-PHY IP was hitting power, performance, and cost targets for the Ergo 2. Perceive’s customers, in turn, can implement Ergo 2 in smaller, power-constrained devices where battery life is a key metric, but AI inference performance has to be uncompromised. It’s a good example where bringing images on-chip for AI inference with carefully crafted integration contributes to savings at the small-system level.

For more information:

Perceive: Ergo 2 AI processor

Mixel: MIPI D-PHY IP core

Also Read:

MIPI bridging DSI-2 and CSI-2 Interfaces with an FPGA

MIPI in the Car – Transport From Sensors to Compute

A MIPI CSI-2/MIPI D-PHY Solution for AI Edge Devices

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SPIE Advanced Lithography Conference 2023 – AMAT Sculpta® Announcement

SPIE Advanced Lithography Conference 2023 – AMAT Sculpta® Announcement
by Scotten Jones on 03-13-2023 at 8:00 am
Categories: Semiconductor Services, TechInsights
3 Comments

Applied Materials Sculpta Presentation for Media Page 06

The SPIE Advanced Lithography Conference is the semiconductor industries premier conference on lithography. The 2023 conference was held the week of February 27th and at the conference Applied Materials announced their Sculpta® pattern shaping tool. Last week I had an opportunity to interview Steven Sherman the Managing Director and General Manager of the Advanced Products Group and discuss the new tool.

Introduction

The resolution of an exposure system is given by the Rayleigh Criteria:

R = k1λ/NA

where k1 is a process related factor, λ is the exposure wavelength and NA is the optical system numerical aperture.

The semiconductor industry is continually driving to smaller dimensions to enable greater transistor/bit density. With EUV delayed for many years, DUV was extended by a variety of techniques where multiple exposures were combined to create a higher resolution pattern than a single exposure could produce. Once EUV entered production multi patterning was in many cases replaced by a single EUV exposure.

From the Rayleigh Criteria the ultimate resolution for the current 0.33 NA EUV systems should be approximately 20nm but we are currently far from realizing that. ASML tests EUV system at the factory to 26nm on a flat wafer with a simple one-dimensional pattern but in production 30nm is the current practical limit and even then, there are circumstances where tight tip-to-tip requirements can require an extra cut or block mask. With a single EUV exposure tip-to-tip spacings are currently limited to approximately 25 to 30nm and a second EUV mask is required to get to a 15 to 20nm tip-to-tip. Next generation processes will require several EUV multi patterning layers. the Sculpta® tool is designed to address this situation.

Applied Materials Presentation

In their presentation Applied Materials describes two common cases where two EUV masks are used to create a pattern. The first is where dense interconnect lines are formed by an EUV mask and then a second EUV mask is used to cut or block the pattern to achieve tight tip-to-tip in the orthogonal direction. The second case is where one EUV mask is used to create an array of elongated contacts and then a second EUV mask is used to create a second array of contacts with tight tip-to-tip spacing relative to the first array. Elongated contacts are desirable for reduced sensitivity to placement errors versus lines.

In their presentation Applied Materials illustrates a simplified Litho-Etch Litho-Etch process flow that uses two EUV masks combined with two etches to create a pattern, see figure 1.

Figure 1. EUV Double Patterning Process Flow.

In figure 1, two litho-etch passes are illustrated. In each pass a deposition step deposits a film, the film is planarized, a lithography pattern is formed and measured, the pattern is etched into the film and then cleaned and measured again. Applied materials characterize each litho-etch pass as costing approximately $70.

I write for SemiWiki as a sideline to my “day job” building cost models for the semiconductor industry. A single EUV exposure cost about 2x the $70 cost listed for the entire litho-etch pass, the overall litho-etch pass cost is several times what Applied Materials is conservatively estimating as $70. Eliminating an EUV exposure with associate processing has a lot of value.

The Sculpta® tool is an etch tool built on the Applied material Centura® platform that uses an angled reactive ribbon beam to elongate a pattern in a hard mask. The two examples discussed were:

  1. Form a grating of lines and spaces with a relatively wide tip-tip spacing then use the Sculpta® tool to shrink the tip-to-tip, see figure 2.
  2. Form a dense array of round contact holes and then use the Sculpta® tool to elongate the contact holes, see figure 3.

In both cases a Litho-Etch – Litho-Etch process with two EUV exposures and associated processing is reduced to a single EUV Litho-Etch process followed by a Scultpa® tool shaping process.

Figure 2. Pattern Shaping of Interconnect Lines.

Figure 3. Pattern Shaping of Contacts.

Figure 4 illustrates the Sculpta® tool, it is a Centura® cluster tool with four ribbon beam etch chambers.

Figure 4. Centura® Sculpta® tool.

Applied Materials stated that the Sculpta® tools is the tool of records for multiple layers at a leading-edge logic customer and they included positive quotes from Intel and Samsung in their press release.

Analysis

The first thing to understand is the Sculpta® tool is addressing tip-to-tip and is not a general resolution enhancement solution. If you need resolution below 30nm today you would still be looking at EUV multi patterning, for example EUV based SADP. Sculpta® does not “fix” the fundamental 0.33 NA EUV limitations and does not eliminate the needs for High-NA EUV tools in the futures. It can however eliminate some EUV masks used to create tight tip-to-tip, this can help alleviate the EUV exposure system shortage and save on cost, process complexity and possibly environmental impact.

This brings up the question of cost savings. A standard 4 chamber cluster tool etcher should have a cost in the ten-million-dollar range. The Sculpta® tool may have specialized chambers that add cost but I would be surprised if it cost more than $15 million dollars (Applied Materials did not provide any guidance on this). For 2022 the average ASP for an EUV system from ASML is nearly $200 million dollars from ASML’s financial reports. Add to that deposition, etch, CMP, cleaning, inspection and metrology equipment and compares that to a Sculpta® tool, some inspection and metrology tools, and possibly a cleaning tool, and the capital cost saving should be substantial. The key question is what the throughput is for the Scupta® tool. I asked Applied Materials about this and was told it depends on the amount of shaping and the hard mask material being used (the pattern shaping is done to the hard mask before the pattern is etched into the final film). Due to the required precision I wouldn’t be surprised if the etch times are relatively long and therefore the tool throughput is relatively low, but it would have to be incredibly slow for the Sculpta® tool not to be a much less expensive option than an EUV Litho-Etch loop. The other questions would be what the practical process limits on the technique are in terms of where it can be applied. The fact that it has already been adopted for multiple layers at – at least at one major logic producer argue that it is a promising solution.

Conclusion

In conclusion I see this as a useful addition to the lithographer’s tool set. It is probably not revolutionary but will nicely augment the capability of EUV tools and could see wide adoption for leading edge logic and DRAM fabrication.

Also Read:

IEDM 2023 – 2D Materials – Intel and TSMC

IEDM 2022 – Imec 4 Track Cell

IEDM 2022 – TSMC 3nm

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

Podcast EP147: CachQ’s Harnessing of Heterogeneous Compute with Clay Johnson

Podcast EP147: CachQ’s Harnessing of Heterogeneous Compute with Clay Johnson
by Daniel Nenni on 03-10-2023 at 10:00 am

Dan is joined by Clay Johnson, CEO and co-founder of CacheQ Systems. Clay has more than 25 years of executive management experience across a broad spectrum of technologies including computing, security, semiconductors and EDA tools.

Dan discusses the CacheQ QCC development platform with Clay. This platform enables software developers to deploy and orchestrate applications using new compute architectures, such as multicore devices and heterogeneous distributed compute. The result is a significant increase in performance, reduced power and dramatically reduced development time.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Cadence Hosts ESD Alliance Seminar on New Export Regulations Affecting EDA and SIP March 28

Cadence Hosts ESD Alliance Seminar on New Export Regulations Affecting EDA and SIP March 28
by Bob Smith on 03-10-2023 at 6:00 am
Categories: Cadence, EDA, ESD Alliance, Semiconductor Services

ESD Alliance Export Seminar 2023

Anyone interested in learning about general trade compliance concepts or how export control and sanction regulations affect the electronic systems design ecosystem will want to attend the upcoming ESD Alliance export seminar. It will be hosted by Ada Loo, chair of the ESD Alliance Export Committee and Cadence’s Group Director and Associate General Counsel and held March 28 at Cadence’s corporate headquarters,

The seminar will feature the Cadence Government and Trade Group, including Ada and William Duffy, Cadence’s Corporate Counsel. They will discuss why and how governments implement trade controls, what “exports” are and how they take place in different business contexts. The seminar will cover common due diligence methods, such as customer screening that U.S. companies use to incorporate regulatory compliance into their business processes. It will also highlight recent regulatory updates that address current issues such as U.S.-China trade relations and anticipated effects of those regulations on the U.S. semiconductor design ecosystem.

Attendees will get an overview of relevant regulators and regulations, including a high-level summary of the U.S. government’s publicly stated policy positions and how they influence the development of export controls that affect the EDA industry. The seminar will focus on the Export Administration Regulations (EAR) with a discussion on the International Trafficking in Arms Regulations (ITAR) and Office of Foreign Assets Control (OFAC) sanctions programs. It will look at what is and is not regulated under the EAR, what constitutes an “export,” “reexport,” “release,” and “transfer,” how tangible and intangible exports differ, and scenarios where exports can take place inadvertently.

General prohibitions and regulated activities under the EAR will be covered, as will the facts that compliance officers should almost always know or be willing to ask about any given transaction. Business implications that they must consider when evaluating transactions and instituting effective processes to backstop compliance will be addressed.

Another topic will be how business operations can and should be structured to accommodate export compliance regulations, including questions that compliance personnel should frequently ask themselves and business partners. The seminar will examine where export compliance considerations affect sales, operations, customer support and product development and evaluate effective compliance programs as described by the Bureau of Industry and Security (BIS) compliance guidelines. It will offer ways to identify red flags in customer behavior and how companies can protect themselves by asking the right questions, having the right contract clauses, and by asking for the right assurances from uncertain customers. The implications of falling short in compliance and how to investigate potential escapes internally and with outside counsel will be discussed.

The breakfast meeting will be held Tuesday, March 28, from 8:30am until 11:30am at Cadence’s corporate headquarters in San Jose.

Member tickets are $100 each and $125 per non-member. Member pricing is offered for individuals or companies that are active SEMI members. Visit the ESD Alliance website to register: www.esd-alliance.org

Please contact me if your company is interested in learning about the The ESD Alliance, a SEMI Technology Community, and the range of our programs. We represent members in the electronic system and semiconductor design ecosystem that addresses technical, marketing, economic and legislative issues affecting the entire industry. We act as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. I can be reached at bsmith@semi.org.

The Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, an international association of companies providing goods and services throughout the semiconductor design ecosystem, is a forum to address technical, marketing, economic and legislative issues affecting the entire industry. It acts as the central voice to communicate and promote the value of the semiconductor design industry as a vital component of the global electronics industry.

Follow SEMI ESD Alliance:

www.esd-alliance.org

ESD Alliance Bridging the Frontier blog

Twitter: @ESDAlliance

LinkedIn

Facebook

Also Read:

2022 Phil Kaufman Award Ceremony and Banquet Honoring Dr. Giovanni De Micheli

ESDA Reports Double-Digit Q3 2021 YOY Growth and EDA Finally Gets the Respect it Deserves

ESD Alliance Reports Double-Digit Growth – The Hits Just Keep Coming

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AAA Hypes Self-Driving Car Fears

AAA Hypes Self-Driving Car Fears
by Roger C. Lanctot on 03-09-2023 at 10:00 am
Categories: Automotive
3 Comments

AAA Hypes Self Driving Car Fears

The AAA (U.S. auto club) must have AGHD (attention-getting deficit disorder). The headline from the organization’s latest research is: “Fear of Self-Driving Cars is on the Rise.” That should straighten things out, right?

The survey was conducted across a representative sample of U.S. households, according to the reported methodology. This was an effective way to enhance the “fear factor” by not focusing the survey specifically on the drivers themselves or whether they own vehicles or intend to buy a vehicle soon. The “fear” that the AAA is targeting is presumably some sort of widespread anxiety among the general population.

Fear is an effective emotion to grab the attention of the press and consumers. There isn’t much else that turns our heads these days and all forms of media – broadcast, print, online – routinely turn to fear to increase ratings, viewers, and stimulate reactions: likes, shares, thumbs up.

Fear also has a deadening or muffling effect.  It is overwhelming and obscuring. Fear means different things to different people and fear isn’t always the right word for how people really feel.

I just returned from the Mobile World Congress in Barcelona. Was I afraid of being pickpocketed or otherwise becoming a victim of some petty crime? Not really afraid. No. “Concerned” would be a better term or “aware” of my surroundings – as I would be in any urban environment. Those feelings would be slightly elevated due to Barcelona’s reputation. Definitely not “afraid.”

AAA could have performed a much more useful public service if it had surveyed specific consumer groups – which, of course, would have been more complicated and expensive. Car makers and the general public would probably appreciate an education as to how current car owners feel about self-driving cars or how likely car buying intenders feel.

Saying consumers, in general, are afraid of self-driving cars reminds me of an old Monty Python’s Flying Circus animation of “killer cars” terrorizing London. The cars in the animation eat pedestrians – it seemed funny at the time.

By hyping the fear factor, though, AAA is missing the bigger picture. A more accurate description of the state of consumer attitudes toward cars generally and self-driving in particular would reflect intense curiosity, some concern, and, in some circles, broad-based enthusiasm.

TechInsights has conducted this research and found skepticism on the decline and interest in self-driving technology on the rise. The latest study, conducted in 2022 by TechInsights, found that at least 20% of car owners in China would pay more for any automated driving or parking feature, a figure that falls to 10% in Western Europe and 15% in the U.S.

A third of customers in China would pay more for fully autonomous driving capabilities. This figure does not exceed 18% in the West. This is certainly not what one would describe as fear.

Chinese consumers are most interested in automated parking. U.S. and Western European customers are more likely to pay more for parking assistance, followed by fully autonomous driving.

Missing this more nuanced part of the story is the greatest failing of the AAA study. In fact, enthusiasm for and interest in self-driving is a major contributor to Tesla’s ability to not only sell hundreds of thousands of cars equipped with its Autopilot technology (which still requires driver engagement), but has also fueled widespread consumer willingness to pay as much as $15,000 for so-called Full Self-Driving technology which is being blamed and investigated for crashes and mocked for its limitations.

In essence, AAA appears to be trying to stimulate fear rather than simply measure it. That, ultimately, is the weakness of the AAA study. Instead of lighting a candle, AAA has turned on the high beams blinding news consumers to the realities of the evolving driver assistance landscape. Consumers are actually quite interested in cars enhanced with driver assistance technology. Don’t let the fear mongers at AAA fool you.

Also Read:

IoT in Distress at MWC 2023

Modern Automotive Electronics System Design Challenges and Solutions

Maintaining Vehicles of the Future Using Deep Data Analytics

ASIL B Certification on an Industry-Class Root of Trust IP