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Semiconductor Expert Forum

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WEBINAR: Why Rigorous Testing is So Important for PCI Express 6.0

WEBINAR: Why Rigorous Testing is So Important for PCI Express 6.0
by Daniel Nenni on 09-25-2023 at 8:00 am
Categories: EDA, Events, Synopsys

PCIe IO bandwidth doubles every 3 years

In the age of rapid technological innovation, hyperscale datacenters are evolving at a breakneck pace. With the continued advancements in CPUs, GPUs, accelerators, and switches, faster data transfers are now paramount. At the forefront of this advancement is PCI Express (PCIe®), which has become the de-facto standard of interconnect for high-speed data transfers between processing and computing nodes.

Click here to register now!

Doubling Data Rates: The Trend Continues

The PCI-SIG® consortium, responsible for the PCIe interface, has a history of launching a new PCIe generation approximately every three years. This invariably has doubled the data rate over the past decade. PCI-SIG’s latest release, PCIe 6.0.1, ushers in multi-level Pulse Amplitude Modulation (PAM4) signaling, boasting a staggering transfer rate of 64 GT/s in one direction on a single lane. Notably, during the 2022 PCI-SIG DevCon, the announcement of PCIe 7.0 specification came, doubling the data rate to 128 GT/s, emphasizing both power efficiency and higher bandwidth.

Figure 1. PCI-SIG I/O Bandwidth doubles every 3 years. From PCI-SIG

 Stringent Testing for Compliance and Interoperability

It’s important to understand that beyond hyperscale data centers, the deployment of PCIe technology in fields like handheld devices, servers, automotive, industrial applications, and more demands high reliability and cost-effectiveness. This necessitates rigorous compliance testing for products to ensure they align with the PCIe 6.0.1 specification and can successfully interoperate with other PCIe devices.

Unveiling PAM4 Signaling and its Implications

The integration of PAM4 signaling in PCIe 6.0.1 is key. Unlike the Non-Return-to-Zero (NRZ) signaling, which used two distinct signal levels, PAM4 uses four, transmitting two bits of information within a single unit interval (UI). This modification introduces new challenges like cross-talk interferences, signal reflections, and power supply noise. The PCIe 6.0.1 specification has introduced the Signal-to-Noise Distortion Ratio (SNDR) to address these challenges, encapsulating both the traditional noise and non-compensable impairments within the electrical signal. Understanding of signal integrity issues in the high-speed communication channels due to cross-talk, reflection losses with frequency and time domain analysis  is the key. Channel measurement techniques and various signal enhancement techniques with PCIe 6.0 Transmitter and Receiver equalization are used to compensate for non-ideal channel characteristics.

Summary

The advancements in PCIe technology have paved the way for a new age of data transfer capabilities, with PCIe 6.0.1 and the forthcoming PCIe 7.0 setting new benchmarks. However, with greater capabilities come greater challenges, particularly in ensuring compliance and interoperability. Partnerships like Synopsys and Tektronix are leading the charge in addressing these challenges, ensuring that the technology not only meets but exceeds the demands of today’s digital age.

Join Our Webinar!

Want to delve deeper into PCIe simulations and electrical testing? Join our upcoming webinar on Tuesday October 10, from 9:00 am to 10:00 am PDT, where Synopsys and Tektronix industry experts will discuss the latest in PCIe technology and the significance of robust testing methodologies. Click here to register now!

Speakers:

David Bouse is a Principal Technology Leader at Tektronix and an active contributor to PCI-SIG with expertise in highspeed SERDES including transmitter and receiver test methodologies, DSP algorithms for NRZ/PAM4 signaling, clock characterization, and automation software architecture.

Madhumita Sanyal is a Sr. Staff Technical Manager for Synopsys high-speed SerDes portfolio. She has +17 years of experience in design and application of ASIC WLAN products, logic libraries, embedded memories, and mixed-signal IP.

About Synopsys

Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As an S&P 500 company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and offers the industry’s broadest portfolio of application security testing tools and services. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing more secure, high-quality code, Synopsys has the solutions needed to deliver innovative products. Learn more at www.synopsys.com.

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Next-Gen AI Engine for Intelligent Vision Applications

VC Formal Enabled QED Proofs on a RISC-V Core

Computational Imaging Craves System-Level Design and Simulation Tools to Leverage AI in Embedded Vision

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TSMC’s First US Fab

TSMC’s First US Fab
by Daniel Nenni on 09-25-2023 at 6:00 am
Categories: Foundries, TSMC
5 Comments

WaferTech TSMC

TSMC originally brought the pure-play foundry business to the United States in 1996 through a joint venture with customers Altera, Analog Devices, ISSI, and private investors (no government money). Altera is now part of Intel but ADI is still a top TSMC customer and enthusiastic supporter. I have seen the ADI CEO Vincent Roche present at recent TSMC events and his TSMC partnership story is compelling. This joint venture was part of TSMC’s customer centric approach to business, responding directly to customer requests.

The WaferTech fab was established in Camas Washington (just North of the Oregon/Washington border) in 1996 with an investment of more than $1B which was a huge amount of money at the time. Production started two years later at .35 micron which was part of the Philips technology transfer that TSMC was founded upon. In 2000 TSMC bought out the partners and private investors, taking full control of the Washington fab. It is now called TSMC Fab 11 but clearly this fab was ahead of its time, absolutely.

From TSMC:

WaferTech focuses on Embedded Flash process technology while supporting a broad TSMC technology portfolio on line-widths ranging from 0.35-microns down to 0.16-microns. We specialize in helping companies deliver differentiated products and work with them on a number of customized and manufacturing “phase-in” projects. As a result, WaferTech delivers the latest generation semiconductors around the globe, supporting innovations in automotive, communications, computing, consumer, industrial, medical and military/aerospace applications.

To complement our world class process manufacturing services, WaferTech also provides test and analysis services at our Camas, Washington facility. Moreover, TSMC provides design, mask and a broad array of packaging and backend services at its other locations around the world. WaferTech also is a host for TSMC’s foundry-leading CyberShuttle™ prototyping services that help reduce overall design risks and production costs.

WaferTech, First U.S. Pure-play Foundry Ships Production Qualified Product ahead of Plan Issued by: Taiwan Semiconductor Manufacturing Company Ltd. Issued on: 1998/07/07

“With WaferTech on-line and shipping, TSMC customers gain another assured source for wafers produced to our standards of excellence,” said Ron Norris, president of TSMC, USA and a director of WaferTech. “Now TSMC is the only foundry in the world to transparently support customers from geographically dispersed sites.”

Ron Norris is another hire TSMC made with TI roots. Ron himself was a semiconductor legend. He started his career at TI and held executive level positions at Microchip in Arizona, Fairchild Semiconductor in Silicon Valley, and Data I/O Systems in Redmond WA, so he certainly knew the challenges of semiconductor manufacturing in the United States.

Historically, TSMC doesn’t just build fabs, TSMC builds communities. In fact, a TSMC fab itself is a community with everything you need to help maintain a work life balance. I have spent a lot of time in different fabs around the world but for the most part they were TSMC fabs in Taiwan. I still consider the Hsinchu Hotel Royal (walking distance from TSMC Fab 12A) as my second home. I remember flying in on my birthday one year and the staff had a mini birthday celebration when I arrived. Yes, they are that good, but I digress.

One thing you have to remember is that in Taiwan, working for TSMC brings status. You are a rockstar. Working for Samsung in South Korea has a similar aura. When TSMC breaks ground on a new fab location in Taiwan you can expect a whole support ecosystem to develop around it with everything a TSMC fab needs to be successful including housing and university level education for recruiting and employee growth.

Bottom line: Working for TSMC in Taiwan is like joining a very large and very successful family business.

Unfortunately, in Camas Washington, that was not the case. The WaferTech campus is a 23 acre complex housed on 260 acres. The main fabrication facility consists of a 130,000 square foot 200mm wafer fabrication plant.  Additional fabs were planned but never built, a support ecosystem never formed, thus the TSMC Taiwan fab recipe was called out as a failure in the US.

Many reasons have been sited for this “failure” including high costs, problems attracting local talent, and timing (soft economy), but in my opinion it also had a lot to do with the rockstar factor. In the US we had forgotten or did not know yet how important semiconductors were to modern life and TSMC was not a big name in the US like it is today.

Now that TSMC is building fabs in Arizona, Kumamoto Japan, and Dresden Germany it will be interesting to see how different the TSMC experience is in these world wide locations.

Also Read:

How Taiwan Saved the Semiconductor Industry

Morris Chang’s Journey to Taiwan and TSMC

How Philips Saved TSMC

The First TSMC CEO James E. Dykes

Former TSMC President Don Brooks

The TSMC Pivot that Changed the Semiconductor Industry!

The TSMC OIP Backstory

Podcast EP183: The Science and Process of Semiconductor Innovation with Milind Weling

Podcast EP183: The Science and Process of Semiconductor Innovation with Milind Weling
by Daniel Nenni on 09-22-2023 at 10:00 am

Dan is joined by Milind Weling, the Head of Device and Lab to Fab Realization and co-founder of the neuro-inspired Computing Incubator of EMD Electronics. Previously he was senior vice president for Intermolecular. He led customer programs and operations where he drove the discovery and optimization of new materials, integrated module solutions and leading-edge devices. Milind is a senior engineering and management professional with extensive experience in advanced memory and logic technology development, DFM and design-process interactions, new product introduction, and foundry management. He holds 50+ patents and has co-authored over 70 technical papers, primarily focused on semiconductor process technology, device reliability and integration.

Dan explores the approaches used to achieve semiconductor innovation with Milind. The methods and processes applied to advance the state-of-the-art are discussed in detail, across several application areas. It turns out innovation is not driven by “eureka” moments of invention, but rather by focused and sustained work to find the best path forward.

Semiconductor Devices: 3 Tricks to Device Innovation by Milind Welling

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Semiconductor Devices: 3 Tricks to Device Innovation

Semiconductor Devices: 3 Tricks to Device Innovation
by Milind Welling on 09-22-2023 at 8:00 am
Categories: EMD Electronics, Semiconductor Services

Semiconductor Devices 3 Tricks to Device Innovation 1

The semiconductor industry’s incredible juggernaut has been powered by device innovations at its very core. Moreover, present-day enterprises encounter immense competitive pressures and innovations are a key differentiator to maintain their competitive edge1.

“It wasn’t that Microsoft was so brilliant or clever in copying the Mac, it’s that the Mac was a sitting duck for 10 years. That’s Apple’s problem: Their differentiation evaporated.” – Steve Jobs1 in The Rolling Stone interview (1994)

Interestingly, despite innovation being such a key to differentiation and value creation, there can be a wide range in the adoption of new innovations, as seen in Fig. 12.

Figure 1: Typical diffusion and adoption of innovation into industry

Having established how important innovation can be to successful enterprises, let us focus now on the topic at hand – what are those 3 tricks to semiconductor device innovation. Well, sorry to disappoint you but there are actually no easy tricks. And now that I have your attention, let me start by debunking a few myths.

Device Innovation: some True Lies

First, there is nothing magical about semiconductor device innovation. A second myth is that innovation is some sort of a Eureka moment. For thousands of years, humans have believed in the fallacy that innovation occurs like a lightning-strike of brilliance. It is generally believed that: 1) a person must passively wait for breakthrough ideas to hit and cannot take direct control of the creative process; 2) any person lucky enough to receive a significant idea must grab the most benefit possible because lightning-strikes of brilliance may never reoccur; 3) finally, serial innovators and inventive geniuses are rare talents. All these concepts are flawed. Much like other innovations, semiconductor device successes have instead been a product of structured innovation at its best.

Device Innovation: the gift that keeps on giving

Device innovation is often a virtuous cycle of continuous co-optimization of 3 key ingredients: materials, stack/device structure and device electrical operation. You start with materials which determine what is possible. Then you optimize the device structure to build what is manufacturable and finally you tune the electrical operation to ensure that the device stays reliable over its product life. As an example, you can breathe on a wafer and create a native oxide device that can even switch between 2 memory states. Question is whether it will switch reliably over a billion plus cycles and meet present day performance, manufacturability and cost criteria. A structured innovation cycle of co-optimization of these 3 criteria is the methodology that needs to be repeated diligently till the device Key Parametric Indices (KPIs) are met. As an example, Intermolecular has successfully demonstrated use of its device innovation capabilities in such a virtuous cycle to realize many leading-edge memory and selector devices across various materials systems. This wheel of materials and device innovation is illustrated below in Fig. 2 below:

Figure 2: Device innovation powered by co-optimization of materials, electrical operation, and device structure to meet device KPIs.

Its very foundation is the co-optimization of materials, device structure, and device operation which is achieved by rapid combinatorial depositions, advanced physical and electrical characterizations, data analysis to assess device performance and reliability, and an ongoing understanding of mechanisms that drive device behavior.

Semiconductor Devices: The heat is on

Not so surprisingly, technical progress in the semiconductor industry follows a “method to the madness”. For semiconductor products, it starts with an application that drives software and system architecture which in turn drives chip architecture to devices to process integration to materials. For successful device innovations, it is essential to understand the metrics that drive device behavior.  Emerging and leading-edge logic and memory devices are a co-optimization and improvement on the following parameters listed in Table 1:

Table 1: Exemplary leading-edge parameters (KPIs) that drive device innovations

Device innovation: a case study is worth a thousand words

Next, let us review a case study which will further underscore the methodology of co-optimization describe in section 3 to achieve KPIs as illustrated in section 4. A few years ago, a leading-edge memory maker approached Intermolecular to find a selector device that would have best in class performance for all the parameters in Table 1’s emerging selectors column. The material system for this Ovonic Threshold Switch (OTS) diode was expected to be a multinary (3 to 7) chalcogenide elements. While each of those parameters are extremely difficult, a major “stone wall” was a trade-off between leakage (IOFF) and thermal stability (Fig. 3)

Figure 3: Fundamental leakage versus thermal stability trade-off for OTS selectors

The technical team took on this challenge by simultaneously considering and co-optimizing the materials system based on co-ordination number and electrical bandgap, careful management of electrical compliance during operation, leveraging the device structure’s thermal conduction properties, underlying mechanisms understanding and last but not the least, machine learning to leverage the diversity and the quantity of the rich data set. As a result, over a 3 year period, as shown in Fig. 4, the device’s multinary material system was significantly improved to address device level KPIs such as leakage, thermal stability and furthermore, a chip physical design parameter such as threshold voltage drift (VTH).

Figure 4: Optimizing multinary elements (A to E) for device and design KPIs

Systems to chip design to devices to materials: that is how the cookie crumbles

With device innovation at its core, present day technology development focuses on emerging methodologies that extends device and materials technology co-optimization even further to higher orders of abstraction. Such leading edge technology development strategies involve including design interdependencies aka DTCO (Design – Technology Co-optimization) and some are stretching the optimization to include product and systems level careabouts such as with STCO (System – Technology Co-optimization). Following is what our key leading edge customers are highlighting as their focus areas. Fig. 5 shows TSMC’s3 estimates of the increasing DTCO contribution at each node versus traditional scaling that is independent of co-optimization with chip design.

Figure 5: Growing contribution of DTCO vs technology node

Similarly, Micron4 expects improved R&D efficiency and value to their end customers when a wholistic approach to technology optimization includes chip design, packaging and product level interdependencies, as seen in Fig. 6.

Figure 6: Wholistic approach that includes product, design, package, process and device interdependencies for improved R&D efficiency and value generation

Semiconductor Devices: to infinity and beyond

The global semiconductor industry is anticipated to grow to US$1 trillion in revenues by 2030, doubling in this decade5. This will be enabled by innovations in devices and materials at its core. The Roadmaps of the Electronics industry underscore this target rich landscape and a bright future for semiconductor devices. So don’t stop thinking about tomorrow and be a device innovator now and forever. Each one of us will be a contributor to this incredible progress either as the innovator, the maker or perhaps even a user of the semiconductor devices. As these emerging devices not just survive but actually thrive, I invite you to embrace structured innovation and leave Eureka to just being a coastal city in Humboldt County, California.

References:
  1. https://www.rollingstone.com/culture/culture-news/steve-jobs-in-1994-the-rolling-stone-interview-231132/
  2. Silicon Valley Engineering Council (SVEC) Journal, Vol. 2, 2010 pp 38-71.
  3. Mark Liu, TSMC, ISSCC – International Solid-State Circuits Conference, 2021
  4. S Deboer– Micron, Tech Roadmap, November 2020 https://www2.deloitte.com/us/en/pages/technology-media-and-telecommunications/articles/semiconductor-industry-outlook.html

About EMD Electronics
EMD Electronics is the U.S. and Canada electronics business of Merck KGaA, Darmstadt, Germany. EMD Electronics’ portfolio covers a broad range of products and solutions, including high-tech materials and solutions for the semiconductor industry as well as liquid crystals and OLED materials for displays and effect pigments for coatings and cosmetics. Today, EMD Electronics has approximately 2,000 employees around the country, with regional offices in Tempe (AZ) and Philadelphia (PA).
For more information, please visit www.emd-electronics.com.

About Merck KGaA, Darmstadt, Germany
Merck KGaA, Darmstadt, Germany, a leading science and technology company, operates across life science, healthcare, and electronics. More than 64,000 employees work to make a positive difference to millions of people’s lives every day by creating more joyful and sustainable ways to live. From providing products and services that accelerate drug development and manufacturing as well as discovering unique ways to treat the most challenging diseases to enabling the intelligence of devices – the company is everywhere. In 2022, Merck KGaA, Darmstadt, Germany, generated sales of € 22.2 billion in 66 countries. The company holds the global rights to the name and trademark “Merck” internationally. The only exceptions are the United States and Canada, where the business sectors of Merck KGaA, Darmstadt, Germany, operate as MilliporeSigma in life science, EMD Serono in healthcare, and EMD Electronics in electronics. Since its founding in 1668, scientific exploration and responsible entrepreneurship have been key to the company’s technological and scientific advances. To this day, the founding family remains the majority owner of the publicly listed company.

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LIVE WEBINAR: New Standards for Semiconductor Materials

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CEO Interview: Dr. Tung-chieh Chen of Maxeda

CEO Interview: Dr. Tung-chieh Chen of Maxeda
by Daniel Nenni on 09-22-2023 at 6:00 am
Categories: CEO Interviews

Dr. Tung chieh Chen of Maxeda

Dr. Tung-chieh Chen has been serving as the CEO of Maxeda Technology since 2015. In 2021, at DAC, the largest EDA conference, Dr. Chen was honored with the Under-40 Innovators Award in recognition of his exceptional achievements and contributions to EDA development. He is the infrastructure designer of NTUplace, a circuit placer that has won in three top EDA contests: DAC, ICCAD, and ISPD.

In addition to his role at Maxeda, Dr. Chen has held positions as an R&D manager at SpringSoft and Synopsys. He has authored more than 30 EDA papers and holds 14 U.S. patents. Dr. Chen received his Ph.D. degree in Electrical Engineering and Computer Science (EECS) from National Taiwan University (NTU).

Tell us about Maxeda Technology
Maxeda Technology envisions pioneering AI-assisted EDA solutions for the optimization of next-generation chip design. Through close collaboration with partners, we develop validated floorplan and dataflow-analysis tools to support IC design engineers in overcoming design challenges, especially as the design complexity increases along with the macro quantities within the chip. Our clients include several global top 10 fabless companies and some well-known IC design service providers.

What keeps your customers up at night? What problems are you solving?
The semiconductor industry’s growth is driven by the chip requirements of AI/5G and high-performance computing applications, especially as Generative AI attracts increasing attention. Those chips contain millions of components, which results in designs becoming too complex to generate even by experienced engineers.

Therein lies the challenge: the optimized placement of these components is difficult given the huge number of possible placement states. Therefore more iterations are required to optimize the design and this is incredibly time-consuming.

As a consequence, a growing number of IC designers are now considering the incorporation of AI technology, particularly reinforcement learning, in their chip floorplan design process.

Even for a tech giant like Google, it is challenging to integrate Reinforcement Learning into the chip design flow. One reason is the need for more than 100,000 iterations to complete the learning process. Therefore it is an extremely time-consuming method that makes heavy demands on machine resources.

What is the solution Maxeda provided to address the problem and how do you differentiate?
A completely new approach is necessary to apply Reinforcement Learning to chip floorplan design. What is needed are ultra-fast placement and routing, ultra-fast rewards calculation, and a high correlation to final results. Maxeda is collaborating with MediaTek and NTU to develop the MaxPlace™ RL (Reinforcement Learning) Reward Platform to address these demands. Through expedited placement and its strong correlation with rewards, reinforcement learning has proven highly effective in optimizing chip performance, reducing the physical design process from months to just days. What sets this platform apart is its demonstrated performance in actual production.

Existing commercial place and route solutions, which take a completely different approach by aiming for precise placement and routing to meet chip tape-out criteria, are not well-suited for reinforcement learning due to their resource-intensive nature. Hence, no other vendor provides such an effective method for reward calculation.

Figure 1: The MaxPlace™ RL Reward Platform optimizes chip floorplan design.

What are Maxeda’s upcoming plans?
As an EDA company with a vision to develop innovative solutions, Maxeda Technology continues to collaborate closely with partners to develop validated AI-assisted EDA solutions. In Q3 of 2023, we proudly released DesignPlan™, an SoC floorplan exploration tool designed to facilitate block outline and location exploration during the early stages of chip design. Furthermore, we are targeting the development of a completely new AI-assisted verification tool by the end of 2024.

Moreover, we are actively partnering with tier-one foundries to meet the evolving demands of advanced process nodes and navigate the challenges of the post-Moore era. We aim to expand our success from Taiwan to customers worldwide by leveraging this robust partner ecosystem.

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CEO Interview: Koen Verhaege, CEO of Sofics

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Nvidia Number One in 2023

Nvidia Number One in 2023
by Bill Jewell on 09-21-2023 at 8:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services
1 Comment

Nvidia number one in 2023

Nvidia will likely become the largest semiconductor company for the year 2023. We at Semiconductor Intelligence (SC-IQ) estimate Nvidia’s total 2023 revenue will be about $52.9 billion, passing previous number one Intel at an estimated $51.6 billion. Nvidia’s 2023 revenue will be almost double its 2022 revenue on the strength of its processors for artificial intelligence (AI). Intel has been the top semiconductor company for most of the last twenty-one years – except for 2017, 2018 and 2021 when Samsung was number one.

According to its website, Nvidia was founded 30 years ago in 1993 to create 3D graphics ICs for gaming and multimedia. It created the graphics processing unit (GPU) in 1999. Nvidia became involved in artificial intelligence (AI) in 2012. The company became public in 1999. Its revenue for fiscal 1999 was $158 million. Three years later its revenue was $1,369 million, an over eight-fold increase. In fiscal 2023 ended in January, its $27 billion in revenues were split between $15.1 billion in compute & networking and $11.9 billion in graphics.

Despite the fast pace of the semiconductor industry and the numerous startup companies, the top ten companies in 2023 have all been in business at least 30 years. Nvidia is the youngest at 30. Number four Broadcom Inc. is the result of Avago Technologies acquiring Broadcom Corporation in 2015. However, the original Broadcom Corporation was founded 32 years ago. Avago was a spin-off of Hewlett-Packard which entered the semiconductor business 52 years ago.

38-year-old Qualcomm grew to number five primarily through cellphone ICs and licensing revenues. Only Qualcomm’s IC revenues are included in the rankings. Number ten STMicroelectronics was formed in 1987 through the merger of SGS Microelettronica of Italy with Thomson Semiconducuteurs of France. The semiconductor businesses of SGS and Thomson both date back to the 1970s.

Two of the top ten companies were among the industry pioneers about 70 years ago. Texas Instruments was founded in 1930 and entered the semiconductor business in 1954. Infineon Technologies was originally part of Siemens AG, which was founded in 1847. Siemens began producing semiconductors in 1953. Infineon was spun out as a separate company in 1999.

The two South Korean companies, Samsung Electronics and SK Hynix, have over 40 years of semiconductor sales. They became dominant in the memory business after it was largely abandoned by U.S. and Japanese companies (except Micron Technology). SK Hynix was originally Hyundai Electronics which began making semiconductors in 1983. Hyundai merged with LG Semiconductor in 1999 to form Hynix, later SK Hynix.

Intel started 55 years ago and originally sold memory devices. AMD began 54 years ago producing logic ICs. Today the two companies primarily sell microprocessors, together accounting for over 95% of the market for computer microprocessors.

The relative stability of the top semiconductor companies can be seen by comparing the 2023 top ten with 1984, 39 years ago and the year the principal of Semiconductor Intelligence began in semiconductor market analysis. Of the top ten semiconductor companies in 1984, most are still in business today in one form or another. TI was number one in 1984. Since then, TI has narrowed its focus to become primarily an analog company. Number two Motorola split off its discrete business as ON Semiconductor in 1999. ON is now an $8 billion company and acquired industry pioneer Fairchild Semiconductor in 2016. Motorola spun off its IC business as Freescale Semiconductor in 2004. NXP Semiconductors was split off from number seven Philips in 2006. Freescale merged with NXP in 2015. NXP is currently a $13 billion company. Number five National Semiconductor was acquired by TI in 2011. Intel and AMD were number seven and eight, respectively, in 1984. They will be number two and number six in 2023.

Japanese companies were strong in the semiconductor industry in most of the 1980s and 1990s, especially in memory. They were all large, vertically integrated companies. Beginning in the late 1990s these companies began spinning off their semiconductor operations. Renesas Electronics was formed by the merger of the non-memory operations of Hitachi, Mitsubishi, and NEC. Renesas is now a $13 billion company. NEC and Hitachi split off their DRAM businesses in 1999 to form Elpida Memory. Elpida was acquired by Micron Technology in 2013. Toshiba spun off its flash memory business as Kioxia in 2016. Kioxia had over $11 billion in revenue in 2022. Toshiba continues to provide primarily discrete semiconductor devices. Fujitsu divested its IC foundry business in 2014 which was later acquired by UMC. Fujitsu formed a joint venture with AMD for flash memory, Spansion. Spansion merged with Cypress Semiconductor in 2014 and Cypress was acquired by Infineon in 2020.

The relative stability of the semiconductor industry is demonstrated by the market shares of the top ten companies in 1984 and 2023. In 1984 TI had a 9.3% share. In 2023 Nvidia will have about a 10.6% share. The combined market share of the top ten companies in 1984 was 63%. In 2023 it will be about 62%. Although the top companies are relatively stable, the industry has grown from $26 billion in 1984 to $500 billion in 2023, almost a 20-fold increase.

A significant trend since the 1980s has been the rise of fabless semiconductor companies. In 1984 all the top companies had their own wafer fabs. In 2023, three of top ten (Nvidia, Broadcom and Qualcomm) were founded as fabless companies. AMD became fabless in 2008 by spinning off its wafer fabs to what is now GlobalFoundries. Intel, TI, Infineon, and STMicroelectronics all use outside foundries to provide some of their semiconductor manufacturing. The rise of fabless companies was enabled by the founding of major wafer foundry TSMC in 1987, which currently has over 50% of the market. Other significant wafer foundries are Samsung, GlobalFoundries, UMC, and SMIC.

Also Read:

Turnaround in Semiconductor Market

Has Electronics Bottomed?

Semiconductor CapEx down in 2023

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Cadence Tensilica Spins Next Upgrade to LX Architecture

Cadence Tensilica Spins Next Upgrade to LX Architecture
by Bernard Murphy on 09-21-2023 at 6:00 am
Categories: AI, Cadence, EDA, IP

Xtensa LX8 processor

When considering SoC architectures it is easy to become trapped in simple narratives. These assume the center of compute revolves around a central core or core cluster, typically Arm, more recently perhaps a RISC-V option. Throw in an accelerator or two and the rest is detail. But for today’s competitive products that view is a dangerous oversimplification.  Most products must tune for application-dependent performance, battery life, and unit cost. In many systems general purpose CPU cores may still manage control, however the heavy lifting for the hottest applications has moved to proven mainstream DSPs or special purpose AI accelerators. In small, price-sensitive, power-sipping systems, DSPs can also handle control and AI in one core.

When only a DSP can do the job

While general purpose CPUs or CPUs with DSP extensions can handle some DSP processing, they are not designed to handle the high throughput streaming data flows common in a wide range of communications protocols, high quality audio applications, high quality image signal processing, safety-critical Radar and Lidar processing or the neural network processing common in object recognition and classification.

DSPs natively support fixed- and floating-point arithmetic essential for handling analog values that dominate signal processing, and they support massively parallel execution pipelines to accelerate the complex computation through which these values flow (think FFTs and filters for example) while also supporting significant throughput for streaming data. Yet these DSPs are still processors, fully software programmable therefore retaining the flexibility and futureproofing that application developers expect. Which is why, after years of Arm embedded processor ubiquity and the emerging wave of RISC-V options, DSPs still sit at the heart of devices you use every day, including communication, automotive infotainment and ADAS, and home automation. They also support the AI-powered functions within many compact power sensitive devices – smart speakers, smart remotes even smart earbuds, hearing aids, and headphones.

The Tensilica LX series and LX8

The Tensilica Xtensa LX series has offered a stable DSP platform for many years. A couple of stats that were new to me are that Tensilica counts over 60 billion devices shipped around their cores and they are #2 in processor licensing revenue (behind Arm), reinforcing how dominant their solutions are in this space.

Customers depend on the stability of the platform, so Tensilica evolves the architecture slowly; the last release, LX7, was back in 2016. As you might expect, Tensilica ensures that platforms remain compatible with all major OSes, debug tools and ICE solutions, supported by an ecosystem of third-party software/dev tools. The ISA has been extensible from the outset, long before RISC-V emerged while offering the same opportunities for differentiation that are now popular in RISC-V. The platform is aimed very much at embedded applications, delivering high performance at low power.

The latest version in this series, LX8, was released recently and adds two major features to the architecture in support of growing intelligence at the edge, a new L2 memory subsystem and an integrated DMA. I always like looking at features like this in terms of how they enable larger system objectives, so here is my take.

First the L2 cache will improve performance on L1 misses which should translate to higher frames per second rates for object recognition applications, as one example. The L2 can also be partitioned into cache and fixed memory sections, offering application flexibility through optimizing the L2 memory for a variety of workloads. The integrated DMA among other features supports 1D, 2D and 3D transfers, very important in AI functions. 1D could support a voice stream, 2D an image and 3D would be essential for radar/lidar data cubes. This hardware support will further accelerate frame rates. Also, the iDMA in LX8 supports zero value decompression, a familiar need in transferring trained network weights where significant stretches of values may be zeroed either through quantization or pruning and are compressed to something like <12:0> rather than a string of twelve zeroes. This is good for compression, but the expanded structure must be recovered before tensor operations can be applied in inference. Again, hardware assist accelerates that task, reducing latency between updates to the weight matrix.

Not revolutionary changes but essential to product builders who must stay on the leading edge of performance while preserving a low power footprint. Both SK Hynix and Synaptics have provided endorsements. You can read the press release HERE.

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Water Sustainability in Semiconductor Manufacturing: Challenges and Solutions

Water Sustainability in Semiconductor Manufacturing: Challenges and Solutions
by Kalar Rajendiran on 09-20-2023 at 10:00 am
Categories: Mettler-Toledo, Semiconductor Services

Typical on line sensor monitoring points in the semiconductor industry

Water, the planet’s lifeblood, remains a finite and precious resource. The Earth’s total water supply has remained relatively constant over millennia. However, it is the uneven distribution of freshwater and the challenges of providing access to clean water that are causing stress in various parts of the world. Coupled with the growing demands of both human consumption and industrial use, the imperative for quite some time has been, to find innovative ways to balance and sustainably manage water.

Industries are significant water users and consequentially contributors to environmental stress. For example, semiconductor fabs require substantial amounts of water, with some facilities using as much as 460 cubic meters per hour for manufacturing processes. But the semiconductor industry is already a leader in water reclamation and recycling due to its critical need for ultrapure water (UPW). Another reason Fabs invest heavily in water recycling is to reduce the demand on freshwater resources and minimize the discharge of pollutants into the environment. This is not to say that the industry does not face challenges in implementing cost-efficient and effective solutions. Continuous innovation is needed to keep up with the advances in the semiconductor manufacturing processes.

Reclaiming water involves treating and purifying wastewater generated during semiconductor manufacturing processes to restore it to a suitable quality for using again. Recycling water involves collecting and treating various wastewater streams generated within a facility and then repurposing this treated water for use in other processes or areas within the same facility. Reusing water refers to the practice of using treated wastewater for non-critical purposes unrelated to semiconductor manufacturing processes.

Mettler-Toledo recently published a whitepaper that goes into the details of the challenges faced during reclaiming wastewater and recommended solutions to enable water recycling and reusing.

Challenges to Water Reclamation, Recycling and Reuse

Semiconductors are manufactured in a highly controlled environment that demands ultrapure water (UPW) with extremely low levels of impurities. Semiconductor wastewater is characterized by wide disparities in pH, dissolved oxygen (DO), conductivity, total organic carbon (TOC), suspended solids content, and metallic contamination. Finding the right technology to treat such wastewater and ensuring consistent and reliable operation can be challenging. In addition, the industry faces several unique challenges when attempting to implement water reclamation, recycling, and reuse practices due to its stringent water quality requirements and sensitivity to contamination. Even minor variations in water composition can impact the performance and reliability of the equipment, potentially leading to product defects or yield losses. The semiconductor industry also operates under strict environmental regulations, requiring companies to comply with various standards and guidelines.

Continuous innovation and collaboration with technology providers are key to overcoming these challenges and ensuring sustainable water management in semiconductor manufacturing.

Mettler-Toledo’s Solutions

Mettler-Toledo’s analytical measurements provide the semiconductor industry with the critical sensors needed to help continuously measure and control water quality. Conductivity, TOC, temperature, pH, and DO are all measured and controlled continuously. Continuous, real-time monitoring with multi-parameter analytical process sensors is pivotal in achieving effective measurement and control during the water reclaim process. The following Figure shows the typical in-line sensor monitoring and measuring points.

TOC & Conductivity Measurement

Traditionally, semiconductor facilities have used conductivity, pH, and DO to measure and control the waste stream. However, recent advancements in analytical technology, such as Mettler Toledo’s Thornton 6000TOCi Total Organic Carbon sensor and the NEW UPW Unicond Resistivity sensor, have revolutionized the process. TOC measurement is critical for controlling the varying waste streams in real-time, as it immediately detects excursions and allows for quick corrective action. There has been a need for improvement and innovation in resistivity monitoring in UPW when it comes to temperature compensation and signal stability. The NEW UPW Unicond sensor is the breakthrough the industry has been waiting for. It delivers next level stability and accuracy well beyond current industry standards for resistivity.

To learn more details, visit www.mt.com/6000TOCi

To learn more details, visit www.mt.com/upwUniCond

Summary

As the semiconductor industry continues to evolve and develop more advanced technologies, the burden on local water resources and support infrastructures intensifies. This not only poses environmental challenges but also impacts the long-term viability of semiconductor manufacturing in water stressed regions of the world. However, sustainable water management practices and responsible water use can help mitigate these challenges.

Mettler Toledo’s whitepaper provides valuable insights and recommendations to guide this transformation. By prioritizing measurement, control, and improvement in materials reclaim, recycling, and reuse, semiconductor manufacturers can reduce their environmental impact, minimize waste, and contribute to a greener future.

Also Read:

Intel Ushers a New Era of Advanced Packaging with Glass Substrates

The TSMC OIP Backstory

Podcast EP182: The Alphacore/Quantum Leap Solutions Collaboration Explained, with Ken Potts and Mike Ingster

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Has U.S. already lost Chip war to China? Is Taiwan’s silicon shield a liability?

Has U.S. already lost Chip war to China? Is Taiwan’s silicon shield a liability?
by Robert Maire on 09-20-2023 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services
11 Comments

SMIC 7nm
  • Huawei’s 7NM chip? This wasn’t supposed to happen
  • Are Chips a weapon for U.S. or China? Role reversal?
  • Will Taiwan turn from protected asset to unwanted liability?
  • Are sanctions so porous that US has already lost to China?
While EUV is critical to advanced chips there are workarounds

Many people either thought or assumed that lacking EUV scanners would act as a complete roadblock to Chinese semiconductor companies seeking to go beyond 14NM technology. After all, this is obviously the case with Global Foundries in the US which after voluntarily abandoning EUV & R&D has been stuck in the technological dark ages of 14NM.

This has clearly proven to not be the case as Huawei has a new 7NM chip which has (surprisingly) shocked many people. Even without EUV, SMIC has been able to do what Global Foundries (and others) seemingly can’t, that is produce 7NM chips.

You don’t need EUV for 7NM

The mistaken assumption on the part of many in the industry and the US government is that blocking access to EUV scanners would by default limit further progress on Moore’s Law beyond 14NM or 10NM. This is patently untrue…..

The reality is quite different. Back when 7NM was being developed, years ago, EUV technology was a lot less certain than it is today. There were still many questions about its readiness for HVM, and whether it would work as needed at the costs hoped for.

All the major chip makers, TSMC, Intel & Samsung etc; had a “dual path” approach to 7NM, that they worked on in parallel. One path was multi-patterning using dual and quad patterning without EUV at all, and the other path was using EUV. Work on 7NM process started way back in about 2013 long before EUV was a settled issue.

Even after EUV was proven as a viable technology, the dirty little secret in the industry is that a number of chip makers still used multi-patterning at 7NM.

Obviously EUV will be the eventual winner as we progress down Moore’s law so everyone wants to get on board and start using it at 7NM and below.

ASML also made a very strong case that EUV was cheaper and it was obviously less complex with fewer steps in the process flow than multi-patterning…..so the choice to transition to EUV seemed clear.

While its quite clear that EUV has a better, simpler process flow, we are not so sure about it actually being significantly cheaper as ASML suggests as there have been a number of public papers that suggest that multi-patterning at 7NM is cheaper (when we get to 5NM, EUV is definitely cheaper).

SMIC can produce 7NM without EUV

Given that a lot of engineers have left TSMC to go to SMIC and likely taken with them all that they learned at TSMC its no surprise that they have been able to take the non-EUV fork of the dual path approach. Also, when you look at the cost basis, its likely not a significant cost hit to make the chips without EUV. After all a 193 scanner is less than a quarter of the cost of an EUV scanner.

Ex TSMC engineer left TSMC to help SMIC 7NM effort

The only thing we don’t know is how good the yields are…..However, with lots of metrology and inspection tools made by KLAC, NVMI, ONTO etc; which are still shipping into China in huge volumes, they can likely figure out the process over time.

Don’t be surprised when SMIC does 5NM

Yes, you can do 5NM without EUV, which means that SMIC can do 5NM. The process flow does however get quite complex and it will certainly cost more than EUV with likely lower yields. But it is indeed “doable” at some high cost & lower yield.

If you have no other choice and need the technology you will do whatever it takes to get access to that technology.

Given that SMIC has figured out multi-patterning for 7NM they can likely figure it out for 5NM.

Blocking EUV scanners is clearly not enough

SMIC has clearly proven that it can get around the EUV ban. With multi-patterning and enough advanced deposition (ALD) tools, etch tools and metrology/inspection tools.

Applied Materials, Lam, KLA and others are still shipping tons of tools to China which is their largest market by far and growing, as memory has shrunk and TSMC has slowed, China is still buying anything not nailed down and obviously getting enough advanced dep, etch and metrology tools to do 7NM

As we have suggested in the past, the current sanctions are likely very porous. The proof of the porosity is SMIC’s ability to do 7NM which would not be possible without advanced dep, etch & metrology….its just that simple.

In many cases older generation tools are simply no longer made by tool makers and current generation tools may be just “software restricted” to older technology nodes. In many cases the difference between an advanced tool and a less capable tool is just a “software switch”.

In lithography there is a clear, crisp line between EUV and 193, in other tools, not so much. As we have mentioned in the past the only sure way to limit technology is to limit to 200MM (8 inch) rather than 300MM as that is not porous and easily verifiable.

So if we truly want to limit China we need to get serious about sanctions and not put it all on ASML and the scanners.

It would be a lot easier for China to just develop a new litho tool than to have to copy litho, dep, etch & metrology and everything else needed to do 7NM so the real sanction would be across the board.

Has the US already lost the Chip war?

If SMIC is at 7NM, they are likely about 5 years or so behind TSMC and maybe a couple of years behind Intel & Samsung. Already close enough for many applications such as 5G and going to 5NM will get them firmly into AI applications.

So if the goal was to keep China out of 5G and AI, by definition, we have already lost the war.

We lost the war due to lack of resolve and bad technology assumptions….

Will Taiwan become a liability?

We have suggested in prior notes a while ago that China taking over Taiwan would be a “hollow victory” as all someone has to do is drop a grenade or satchel charge in the EUV scanners as they are leaving the fab during the invasion by China. China would thus be left with useless fabs and a somewhat hollow victory.

We think that logic may have already been turned on its head…..

The real question is who needs Taiwan more? The US or China? China now has 7NM (not too far behind Intel). They will likely get 5NM in the not too distant future. They can do 5G and AI with that.

Intel isn’t yet doing real AI and doesn’t have 5G like TSMC does. So if Taiwan were to go away tomorrow the US has no domestic fabs that can do a foundry based AI device nor does its have a 5G foundry device…..China in contrast now has a 5G capable 7NM process and probably 5NM AI capable in the future.

China has been ramping semiconductor capacity in a huge way, the US still hasn’t figured out who gets CHIPS act money and TSMC’s Arizona fab is delayed and Intel doesn’t yet have its foundry act together.

Right now it would be China that would have the advantage in semiconductors. All China would have to do is launch a few low yield missiles into TSMC’s Taiwan fabs and the US and the rest of the world would be screwed while China would not be that bad off as they are essentially cut off from TSMC anyway (so why let the rest of the world get the chips that they can’t have). So who needs Taiwan more?

After the fabs are knocked out, so goes the Taiwanese “silicon shield” as there would be nothing left to protect and Taiwan would become a liability rather than an asset to the US as there would be no semiconductors left to protect and the US government likely doesn’t care about the Taiwanese people just the strategic value of semiconductors to the US and global economies.

You may say….but wait!, there’s still Samsung….and I would say that Samsung’s fabs are just about in artillery or short rocket range of North Korea (China’s puppet & buddy) which would then have similar leverage to China under the control of someone even worse than Xi ……

Not too many good options, no quick fixes, likely a decade or two and more away from the US increasing its long lost semiconductor independence, even if we tripled the CHIPS Act.

For the political, intellectually challenged like Ramaswamy who think the US will be semiconductor independent by 2028, I have a bridge in Brooklyn for sale, cheap……

The stocks

We think that the latest news out of SMIC increase the odds of sanctions being tightened ever further, and not just on ASML, as 7NM has proven that enough other dep, etch & metrology/inspection equipment that is advanced enough is getting into China to produce advanced devices. That means AMAT, KLAC, LRCX in the US and TEL, ASMI and others. We are nearing the one year anniversary of the October sanctions of 2022 and so far its a big fail……as SMIC & Huawei have thumbed their noses at the US.

The down cycle is far from over as TSMC’s recent delay of tools underscores. Memory still sucks, although pricing seems to have bottomed we are a very, very long way from needing to increase memory chip production.

However, the stocks are still near all time highs and the recent ARM IPO was a raging success and likely carried semiconductor valuations which were already high even further.

We still see a lot of risk everywhere and not much of it reflected in semiconductor stocks. We think the ARM IPO while great was more of a sign of “cabin fever” being released on the first big tech IPO in a while with everyone wanting a piece at any price.

We’ll see if the apparent failure of sanctions on the one year anniversary has any reaction…..and what that may be….

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies.
We have been covering the space longer and been involved with more transactions than any other financial professional in the space.
We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors.
We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

SMIC N+2 in Huawei Mate Pro 60

ASML-Strong Results & Guide Prove China Concerns Overblown-Chips Slow to Recover

SEMICON West 2023 Summary – No recovery in sight – Next Year?

Micron Mandarin Memory Machinations- CHIPS Act semiconductor equipment hypocrisy

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Hyperstone Webinar – There’s More to a Storage System Than Meets the Eye

Hyperstone Webinar – There’s More to a Storage System Than Meets the Eye
by Mike Gianfagna on 09-19-2023 at 10:00 am
Categories: Events, Hyperstone GmbH, IP
2 Comments

Hyperstone Webinar There's More to a Storage System Than Meets the Eye

Founded in 1990, Hyperstone is a fabless NAND flash memory controller company enabling safe, reliable and secure storage systems. The company designs, develops and delivers high-quality, innovative semiconductor solutions to enable its customers to produce world-class products for industrial, embedded, automotive and global data storage applications. With a pedigree like this, you can bet the company helped a lot of companies navigate the many choices associated with storage systems. Hyperstone will be presenting an informative webinar on the topic. A link to register for the webinar is coming. Read on to understand why there’s more to a storage system than meets the eye.

The Webinar Presenter

Steffen Allert

Steffen Allert is the webinar presenter. He heads the global sales organization of Hyperstone, orchestrating the company’s worldwide engagements with clients. For almost two decades he has adeptly bridged the gap between customers and engineers, amassing a profound understanding of the intricate nuances and demands intrinsic to storage design.

This experience has given many insights into navigating the conversation around trade-offs between reliability, security, performance, price, and endurance – critical for customers to ensure an optimal storage module. During the webinar, Steffen shares his substantial experience, explaining how storage solution choices can have a profound impact on the overall success of a product.

Many topics are covered by Steffen. The actual webinar title provides a clue about the breadth of the discussion.

Issues in Data Storage? Cyber Security, Data Privacy, AI, Boot Storage, IoT, and Mission Critical Data and Autonomous Driving

 The Webinar Topics

Steffen frames the initial discussion using the “iceberg” graphic shown above. He touches on the clear choices that lie above the water line:

Performance – This is one of the first criteria. Speed is key, but how long can the module hold that performance?

Price – Another top-of-mind item. But what exactly are you paying for?

As we venture below the water line, the topics become more subtle and far-reaching.

Use Case & Reliability – Where will the storage module be integrated? Into what kind of an application? How much storage is needed? Will It be reading or writing data? Is it in operation 24/7 or only occasionally?

Longevity & Supply – Realistically, how long should the end-application be in operation? Are you looking for long-term chip supply (+7 years) or is 2 years before EOL OK?

Your Data’s Value – Have you considered the true value of your data in relation to security or potential power failures? If your company was hacked, or a power outage resulted in a loss of data, what would the consequences be?

What Are You Willing to Trade Off? – You have heard it before, but you can’t have it all. To achieve the optimal solution, you must be prepared to make sacrifices for unnecessary functionality, which in turn allows optimization of other features.

With this setup, Steffen goes through several application examples and use cases to illustrate the options available and how to navigate the choices for an optimal result for the specific product and deployment being developed.  Environmental and quality considerations are also discussed.

Steffen provides a very useful set of questions to be asking as you make your storage system choices and a detailed view of the key trade-offs that impact the final product. Anyone who requires an optimized storage system for their product will get substantial benefit from this webinar.

To Learn More

The webinar will be broadcast on Wednesday, Oct 11, 2023 10:00 AM – 10:30 AM Pacific time. You can register for the webinar here. I highly recommend it. Hyperstone also has a rich download library on their website here. You can find lots of great storage design topics to dig into there. Clearly, there’s more to a storage system than meets the eye.

Also Read: 

Selecting a flash controller for storage reliability

CEO Interview: Jan Peter Berns from Hyperstone