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Semiconductor Expert Forum

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2025 Outlook with Dr. Chouki Aktouf of Innova

2025 Outlook with Dr. Chouki Aktouf of Innova
by Daniel Nenni on 01-14-2025 at 10:00 am
Categories: EDA, Innova

Picture Chouki

Chouki Aktouf is Founder & CEO of Defacto Technologies and Co-Founder of Innova Advanced Technologies.  Prior to founding Defacto in 2003, Dr. Aktouf was an associate professor of Computer Science at the University of Grenoble – France and leader of a dependability research group. He holds a PhD in Electric Engineering from Grenoble University.

Tell us a little bit about yourself and your company. 

As a startup with a unique software offer to manage design flow and more generally design resources (EDA tools, computing servers, IP cores, etc.) Innova’s PDM tool help predict, manage and report  design resources by targeting not only cost but also eco-design compliance.

What was the most exciting high point of 2024 for your company? 

Innova confirmed its unique methodology how procurement and design teams can benefit from its PDM software to predict EDA tools licenses and computing servers for new projects and also how to track and optimize the design resource access by users.

What was the biggest challenge your company faced in 2024? 

In 2024, the challenge for the startup was to convince first users that Innova is a real alternative to old and traditional tools for design flow management with much higher possibilities including customization and a much lower cost.

How is your company’s work addressing this biggest challenge? 

We work closely with leading R&D teams in France and in Europe to help solving technical challenges.

What do you think the biggest growth area for 2025 will be, and why?

We believe AI-based EDA will be the main topic for the coming year

How is your company’s work addressing this growth? 

The company has engaged since several years with best Research labs in Europe to work closely on advanced AI-based technologies for EDA.

What conferences did you attend in 2024 and how was the traffic?

We were a key sponsor of DSD/Euromicro in Paris in August in 2024.

We were invited in the booth of Defacto Technologies at DAC this year. We were happy to be able to present our technology and the traffic was really good. Also, we exhibited at DSD/Euromicro in Paris in August where we presented our new methodology around eco-design and sustainability analysis. This is a small conference compared to DAC but it was fairly good.

Will you attend conferences in 2025? Same or more?

Of course, since we are based in Grenoble, we’ll be attending DATE. Defacto renewed its invitation to have us on their booth so we will be present at DAC also in 2025.

How do customers engage with your company?

The best way is to contact us through our website (https://www.innova-advancedtech.com/formulaire-de-contact).The we have an evaluation package that can be sent anytime. The installation is fast and we use to provide a close support from our AE to optimize the use of our solution and enable the users see the benefits we can bring.

Also Read:

WEBINAR: Reconcile Design Cost Reduction & Eco-design Criteria for Complex Chip Design Projects

Innova at the 2024 Design Automation Conference

INNOVA PDM, a New Era for Planning and Tracking Chip Design Resources is Born

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WEBINAR: Reconcile Design Cost Reduction & Eco-design Criteria for Complex Chip Design Projects

WEBINAR: Reconcile Design Cost Reduction & Eco-design Criteria for Complex Chip Design Projects
by Daniel Nenni on 01-14-2025 at 6:00 am
Categories: EDA, Events, Innova

flow innova2

As chip design complexity keeps increasing, the challenge of managing costs becomes a pressing concern for companies of all sizes. Efficient resource management is emerging as a critical lever for controlling design expenses and ensuring project success.

The chip design market increasingly demands automated solutions for resource prediction, planning, and analysis. Among these, AI-based technologies hold great promises for transforming resource management, enabling companies to make data-driven decisions that optimize their processes.

“How to Track and Predict Design Resources for Complex Chip Design Projects by Including Jointly Cost and Sustainability.”

On January 21st (10:00AM PST).

The Shift to Cloud-Based Computing: Is It Predictable?

Modern chip design trends show an increasing reliance on cloud-based computing servers. Yet, a vital question arises: Can companies accurately predict when to transition from on-premise to cloud-based resources?

INNOVA provides a clear, AI-powered answer through its innovative Project Design Manager (PDM) tool. This solution simplifies three essential steps in resource management:

  1. Model Training – Using historical data to create predictive models.
  2. Model Selection – Identifying the most suitable model for a specific context.
  3. Resource Time Prediction – Forecasting CPU, memory, and disk requirements with precision.

With its robust tracking capabilities, INNOVA’s PDM monitors the usage of critical resources such as EDA tools, servers, libraries, and engineering assets. It seamlessly integrates with existing IT environments and interoperates with standard project, license, and server management tools, ensuring secure and effective operations.

Streamlined Implementation and AI-Driven Predictions

Once installed, INNOVA’s PDM makes resource prediction straightforward. Its intuitive interface allows users—even those without deep AI expertise—to select appropriate ML models, execute predictions, and generate comprehensive reports. These reports compare real-world data with predictions, enabling teams to make informed adjustments to their resource strategies.

Unified Project and Design Management for SoC Design

INNOVA’s Project and Design Management (PDM) platform combines project management, design flows, and resource optimization into a single, unified software environment. Designed for multi-user accessibility, PDM is suited to design project managers, engineers, purchasing teams, and HR departments. Key features include:

  • Scalability and Integration: Easily interfaces with existing information systems and software tools, ensuring consistent data throughout the project lifecycle.
  • Real-Time Synchronization: Keeps design data and flows up to date, offering traceability of resource usage.
  • Interoperability: Bridges software and hardware needs, managing both design licenses and computational servers effectively.

By offering real-time insights and seamless compatibility with existing tools, PDM simplifies the complexities of managing design entities such as projects, data, servers, and licenses.

Driving Sustainability in Chip Design

INNOVA extends its value by integrating sustainability metrics into the design process. PDM evaluates design configurations—encompassing workflows, resources, and power consumption—to ensure eco-compliance. Its automated measures enable users to identify configurations that fulfill sustainability criteria, providing a clear differentiation between eco-friendly and less efficient options.

Through these capabilities, INNOVA empowers organizations to reduce environmental impact while optimizing resource allocation, ensuring that modern chip designs are not only innovative but also sustainable.

Conclusion

INNOVA’s PDM represents a revolutionary step forward in managing the complexity of chip design projects. By combining AI-driven predictions with unified project management and sustainability tools, it addresses the critical challenges of cost reduction, resource optimization, and environmental compliance. With INNOVA, design teams can confidently navigate the demands of modern chip development while achieving their strategic goals.

To explore these advancements further, join INNOVA’s upcoming webinar:

“How to Track and Predict Design Resources for Complex Chip Design Projects by Including Jointly Cost and Sustainability.”

On January 21st (10:00AM PST).

Don’t miss this opportunity to gain valuable insights into sustainable chip design practices. The webinar is held in partnership with SemiWiki and INNOVA.

Register now and the replay will be sent to you if you are not able to attend live.

Also Read:

2025 Outlook with Dr. Chouki Aktouf of Innova

Build a 100% Python-based Design environment for Large SoC Designs

Defacto Technologies and ARM, Joint SoC Flow at #61DAC

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Averting Hacks of PCIe® Transport using CMA/SPDM and Advanced Cryptographic Techniques

Averting Hacks of PCIe® Transport using CMA/SPDM and Advanced Cryptographic Techniques
by Kalar Rajendiran on 01-13-2025 at 10:00 am
Categories: EDA, IP, Security, Siemens EDA

CMA:SPDM Flow for Establishing a Secure Connection

In today’s digital landscape, data security has become an indispensable feature for any data transfer protocol, including Peripheral Component Interconnect Express (PCIe). With the rising frequency and sophistication of digital attacks, ensuring data integrity, confidentiality, and authenticity during PCIe transport is crucial. To address these concerns, technologies like Security Protocol and Data Models (SPDM) have emerged as key enablers for secure communication. Component Measurement and Authentication (CMA) determines how SPDM is applied to PCIe systems. By employing these frameworks alongside advanced cryptographic techniques, such as elliptic curve cryptography (ECC), PCIe systems can safeguard sensitive data against potential threats. Siemens EDA recently published a whitepaper on this very topic.

CMA and SPDM: Foundations of PCIe Security

CMA and SPDM play a vital role in fortifying PCIe connections. Together, they establish secure sessions, authenticate communication endpoints, and facilitate encrypted data exchanges. SPDM achieves these goals by defining a series of messages that enable secure connections between devices. These messages negotiate protocol versions, advertise device capabilities, and determine supported cryptographic algorithms. Handshake secrets are generated using hash functions such as HMAC and HKDF, which are critical for encrypting and decrypting communication. After the successful exchange of SPDM requests, a secure session is established.

Symmetric vs. Asymmetric SPDM Flows

Symmetric Encryption: This method relies on a Pre-Shared Key (PSK) known to both parties before initiating communication.  It is computationally efficient but requires secure key distribution beforehand.

Asymmetric Encryption: Public/private key pairs are used to eliminate the need for pre-shared keys. This approach enables stronger authentication mechanisms, such as digital signatures, ensuring that communication endpoints are verified.

SPDM supports both symmetric and asymmetric encryption flows to establish secure connections. While symmetric encryption is faster and less resource-intensive, asymmetric encryption provides superior security and solves key distribution challenges.

Key Generation and Authentication Techniques

Key generation is an essential part of the SPDM flow, with the Diffie-Hellman Key Exchange (DHE) algorithm playing a central role. The algorithm facilitates secure key exchanges by leveraging shared secrets generated during the handshake process.

Elliptic Curve Cryptography (ECC) enhances the DHE algorithm by performing complex operations on elliptic curves, enabling faster and more secure key generation. Authentication within SPDM is achieved through digital signatures, which validate the origin and integrity of transmitted data. By combining message hashing with encryption using a private key, digital signatures ensure that only authorized entities can participate in communication.

Advantages of Elliptic Curve Cryptography

Elliptic curve cryptography has gained prominence due to its ability to deliver equivalent security to traditional algorithms like RSA while requiring significantly smaller key sizes. This efficiency makes ECC particularly suited for resource-constrained environments like PCIe systems. For example, an ECC 256-bit key provides the same level of security as a 3072-bit RSA key, reducing computational overhead and improving performance. The smaller key sizes also simplify key management and accelerate cryptographic operations, making ECC an attractive choice for modern PCIe security.

Strengthening Security with ECC Algorithms

Elliptic curve cryptography further strengthens the security of PCIe transport by offering computational advantages over conventional methods. Its reliance on solving complex elliptic curve equations makes it resistant to cryptanalysis while reducing processing requirements. This efficiency allows for faster encryption and decryption, as well as quicker digital signature generation. Additionally, ECC’s smaller key sizes make it easier to maintain and manage cryptographic keys, ensuring seamless integration into PCIe systems.

Verification with Siemens VIP for PCIe

To ensure the successful implementation of CMA/SPDM, Siemens Verification IP (VIP) for PCIe provides a comprehensive framework for design verification. This solution is fully compliant with CMA Revision 1.1 and SPDM Version 1.3.0, offering robust testing capabilities for secure PCIe communication. Siemens VIP supports the generation of SPDM messages required to establish secure connections, along with APIs that enable flexible stimulus generation. Users can modify fields to create diverse test cases, covering both positive and negative scenarios.

Error injection and debugging are additional strengths of Siemens VIP, allowing designers to simulate fault conditions and analyze system behavior. The solution also supports both symmetric and asymmetric encryption flows, enabling a wide range of testing scenarios. Algorithms such as secp256r1 and secp384r1 are supported for Diffie-Hellman key generation, while digital signature algorithms like TPM_ALG_ECDSA_ECC_NIST_P256 ensure robust authentication. Moreover, Siemens VIP accommodates various device configurations, making it adaptable to the diverse capabilities advertised by different PCIe components.

Summary

CMA and SPDM provide a robust framework for PCIe security, enabling encrypted communication and authentication between devices. The integration of advanced cryptographic techniques, such as ECC, enhances these protocols by offering efficient and secure key generation, digital signatures, and encryption. Siemens Verification IP for PCIe ensures compliance with these security standards, offering extensive testing and debugging capabilities. Together, these technologies establish a new benchmark for PCIe transport security, protecting sensitive data against emerging threats in the digital age.

The whitepaper can be accessed here.

Also Read:

Reset Domain Crossing (RDC) Challenges

Electrical Rule Checking in PCB Tools

Innexis Product Suite: Driving Shift Left in IC Design and Systems Development

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2025 Outlook with Mahesh Tirupattur of Analog Bits

2025 Outlook with Mahesh Tirupattur of Analog Bits
by Daniel Nenni on 01-13-2025 at 6:00 am
Categories: Analog Bits, IP

Mahesh Tirupattur

Tell us a little bit about yourself and your company. 

Mahesh Tirupattur

I’m Mahesh Tirupattur. I’ve been with the company for over 20 years. Recently I took the role of CEO, where I drive business partnerships, IP licensing, and joint venture development. This change was a mutual decision between Alan Rogers and I. Alan wants to focus on technology innovation and he will be able to do that as President and CTO. I have a vision for taking the company to the next level and I will focus on that in my new role as CEO.

Analog Bits is truly a unique company. Through many customer and foundry partnerships we’ve become the leader at developing and delivering low-power integrated clocking, sensor and interconnect IP that are pervasive in virtually all of today’s semiconductors.

What was the most exciting high point of 2024 for your company? 

This is a difficult one. There were many exciting achievements this past year, both with our foundry partners and our customers. If I had to pick one, I would say the introduction of advanced analog and mixed signal IP at cutting edge technologies. We presented proven results at 3nm, and we are moving to 2nm next.

For many years, analog IP was typically developed in older nodes. There have been many advances over the past few years that have changed this paradigm. Today, sensing and communication must be integrated on-chip with cutting edge technology. Analog Bits has met this challenge with a broad range of IP to address the needs of the latest AI and data center chip designs.

What was the biggest challenge your company faced in 2024? 

The best way to describe this is a multi-dimensional balancing act. We need to deliver high-speed, high-precision IP that runs at the most advanced nodes with the lowest possible power. Achieving that combination requires a lot of analyses and tradeoffs.

How is your company’s work addressing this biggest challenge?  

There are technical achievements that are certainly needed. For example, thermal considerations are top of mind for many design teams. To help with that we’ve developed a comprehensive on-die sensing IP portfolio. This technology helps to manage power, enhance reliability, and improve yield. Timing glitches are also becoming more prevalent in advanced designs. We also have a portfolio of glitch detection IP to address this growing problem. There are many more areas we cover, you get the idea.

But there is also an industry-level shift in thinking that is coming. For a long time, analog IP choices were made at the end of the design process. It was something of an afterthought to finish the design. I liken this to package design. For many years, the package for a monolithic chip was done near the end of the design to finish things up. With the growth of multi-die design, the package team is now an integral part of the system development team – the choices made impact and enable the entire project.

In the new multi-die environment, enabling IP that unlocks optimal power distribution, high-speed communication and eases thermal stress becomes a cornerstone item for system design. This is the IP that Analog Bits provides, and I am making changes to the company’s structure to allow us to be part of the system architecture team, ensuring all demands can be met early in the architectural definition phase. You will be hearing more details of how Analog Bits is moving upstream to address substantial challenges as early as possible.

What do you think the biggest growth area for 2025 will be, and why?

Thanks to the huge increase in data center expansion and AI application development, energy efficiency with superior performance and latency are an absolute requirement. To achieve these requirements, superior clocking, sensing, I/O and SerDes communication are all needed. This will be a big growth area, and these are all sweet spots for Analog Bits.

How is your company’s work addressing this growth? 

Beyond design excellence, we focus on partnering with foundries and leading suppliers. A good example of this is the work we’ve done with Arm.

We worked on several integrated power management and clocking IPs with the company. Arm’s customers can readily use these solutions in N3P and soon in N2P. LDO regulator IPs were also part of the effort to efficiently manage the large absolute and dynamic current supplies to Arm CPU cores.

A case study of how CPU cores seamlessly integrate with Analog Bits LDO and Power Glitch Detector IPs, along with integrated clocking capabilities was presented at TSMC OIP in 2024. The implication of this work is substantial for advanced data center applications.

And our focus on working with system design teams early will clearly have a positive impact as well.

What conferences did you attend in 2024 and how was the traffic?

Beyond the usual industry trade shows such as DAC, Analog Bits supports many of the events of our foundry partners. We attend all the worldwide events for the TSMC Technology Symposium, TSMC OIP Ecosystem Forum, Samsung SAFE Forum, GlobalFoundries Technology Summit and Intel Foundry Services Direct Connect events. Each event brings us closer to key customers and our foundry partners, so we view them as all quite valuable.

Will you attend conferences in 2025? Same or more?

Each event we attended last year allowed us to reach an important segment of our customer base and partner network. I expect we will have a similar program this coming year. You can view the current plans on our website at https://www.analogbits.com/events/.

How do customers engage with your company?

As discussed, we are at a lot of shows. You can come by our booth, get the latest information and start a conversation with us. We also joined the Silicon Catalyst In-Kind Partner Ecosystem last year, so if you’re a startup in that incubator it’s easier to work with us. We also opened a new design center in Prague last year. You can also get things started by dropping a note to info@analogbits.com.

Additional questions or final comments? 

2024 was a great year for Analog Bits and we’re excited to see the expansion on the horizon in 2025. If you’re working on advanced data center or AI applications, things just got a bit easier. If power management, performance or communication are challenges we can help.

Also Read:

Analog Bits Builds a Road to the Future at TSMC OIP

Analog Bits Momentum and a Look to the Future

Analog Bits Enables the Migration to 3nm and Beyond

Podcast EP269: A Broad View of Semiconductor Market Dynamics with Rajiv Khemani

Podcast EP269: A Broad View of Semiconductor Market Dynamics with Rajiv Khemani
by Daniel Nenni on 01-10-2025 at 10:00 am

Dan is joined by Rajiv Khemani, a serial entrepreneur and an industry leader with 25 years of experience in building and scaling businesses. He is currently co-founder & CEO of Auradine. He is also an investor and board member in the data infrastructure, AI and software/platforms space. Previously, Rajiv was co-founder & CEO of Innovium, a leading provider of cloud-optimized network switching solutions that was acquired by Marvell for over $1B in 2021. Prior to that, Rajiv was COO at Cavium, he also worked at Intel, Sun Microsystems & Network Appliance.

In this comprehensive discussion, Dan explores the market dynamics and evolution of the semiconductor ecosystem with Rajiv. How monopolistic tendencies impact the market as well as the growth of AI and the importance of an open ecosystem are discussed. Rajiv provides some growth projections as well as advice to entrepreneurs on how to work with the semiconductor ecosystem. The role of the government to maintain semiconductor innovation in the US is discussed as well with a overview of the benefits and challenges of the CHIPS Act.

Rajiv concludes with a summary of his company, Auradine, which provides semiconductors, systems, and software for block chain and AI infrastructure. Auridine builds products that support innovation, sustainability and scalability. You can learn more about Auradine here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual

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CEO Interview: Dr. Zeynep Bayram of 35ELEMENTS

CEO Interview: Dr. Zeynep Bayram of 35ELEMENTS
by Daniel Nenni on 01-10-2025 at 6:00 am
Categories: CEO Interviews, Semiconductor Services, Silicon Catalyst

Zeynep Bayram headshot

Zeynep is a co-founder and the Chief Executive Officer of 35ELEMENTS Corp., the GaN solutions company, which spun off from the University of Illinois at Urbana Champaign. She worked in small and large semiconductor companies, and managed operations of an equipment manufacturing business. She completed her B.S. and M.S. in EE, from Cornell and Colombia Universities, respectively.

Why did you start 35ELEMENTS?

To help us reach carbon neutrality, we (Zeynep, CEO/CFO, B.S. in EE, Cornell University, M.S. in EE, Columbia University, & Can, CTO, Ph.D. in EECS, Northwestern University) spun off 35ELEMENTS from the University of Illinois at Urbana-Champaign. We discovered that the best semiconductor material for assisting us in achieving carbon neutrality is cubic gallium nitride – a III-V compound semiconductor material which Can has been leading as a faculty member at ECE Illinois for the past eleven years. The purpose of 35ELEMENTS is to expand this novel semiconductor materials technology platform.

Why did you join Silicon Catalyst?

One of our goals is to form strategic alliances with foundries to scale our novel gallium nitride material solutions on CMOS-compatible Si (100) substrates by our target of two years. We plan to accomplish this by working with Silicon Catalyst’s in-kind and strategic partners. The tremendous experience and wide knowledge that the Silicon Catalyst team has is also what drew us to working with them.

What differentiates your company?

The foundation of 35ELEMENTS is the exclusive portfolio of cubic gallium nitride patents covering materials synthesis as well as photonic and electronic devices. We are the only company that can epitaxially hetero-integrate gallium nitride materials on Si (100) substrates that are compatible with CMOS processes and foundries. We make use of an industrious epitaxy tool called metalorganic chemical vapor deposition.

What is 35ELEMENTS’ goal?

35ELEMENTS will offer the fastest and the highest efficiency light emitters in the world, while still on the largest substrate platforms. To facilitate the rapid adoption of solid-state lighting and contribute to the development of the ideal light sources, which will result in even greater energy and environmental savings sooner, our first product will be a technological advancement in solid-state lighting: direct-emitting innovative green light emitting diodes. A ~ $1 trillion in energy savings, in addition to other health advantages like improved mood regulation and eye safety, will be an immediate advantage of our solution.

What new features/technology are you working on?

We see direct applications in augmented and virtual reality displays, digital lighting, optical interconnects, wide bandgap complementary logic functions, and power electronics. The strategic partnerships with CMOS-centric companies will enable our gallium nitride and their silicon solutions on one platform.

What keeps your customers up at night?

In the process of creating human-centered lighting solutions, our customers currently sacrifice form factor, cost, efficiency, and light quality. Consider any lighting application such as headlights, flashlights, displays, signage, lamps, etc. These days, such devices’ efficiency is cut in half, their color spectrum alters, and thermal issues arise when further light output is needed. The existing photonic solutions are not customer-centric.

Also Read:

CEO Interview: Subi Krishnamurthy of PIMIC

CEO Interview: Dr Josep Montanyà of Nanusens

CEO Interview: Marc Engel of Agileo Automation

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2025 Outlook with Matt Burns of Samtec

2025 Outlook with Matt Burns of Samtec
by Daniel Nenni on 01-09-2025 at 10:00 am
Categories: Samtec, Semiconductor Services

Matt Burns Samtec

My good friend Matthew Burns develops go-to-market strategies for Samtec’s Silicon-to-Silicon solutions. Over the course of 25 years, he has been a leader in design, applications engineering, technical sales and marketing in the telecommunications, medical and electronic components industries. Matt holds a B.S. in Electrical Engineering from Penn State University.

Tell us a little bit about yourself and your company.

Samtec is a privately held, global manufacturer of a broad line of high-performance copper, optical, and RF interconnect solutions. Our technical experts around the globe optimize the signal path from the bare die to an interface 100 meters away, and all interconnect points in between. I lead an experienced team of professionals who evangelize the capabilities of Samtec’s Silicon-to-Silicon solutions.

What was the most exciting high point of 2024 for your company?

Throughout the year, Samtec was able to demonstrate the high-speed capabilities of several next-gen interconnect platform solutions. Even at 224 Gbps PAM4 speeds, copper isn’t dead.  Samtec’s Flyover® Next-Gen Systems route data from the ASIC to the front panel (or backplane) via our Eye Speed® Cable Technology. At SC24, we exhibited the latest versions of our Si-Fly® HD co-packaged and near chip systems driven by Synopsys IP with a pre-FEC BER of e-9 over a 40 dB channel. On the optical side, our demonstrated 56 Gbps PAM4 performance of our Halo™ next-gen mid-board optical transceivers.

What was the biggest challenge your company faced in 2024? 

I talked with several colleagues throughout the year. All of us agreed that innovation is speeding up. We anticipate that will continue going forward. The near insatiable demand for GPUs, XPUs, and AI accelerators by the hyperscalers remains the key driving force here. Semiconductor suppliers, IP providers, EDA vendors and interconnect companies like Samtec must meet their design requirements on-time and under budget. That sounds common sensical, but the combined technology required to scale AI at the pace the industry demands is unprecedented.

How is your company’s work addressing this biggest challenge? 

Samtec is innovating faster as well. We are ramping up our engineering hiring. It’s just a necessity. Unique design challenges demand unique interconnect solutions. Our technical experts are improving the SI performance across the new signal channels. We are creating next-gen mated contact systems to enable 224 Gbps PAM4 performance in dense, small footprints. We constantly tweak our twinax cable technology by testing new dielectric materials, improving cable manufacturing, or developing new cable testing techniques. Our SI engineers are always researching the latest laminates to recommend for high-speed or high-frequency design. We work with our partners to squeeze more performance out of simulation tools. The list goes on.

What do you think the biggest growth area for 2025 will be, and why?

In short, we can’t manufacture micro coax and twinax copper cables fast enough. The adoption of Samtec’s Flyover® technology across networking, computing, storage, and AI acceleration platforms throughout data center, supercomputing systems, and semiconductor testing and manufacturing applications continues to be the driver here. We are also seeing increased demand for our growing portfolio mid-board optical transceivers across several applications.

How is your company’s work addressing this growth? 

As mentioned, we continue to invest in innovation. On the copper cable side, we need to find to materials with the lowest dK available. That has led us to researching, developing and finally manufacturing twinax cable based on uniformly foamed dielectrics. Cable diameters need to be smaller, so finding thinner cable wraps is a necessity. We are expanding cable manufacturing globally. Additionally, we have standard cable assemblies, but our customers usually require something unique. We need to balance supporting emerging R+D opportunities while handling high-volume needs of programs already in production. On the optical side, its more of the same story: ramp innovation and ramp production.

What conferences did you attend in 2024 and how was the traffic?

Samtec sponsors, exhibits, and presents at more than 50 tradeshows and conferences annually around the glove.  Some of the shows I attended included OFC, the OCP Global Summit, MemCon, various PCI-SIG DevCons, ECOC, embedded world, SuperComputing (SC24), and the AI Hardware and Edge AI Summit. From Samtec’s perspective and personally, attendance at tradeshows is still on an upward trend. That’s been the case that last few years coming out of the pandemic.  However, I think the accelerating pace of innovation in AI, semiconductors, EDA, optical connectivity, and other high-growth areas are defining this trend.  I expect this to continue into 2025

Will you attend conferences in 2025? Same or more?

Yes, without a doubt. Conference and events are still a great way to meet luminaries, thought leaders, influencers, design engineers and the like. We are still finalizing our 2025 event strategy and scheduling.  Overall, we will probably attend more vents in 2025. We will likely be on par in the Americas and EMEA, while we strategically invest a bit more across Asia.

How do customers engage with your company?

That’s a great question. As I just mentioned, we still meet plenty of new customers as conferences. Engineers can engage with us directly via our global sales team or our global network of approved distributors. Technically, our FAEs, AEs, and SI engineers are only a phone call or e-mail away. Our website – www.samtec.com – is a treasure trove of product information. We are also accessible via our social media channels.

Additional questions or final comments? 

It’s always nice to engage with you and you team, Dan. We always appreciate the opportunity.  I am sure the year ahead will pose many opportunities and challenges. Samtec looks forward to working with our customers and partners to solve their next-gen interconnect challenges.

About Samtec

Founded in 1976, Samtec is much more than just another connector company. We put people first, along with a commitment to exceptional service, quality products and innovative technologies that take the industry further faster. This is enabled by our unique, fully integrated business model, which allows for true collaboration and innovation without the limits of traditional business models.

Also Read:

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

Samtec Demystifies Signal Integrity for Everyone

Samtec Simplifies Complex Interconnect Design with Solution Blocks

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2025 Outlook with Christelle Faucon of Agile Analog

2025 Outlook with Christelle Faucon of Agile Analog
by Daniel Nenni on 01-09-2025 at 6:00 am
Categories: Agile Analog, IP

Agile Analog Christelle Faucon headshot

Tell us a little bit about yourself and your company. 

I was born in France, but I have been living in the Netherlands for two decades. I have worked in the global semiconductor industry for over 25 years. After my Master’s Degree in Electronics Engineering, I started my career as a Design Engineer. Since then I have held senior product and commercial positions, including 10 years at TSMC and 10 years as President of GUC (Global Unichip) Europe. Currently I am the VP of Sales at Agile Analog, the customizable analog IP company.

Agile Analog is revolutionizing the analog IP sector with our expanding portfolio of highly configurable, multi-process analog IP products. The company has developed a unique way to automatically generate analog IP that meet the customer’s exact specifications, for any foundry and on any process. We provide a wide-range of customizable analog IP solutions and subsystems, covering data conversion, power management, IC monitoring, security and always-on IP. Applications include; HPC (High Performance Computing), IoT, AI and security.

What was the most exciting high point of 2024 for your company? 

2024 was an extremely busy time at Agile Analog. Our main focus was on implementing and delivering customer projects. Throughout the year we saw a significant increase in demand for our novel analog IP and we ramped up the number of customer deliveries. There are tier 1 companies that we work with that unfortunately we can’t talk about due to confidentiality, but in March 2024 we were able to announce the completion of our first always-on IP subsystem for XMOS.

We have also strengthened relationships with the major foundries. Partnering with these foundries enables us to access advanced technology PDKs, so we can support customers across the globe who need solutions on advanced nodes. Agile Analog has been a member of the TSMC OIP IP Alliance Program and Intel Foundry IP Alliance Program since 2023. In July 2024 we announced that we had joined the GlobalFoundries GlobalSolutions Ecosystem and delivered our IP to customers on FinFet and FDX processes.

Other company highlights in 2024 included being on the EE Times Silicon 100 list for semiconductor startups worth watching and being selected as a WIRED Trailblazer.

What was the biggest challenge your company faced in 2024? 

2024 was another challenging year across the semiconductor sector, with the ongoing geopolitical turmoil and economic downturn leading to more uncertainty. The impact of this was felt across the entire industry, with many companies frustrated and restricted by reduced budgets. The automotive sector in Europe was particularly badly hit, although Agile Analog’s exposure to this market is small.

How is your company’s work addressing this biggest challenge? 

Agile Analog has continued to drive forward to accelerate the adoption of our unique analog IP. Despite the challenges, we are proud that Agile Analog has grown as a business, achieving our highest number of IP sales and bookings. We work closely with our foundry and industry partners across the globe, and we have seen a surge in demand, especially for our data conversion IP, power management IP and security IP. Our aim is that when chip designers are looking for customizable analog IP then Agile Analog is the company that comes to mind. Our reach is truly global, with increased levels of interest from customers in North America and Asia. In October we announced a collaboration to support the work of the Southern Taiwan IC Design Industry Promotion Center.

What conferences did you attend in 2024 and how was the traffic?

Over the last 12 months the Agile Analog team has taken part in more global semiconductor foundry events than ever before – including the TSMC Technology Symposiums, TSMC OIP Ecosystem Forums, GlobalFoundries Technology Summits, Samsung Foundry Forums and Intel Connect. The audience and flow of traffic at these events have been encouraging. We have enjoyed showcasing our extending range of analog IP solutions, as well as talking with customers and partners about market trends and challenges. These discussions are invaluable as they form part of the decision-making process as we develop our product roadmap.

The Global Semiconductor Alliance (GSA) events have also been very interesting, including those focused on the Women’s Leadership Initiative (WLI). In March I attended the first GSA WLI EMEA event – Women in Semiconductors Conference – at the GSA International Semiconductor Conference in London. Then in October there was the first GSA WLI EMEA lunch and learn event in Munich. It’s great to see such a strong community that supports the career development of women working in the semiconductor industry.

What do you think the industry’s biggest growth areas will be in 2025?

Despite the fact that there are obviously ongoing global challenges, there are still reasons for cautious optimism in the semiconductor industry. AI and data centers have been key areas of interest in 2024, and we expect that these will continue to be the main growth areas in 2025. Indeed, the potential of generative AI has been a recurring talking point and its future impact on the world looks set to be game-changing.

Will you attend conferences in 2025?

In 2025, we will further strengthen our foundry relationships by participating in more of the foundry events. We may also review sector related events such as those focused on AI/Big data.  We really enjoy meeting existing and potential customers and partners face-to-face, so events are important for us.

What will be the main product focus areas for your company in 2025? 

At Agile Analog, our key product related priorities in 2025 will be working on advanced nodes and our security IP. Until now we have not been able to focus enough attention on developing our technology on advanced nodes. In 2025, we are keen to change this. We have exciting plans to collaborate with major foundries, such as TSMC and Samsung Foundry. There is also growing demand for our security IP solutions, especially for anti-tamper applications, so this range of our products will be at the forefront in 2025. As always at Agile Analog, meeting the needs of our customers comes first. We will continue to listen to and support our customers, and share our extensive expertise and experience in order to ensure that we can deliver the very best solutions possible.

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Stanford showcases the first 60 GHz GaN IMPATT Oscillator at IEDM 2024

Stanford showcases the first 60 GHz GaN IMPATT Oscillator at IEDM 2024
by Daniel Nenni on 01-08-2025 at 10:00 am
Categories: Events

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Key takeaways

  • IMPATT (Impact Ionization Avalanche Transit Time) sources operating at millimeter-wave and sub-THz frequencies using GaN technology have the potential to become some of the most powerful high-frequency (RF) generators.
  • At this year’s IEDM, a major breakthrough was reported: a GaN IMPATT RF oscillator achieving 60 GHz oscillation with an output power of 12.7 dBm.
  • The Stanford team, spearheaded the design and fabrication efforts, introducing key process innovations in edge termination, substrate thinning, and device packaging.
  • The QuinStar team contributed by designing the circuit and conducting RF characterization using their industry-standard setup to rigorously evaluate the device’s performance.

Performance comparison for IMPATT technology with various base materials

Gallium nitride (GaN) proves its prominence in high-power high-frequency RF applications due to its superior properties, such as high critical field, high mobility, and high saturation velocity. These merits make GaN a prime candidate for making IMPATT diodes, which promise to offer the best power-frequency performance among solid-state semiconductor RF devices. Theoretical analysis predicts GaN IMPATT diodes can offer a power-frequency product 450 times higher than their silicon counterparts. However, the experimental demonstration of GaN IMPATT diodes has been long hindered by the absence of achieving uniform avalanche. In 2020, an 800 MHz oscillation was observed for the first time in a GaN pn diode, capable of avalanche breakdown. The latest results presented by Stanford University at 2024 IEDM significantly advanced GaN IMPATT technology, reaching 60 GHz oscillation.

IMPATT diodes are such unique devices that they operate in the breakdown regime. For GaN, edge termination structures are vital to prevent field crowding and premature device breakdown. In this work, a 5-degree bevel mesa etch was utilized to ensure a uniform avalanche, verified by the uniform electroluminescence in the device during the unclamped inductive switching test.

5-degree bevel for edge termination and uniform avalanche electroluminescence

It’s worth emphasizing that developing high-performance IMPATT diodes requires much more than just meeting the avalanche requirement. It’s equally important to reduce the parasitic resistance to achieve efficient high-frequency operation and enhance heat dissipation to improve power density and device reliability. To address the above two challenges, the Stanford team, in collaboration with QuinStar Technologies Inc., developed a bulk GaN substrate thinning process and packaged the diode with the integration of a type IIa diamond heat sink.

The thinning process was carefully optimized to thin down bulk GaN substrate from 400 to 20 µm while keeping the avalanche capability in the diodes intact. The total on-resistance was reduced by 54 %, the leakage current remained minimal, and the breakdown voltage was maintained the same after the thinning process.

A specially designed ceramic pill with the integration of a diamond heat sink as the base was utilized to package the diode. This package offered minimal parasitic elements up to W-band operation. The adoption of a diamond heat sink supported the diode to sustain a high input power density of 2.65 MW/cm2 without burn-out.

GaN IMPATT diode with a substrate thickness of 20 µm and a fully-packaged device

The packaged diode was embedded in a waveguide resonant cavity and tested using an industry testbed at QuinStar Inc. The oscillator circuit featured a sliding backshort for impedance tuning. At a biasing current of 17.1 kA/cm2, the diode was capable of delivering a 60.8 GHz oscillation with 12.7 dBm power. This result marks the first GaN IMPATT oscillator reaching V-band operation, showcasing its great potential for mm-wave applications.

RF oscillation characteristics of the GaN IMPATT oscillator and performance benchmark

Looking ahead, there remains significant potential for improvement. Currently, the GaN substrate is the primary contributor to thermal resistance. To overcome this limitation, achieving a flip-chip configuration and enhancing the thermal boundary conductance between the GaN and diamond interface are critical for increasing the thermal capacity of GaN IMPATT diodes. Device-to-circuit co-optimization is another key to boosting the system efficiency and output power. Our next steps will center on electro-thermal co-design to fully unlock GaN’s potential for next-generation IMPATT technology.

The Presenter

Stanford University and QuinStar Technologies Inc. Under the leadership of Prof. Srabanti Chowdhury, the Wide-Bandgap Lab at Stanford has been at the forefront of GaN vertical device innovation. Their recent work on diamond and GaN integration for advanced thermal management has garnered significant attention for pushing performance boundaries.

The IMPATT devices, a core focus of Zhengliang Bian’s research, a Ph.D. student under Prof. Chowdhury, were a central part of this work who presented it at the IEDM this year. Avery Marshall led the circuit design and measurements, working closely with Lissete Zhang and Tracey Lee. Key innovations in edge termination, wafer thinning, heat sinking, and uniquely designed packaging enabled the successful demonstration of this technology, paving the way for a promising roadmap in this field.

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Stochastic Effects Blur the Resolution Limit of EUV Lithography

Stochastic Effects Blur the Resolution Limit of EUV Lithography
by Fred Chen on 01-08-2025 at 6:00 am
Categories: Lithography

Stochastic Effects Blur the Resolution Limit of EUV Lithography

Conventionally, the resolution limit of a lithography system with wavelength l and numerical aperture NA is given by half-pitch = 0.25 wavelength/NA. With the use of EUV lithography, however, electron blur needs to be added [1]. The impact of this blur is to reduce the contrast [2]. Blur reduces the modulation amplitude by a factor of exp(-0.5*(2*pi*blur/pitch)2). Consequently, the normalized image log-slope (NILS) can drop below the target value of 2.0 (10% CD change for 10% dose change).

Another, more serious issue with EUV lithography, has been its stochastic behavior. Ideally, even with blur, we expect a straight-line image to be projected from a straight line on the mask, with smooth edges. In reality, we expect varying blur from electron scattering due to resist inhomogeneity. Besides locally varying blur, the number of absorbed photons per square nm varies according to Poisson statistics (std. dev. = sqrt(mean)). We also expect locally varying electron yield per absorbed EUV photon [3-6]. Thus, the actual image formed will have randomness, or stochasticity.

Figure 1 shows the simulations of scattered electrons are shown for 30 nm, 40 nm, and 50 nm pitches.

Figure 1. Scattered electron density plotted for 30 nm, 40 nm, and 50 nm pitch horizontal lines. Absorbed dose=60 mJ/cm2, resist thickness = pitch, 5/um absorption, 3-5 electrons/absorbed photon, mean blur = 5 nm, blur std. dev. = 1 nm. The pixel size is 1 nm.

The smaller the pitch, the less well-defined the edge. By setting an appropriate threshold to roughly get a half-pitch linewidth, the edge roughness becomes obvious. Also, the tendency to defects is highlighted by the presence of above threshold pixels outside the edge (“bright defect pixels”), and below threshold pixels within the edges (“dark defect pixels”). More defective pixels means more information lost from the image, particularly edge position, and if severe enough, actual resist defects result.

The sum of bright and dark defect pixel % increases with decreasing pitch as expected (Figure 2).

Figure 2. Left: sum of bright defect pixel % of unexposed area and dark defect pixel % of exposed area, as a function of pitch. The effect of reducing the dose is shown for 50 nm pitch. Right: definitions of bright and dark defects.

Since the dark defect pixels dominate, a dose increase should help reduce the defect pixel %. As expected from Poisson statistics, the dose should be inversely proportional to the cube of the pitch. The # of photons absorbed scales with the thickness (proportional to pitch) and the exposed area (proportional to pitch2).

The rapid rise of required dose with decreasing pitch is a burden on EUV system throughput. Also, the resist would need to be changed to accommodate a much different (≥2X!) dose. If the throughput hit is too severe, or the resist dose is too high to accommodate, it can pose a practical resolution limit even though k1>0.25. In the case shown in Figure 3, a dose upper limit of 2x the dose used at 50 nm pitch would put 40 nm pitch as the practical resolution limit.

Figure 3. Projected dose varies as the inverse cube of pitch to preserve the same degree of photon noise. In this example, a dose upper limit of 2x the dose used at 50 nm pitch would put 40 nm pitch as the practical resolution limit.

To sum up, the resolution limit of EUV lithography is not determined by only the factors limiting DUV lithography. Electron blur and stochastic effects need to be considered as well. Due to stochastics, dose is expected to increase significantly as pitch decreases. With smaller pitch, fewer photons are absorbed, and there is more impact from blur. Higher dose impacts throughput, resist choice. Consequently, the practical resolution limit of EUV lithography will depend on dose as well as the resist. It is no surprise to see multipatterning is used for ~30 nm pitch and below [7].

References

[1] G. He et al., “Stochastic EUV Resist Model,” ISEDA 2023, p.477.

[2] B. J. Lin, “Optical Lithography with and without NGL for Single-Digit Nanometer Nodes,” Proc. SPIE 9426, 942602 (2015).

[3] G. Denbeaux et al., “The role of secondary electrons in EUV resist,” EUVL Workshop 2014.

[4] D. F. Ogletree, “X-rays, Electrons and Lithography: Fundamental Processes in Molecular Radiation Chemistry,” EUVL Berkeley 2017.

[5] A. V. Pret et al., ”Modeling and simulation of low-energy electron scattering in organic and inorganic EUV photoresists,” Proc. SPIE 10146, 1014609 (2017).

[6] P. Theofanis et al., “Modeling photon, electron, and chemical interactions in a model hafnium oxide nanocluster EUV photoresist,” Proc. SPIE 11323, 113230I (2020).

[7] Y-J. Mii, “Semiconductor Industry Outlook and New Technology Frontiers,” IEDM 2024 Keynote.

The full video presentation of this article is available here:

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