Solution for PI, TI & SI Issues in 3D-ICs

Solution for PI, TI & SI Issues in 3D-ICs
by Pawan Fangaria on 11-30-2014 at 7:00 pm

As we move towards packing more and more functionalities and increasing densities of SoCs, the power, thermal and signal integrity issues keep on rising. 3D-IC is a great concept to stack multiple dies on top of each other vertically. While it brings lot of avenues to package dies with multiple functions together, it has challenges… Read More


Noise & Reliability of FinFET Designs – Success Stories!

Noise & Reliability of FinFET Designs – Success Stories!
by Pawan Fangaria on 11-01-2014 at 7:00 am

I think by now there has been good level of discussion on FinFET technology at sub-20 nm process nodes and this is an answer to ultra dense, high performance, low power, and billion+ gate SoC designs within the same area. However, it comes with some of the key challenges with respect to power, noise and reliability of the design. A FinFET… Read More


A Deeper Insight into Quantus QRC Extraction Solution

A Deeper Insight into Quantus QRC Extraction Solution
by Pawan Fangaria on 08-14-2014 at 7:00 pm

Last month Cadenceannounced its fastest parasitic extraction tool (minimum 5 times better performance compared to other available tools) which can handle growing design sizes with interconnect explosion, number of parasitics and complexities at advanced process nodes including FinFETs, without impacting accuracy of … Read More


How to meet 3Ps in 3D-ICs with sub-20nm Dies?

How to meet 3Ps in 3D-ICs with sub-20nm Dies?
by Pawan Fangaria on 03-06-2014 at 1:30 am

It feels to be at the top of semiconductor technology by having dies with high density of semiconductor design at sub-20nm technology node stacked together into a 3D-IC to form a complete SoC which can accommodate billions of gates. However there are multiple factors to be looked at in order to make that successful amid often conflicting… Read More


Smart Strategies for Efficient Testing of 3D-ICs

Smart Strategies for Efficient Testing of 3D-ICs
by Pawan Fangaria on 02-12-2014 at 6:30 am

3D-IC has a stack of dies connected and packaged together, and therefore needs new testing strategies other than testing a single die. It’s given that a single defective die can render the whole of 3D-IC unusable, so each die in the stack must be completely and perfectly tested before its entry into that stack. Looking at it from a … Read More


TSMC projects $800 Million of 2.5/3D-IC Revenues for 2016

TSMC projects $800 Million of 2.5/3D-IC Revenues for 2016
by Herb Reiter on 01-27-2014 at 11:00 am

At TSMC’s latest earnings call held mid January 2014, an analyst asked TSMC for a revenue forecast for their emerging 2.5/3D product line. C.C. Wei, President and Co-CEO answered: “800 Million Dollars in 2016 ”. TSMC has demonstrated great vision many times before. For me, an enthusiastic supporter of this technology, this statement… Read More


TSMC: 3D, 450mm, CoWoS and More

TSMC: 3D, 450mm, CoWoS and More
by Paul McLellan on 12-18-2013 at 4:29 pm

The first keynote at the Burlingame 3D conference was by Doug Yu of TSMC. Not surprisingly he was talking about 3D. In particular, TSMC has WLSI technology that they call CoWoS, which stands for chip-on-wafer-on-substrate which pretty much describes how it is built. This is the technology that Xilinx uses for its recently announced… Read More


AMD Goes 3D

AMD Goes 3D
by Paul McLellan on 12-13-2013 at 7:16 pm

I attended the 3D packaging conference in Burlingame this week. The most interesting presentation to me was by Bryan Black of AMD. He argued very convincingly that Moore’s Law is basically over for the PC microprocessor business and the way forward is going to be 3D. AMD are clearly working on all this.

Increased density and… Read More


3D: Atlanta and Burlingame

3D: Atlanta and Burlingame
by Paul McLellan on 12-04-2013 at 12:44 pm

Two conferences on 3D, one just over and one coming up next week. The one that was just over was hosted by Georgia Tech, the 3rd Annual Global Interposer Technology Workshop (GIT). I wasn’t there but my ex-colleague from VLSI Technology Herb Reiter was. Herb has become very much associated with all things 3D since he led the … Read More


3DIC, the World Goes to…Burlingame

3DIC, the World Goes to…Burlingame
by Paul McLellan on 10-23-2013 at 2:09 pm

For the tenth year, the big 3DIC conference takes place in the Hyatt Regency at Burlingame (just south of San Francisco Airport). Officially it is 3D Architectures for Semiconductor Integration and Packaging or ASIP. This year there have already been some significant 3D announcements: TSMC’s 3D program, and Micron’s… Read More