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2015 3D ASIP conference: Thar’s Gold in Them Thar Hills!

2015 3D ASIP conference: Thar’s Gold in Them Thar Hills!
by Bill Martin on 12-27-2015 at 4:00 pm

 Last week I presented at the 3D ASIP EDA Tutorial and attended the Conference. In previous years, leading edge papers were presented from large companies pushing a solution to meet their needs. These companies had the resources and clout to achieve some astounding successes, but the lingering question was: “what other product development companies could achieve this unless the ecosystem would enable with lower risk as well as costs?”

This year’s conference was different. Rather than just large product development companies pushing their latest accomplishments, 4 aspects hit me:


  • Slight language changes used at conference.

    Last year, it was one solution ‘fits all’ (ie Through Silicon Vias “TSVs”) even though several presentations clearly showed that TSVs are costly and may not be suitable for all applications. This year, it was clear that most memory applications were TSV based but others were “TSVless”. Rather than one size fits all, all presenters stated that viable, cheaper alternatives are developed or being developed (application specific packaging).

    Take away: Ecosystem is maturing and companies recognize that one size might be too expensive/complex for many to use. Better to offer different solutions for different end markets.


  • In previous years, only Foundries presented denser system solutions using silicon interposers.

    When a single solution exists, I often question if the end market exists or if it is large enough to support a growing ecosystem. When other competitive solutions enter the market, these new entries validate the market and product space. Similar to the mid 1980’s to mid 1990’ (ASIC ‘hey day’), after VLSI Technology and LSI Logic showed the Cost of Ownership (COO) and improved performance/area from using ASIC designs, any company that produced silicon quickly started offering ASIC solutions using standard cell and/or gate array solutions. At this year’s 3D ASIP conference, BOTH Foundries and OSATs presented solutions that addressed high density packaging. TSMC’s FOWLP as well as Amkor’s SLIM/SLIT offer different capabilities and business models addressing denser, complex packaging.

    Take away: The large ecosystem suppliers are recognizing that complex packaging is a ‘must’ and that to participate in this market, they must establish a presence. This is good news for product developers where competition will produce better and cheaper products for all. The downside, product developers will need to increase their planning analysis before committing expensive resources.


  • DARPA’s DAHI program is not focused solely with commercially available CMOS process nodes (130nm down to 10nm).

    DAHI is mixing various III-V substrate materials into complex 2.5D systems. The IP integrated in their system design are fabricated in the III-V process nodes that did not compromise the IPs’ performances or functionalities. DAHI is choosing the best of each and then integrating into a heterogeneous 2.5D structure.

    Take away: for the leading/bleeding edge; homogeneous CMOS integration was ineffective and ‘boring’.


  • Although not huge, this year’s (pre) registered attendance was equivalent to last year’s registered plus last minute walk in registrations. I do not have the totals but I assume attendance grew.Several attendees mentioned during their introductions that this was their first time attending and they were there to understand available capabilities.

    Take away: Many companies are starting their discovery process and many will use homogeneous 2.5D products/services in the 2016-17 time frames. By 2018, many will start using heterogeneous 2.5D capabilities demonstrated by DARPA’s DAHI program.

    The end consumers will be the benefit from all of these packaging advancements with more powerful, less power hungry, lighter and cheaper products. The future looks bright, LED bright.


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