Silvaco Swallows Invarian

Silvaco Swallows Invarian
by Paul McLellan on 03-20-2015 at 7:00 am

Yesterday, Silvaco announced that it has acquired Invarian Inc. Details of the transaction were not disclosed.

Who is Invarian? They are a recognized leader in block-level to full-chip sign-off analysis for complex, high-performance ICs. Their unique methodology utilizes a parallel architecture and concurrent power-voltage-thermal… Read More


TSMC ♥ UMC?

TSMC ♥ UMC?
by Daniel Nenni on 03-18-2015 at 8:00 pm

The relationship between TSMC and UMC is one of the more interesting ones in the fabless semiconductor ecosystem in my opinion. Both are headquartered in Hsinchu Taiwan and it is very hard to visit one company without seeing the other as they have facilities right across the street from each other. They also share humble beginnings… Read More


Apple Leaks Chip Sources?

Apple Leaks Chip Sources?
by Daniel Nenni on 03-15-2015 at 10:00 pm

Take a look at the figure below and tell me this information did not come from inside Apple. The question is: Was it voluntary or involuntary? Inquiring minds want to know! There are some minor surprises which I will get to in a minute but the actual source information is spot on to what I have heard the past few quarters. This spicy little… Read More


SoCs More Vulnerable to ESD at Lower Nodes

SoCs More Vulnerable to ESD at Lower Nodes
by Pawan Fangaria on 03-11-2015 at 1:00 pm

Electro Static Discharge (ESD) has been a major cause of failures in electronic devices. As the electronic devices have moved towards high density SoCs accommodating ever increasing number of gates at lower process nodes, their vulnerability to ESD effects has only increased. Among the reasons for ESD failures in SoCs, device… Read More


FinFET Design Enablement

FinFET Design Enablement
by Daniel Payne on 03-10-2015 at 1:00 pm

We read about FinFET technology in the semiconductor press daily now, thanks to Intel introducing their TriGate transistors starting in 2011 and creating a race with foundries and IDMs to switch from planar CMOS nodes. To get some perspective about the progress of FinFET IP and EDA tools I spoke with two experts from Synopsys, Swami… Read More


2015, the Year of the Sheep…And the 16nm FPGA

2015, the Year of the Sheep…And the 16nm FPGA
by Paul McLellan on 03-10-2015 at 7:00 am

If you live in California anyway, with its large Asian population, you can’t have helped noticing that it was the Lunar New Year a couple of weeks ago, the start of the year of the sheep. A couple of days after the New Year, Xilinx announced their new families of what they now call FPGAs, 3D ICs and MPSoCs. But which the rest of us … Read More


Exensio: Big Data in the Fab

Exensio: Big Data in the Fab
by Paul McLellan on 03-03-2015 at 7:00 am

For 20 years PDF Solutions have been working with fabs on yield enhancement. Today, they announced their Exensio Platform for big data manufacturing environments. They haven’t really been keeping it a secret and have been talking about it at events since late last year, but it has basically been in stealth mode for the last… Read More


3D-IC: Embedded Passives

3D-IC: Embedded Passives
by Arabinda Das on 03-02-2015 at 1:00 am

IEDM 2014 was held in the second week of December 2014 in San Francisco. The excitement is over now and the dust has settled. Last week, at my leisure, I was glancing through the conference proceedings and short course material from IEDM 2014, when a slide from the 3DIC short course caught my attention. The slide presented below gives… Read More


Who Leads Semiconductor Innovation?

Who Leads Semiconductor Innovation?
by Pawan Fangaria on 02-25-2015 at 5:30 pm

Semiconductor business is highly dependent on technology and that changes very rapidly in the semiconductor space. It’s important to recognize the importance of research and innovation activities in this space. In my last article on 7nm technology node, one respondent commented, very rightly, “It’s important to have competition… Read More


ASML ASyMptotic progress- When will we get to EUV?

ASML ASyMptotic progress- When will we get to EUV?
by Robert Maire on 02-24-2015 at 5:30 pm

  • ASML making progress – but is it fast enough?
  • ASML has missed 10nm , can it catch 7nm? An economic question
  • Day one at SPIE- Better tone than last year but still cautious

1000 simulated wafers versus 700 simulated
At the opening of the SPIE conference ASML announced that TSMC had reached 1000 wafers a day “exposed”
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