Electronic system level (ESL) modeling for system architecture exploration is rapidly gaining momentum. The simulation performance requirements for hardware/software co-design are demanding — an abstract model for SoC IP cores is required. Typically, soft IP will include a number of model configuration parameters. The SoC architect needs to optimize performance, power, and area (PPA) through evaluation of various design alternatives. Some soft IP cores include the capability to define a configurable instruction set architecture (ISA), for optimum performance of specific algorithm code.
ESL-based design is benefiting from several standardization activities. The SystemC language definition has become the norm for model description, driven by the Open SystemC Initiative (OSCI). The definition of a synthesizable SystemC language subset has also guided IP core release — with high-level synthesis support from EDA vendors, SoC designers can realize both efficient model simulation and optimized cell-based implementations. The emphasis on transaction-level modeling (TLM) for core interface abstraction has provided architects with performance insights, without requiring implementation detail. A set of SystemC libraries release by the OSCI as part of the TLM2.0 standard has facilitated SystemC IP model interoperability in a complex verification environment.
Parenthetically, verification engineers approaching ESL model simulation from an RTL background are likely dealing with an unfamiliar time-base representation. SystemC descriptions may be untimed, loosely timed, or approximately timed. A loosely-timed model reflects non-pipelined transactions — e.g., a complete, atomic read/write access operation has a corresponding timing interval, applying a blocking communication interface. In a loosely-timed model, there are two timing points — i.e., start of transaction, end of transaction. An approximately-timed model breaks transactions into individual steps, with a non-blocking interface. For example, in an approximately-timed model, there would be start/end request and start/end response timing points for each operation, which enables pipelined transaction simulation detail.
SoC architects are rapidly adopting ESL modeling for system performance analysis. Yet, power dissipation is also a crucial optimization objective. How does an SoC architect integrate power estimation into the design exploration phase (long before physical implementation), with technology-based accuracy?
I recently had the opportunity to chat with the team at TSMC who are working on this problem. They described a unique and innovative project underway at TSMC with key partners to address the SoC architect’s dilemma. “As much as 50% of the power may be saved if optimization and analysis is done at the early system level, whereas barely 10% or less of the power can be saved through late gate-level optimization. Optimization at the system level gives the earliest opportunity and greatest gain in system low-power design.” they noted.
“Our customers and IP partners approached us, requesting assistance to define an ESL-based power modeling methodology.”, they highlighted.
Initially, I was admittedly a bit surprised at this initiative — however, as they described the TSMC System-PPAmethodology, it became evident to me that TSMC is an ideal innovator to spearhead this activity. TSMC has an extremely close relationship with IP vendors, who develop/qualify/release their designs on TSMC process shuttles.
The TSMC team briefly described the System-PPA IP power model generation flow — please refer to the figure below.
IP vendors typically release a SystemC model for their IP, using an approximate-timing reference. A set of power-state API’s into the model is written. (This is a relatively low resource effort, according to TSMC.) This code is incorporated into the TLM 2.0 wrapper template developed by TSMC. IP power characterization is executed, and a power data look-up table (LUT) with specified PVT conditions is generated. To support this flow, TSMC has developed a Baseline Virtual Platform(BVP), where IP vendors and system developers can plug-in ESL level power models and perform power analysis and optimization using the TSMC-developed Virtual Platform Analyzer.
Cadence/Tensilica, source of configurable DSP cores, and Arteris, source of Network-on-Chip (NoC) IP, have teamed up with TSMC to collaborate on the early System-PPA implementation activity.
The goal of the TSMC System-PPA methodology is to provide a general, extendible TLM2.0 framework, where individual SoC IP cores each include the API wrapper, and can collectively be presented to the Virtual Platform Analyzer application.
TSMC will be collaborating with additional IP partners in the future, and will be working with EDA vendors to help build momentum for this approach.
With today’s system power design requirements, an ESL platform provides the most efficient and effective method for early system architecture exploration. It is essential that power optimization be an integral part of this analysis. TSMC’s System-PPA power modeling methodology enables effective and accurate power analysis during ESL definition.
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