ESL Architectural Power Estimation Support from TSMC — yes, TSMC

ESL Architectural Power Estimation Support from TSMC — yes, TSMC
by Tom Dillinger on 09-22-2016 at 11:00 am

Electronic system level (ESL) modeling for system architecture exploration is rapidly gaining momentum. The simulation performance requirements for hardware/software co-design are demanding — an abstract model for SoC IP cores is required. Typically, soft IP will include a number of model configuration parameters.… Read More


Multi-level abstraction accelerates verification turnaround

Multi-level abstraction accelerates verification turnaround
by Pawan Fangaria on 05-02-2013 at 8:30 pm

Often a question is raised about how SystemC improves verification time when the design has to go through RTL in any case. A simple answer is that with SystemC, designs can be described at a higher level of abstraction and then automatically synthesized to RTL. When the hands-on design and verification activity is at a higher level,… Read More